From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5827C2D0A3 for ; Mon, 26 Oct 2020 11:01:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 86B1D22263 for ; Mon, 26 Oct 2020 11:01:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1773043AbgJZLBm (ORCPT ); Mon, 26 Oct 2020 07:01:42 -0400 Received: from inva020.nxp.com ([92.121.34.13]:48050 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1772894AbgJZLBl (ORCPT ); Mon, 26 Oct 2020 07:01:41 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A0DEE1A0C41; Mon, 26 Oct 2020 12:01:40 +0100 (CET) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 934611A0C33; Mon, 26 Oct 2020 12:01:40 +0100 (CET) Received: from localhost (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 7DF2720308; Mon, 26 Oct 2020 12:01:40 +0100 (CET) Date: Mon, 26 Oct 2020 13:01:40 +0200 From: Abel Vesa To: Lucas Stach Cc: Shawn Guo , Rob Herring , NXP Linux Team , Fabio Estevam , Frieder Schrempf , Marek Vasut , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: Re: [PATCH 10/11] arm64: dts: imx8mm: add GPC node and power domains Message-ID: <20201026110140.2m7it3atlgrp5qrt@fsr-ub1664-175> References: <20200930155006.535712-1-l.stach@pengutronix.de> <20200930155006.535712-11-l.stach@pengutronix.de> <20201026105622.iqt6cej3iqog57jd@fsr-ub1664-175> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201026105622.iqt6cej3iqog57jd@fsr-ub1664-175> User-Agent: NeoMutt/20180622 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 20-10-26 12:56:22, Abel Vesa wrote: > On 20-09-30 17:50:05, Lucas Stach wrote: > > This adds the DT nodes to describe the power domains available on the > > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > > domain setups, as there is now a hierarchy of domains where complete > > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also > > fine granular gating within those subsystems is possible. > > > > Note that this is still incomplete, as both VPU and DISP domains are > > missing their reset clocks. Those aren't directly sourced from the CCM, > > but have another level of clock gating in the BLKCTL of those domains, > > which needs a separate driver. > > > > Signed-off-by: Lucas Stach > > --- > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > index 76f040e4be5e..a841fb2d0458 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > @@ -4,6 +4,8 @@ > > */ > > > > #include > > +#include > > +#include > > Needs to be imx8mm-reset.h, as in 8MM, not 8MQ. > Actually, now I see what you've done here. You want to use the IMX8MQ_RESET_GPU_RESET. But I think we should avoid having reset IDs shared between i.MX8M platforms. I'll try to find another way around this myself. > > #include > > #include > > #include > > @@ -547,6 +549,61 @@ > > interrupts = ; > > #reset-cells = <1>; > > }; > > + > > + gpc: gpc@303a0000 { > > + compatible = "fsl,imx8mm-gpc"; > > + reg = <0x303a0000 0x10000>; > > + interrupt-parent = <&gic>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + > > + pgc { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + pgc_hsiomix: power-domain@0 { > > + #power-domain-cells = <0>; > > + reg = ; > > + clocks = <&clk IMX8MM_CLK_USB_BUS>; > > + }; > > + > > + pgc_pcie: power-domain@1 { > > + #power-domain-cells = <0>; > > + reg = ; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg1: power-domain@2 { > > + #power-domain-cells = <0>; > > + reg = ; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg2: power-domain@3 { > > + #power-domain-cells = <0>; > > + reg = ; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_gpumix: power-domain@4 { > > + #power-domain-cells = <0>; > > + reg = ; > > + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > + <&clk IMX8MM_CLK_GPU_AHB>; > > + }; > > + > > + pgc_gpu: power-domain@5 { > > + #power-domain-cells = <0>; > > + reg = ; > > + clocks = <&clk IMX8MM_CLK_GPU_AHB>, > > + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > + <&clk IMX8MM_CLK_GPU2D_ROOT>, > > + <&clk IMX8MM_CLK_GPU3D_ROOT>; > > + resets = <&src IMX8MQ_RESET_GPU_RESET>; > > + power-domains = <&pgc_gpumix>; > > + }; > > + }; > > + }; > > }; > > > > aips2: bus@30400000 { > > -- > > 2.20.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBA9FC2D0A3 for ; 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bh=XkLL6tYFK8Z00pAqmDx2AenqirxclEyG9KYPUNWuPKA=; b=x4OCP1er0pZ5DdwTMSImb8ugS OWobY1bM09mLl/dtdJ5AQKwmpjXiivrwpSVHNRo3sA1MIqiVnttlfUviMhrEvbs+3yCOYkvQi+nxx j4xQhy+jiYhWcoRi4VJ8lzIS3soTjsocmthRKnieRUXjnOqKt740V60xmQHc4Gd7efIhpYmwHayUf XofiVr+uFI5CQS7zNUBgYMg2JfVHQs7ZzurTleJrCx9YyljmgnrssgEg2b8+SmVn5ocIYfv9pByvY JP8z5iOg7Lpd40pIlyH8dG13WCC9DuygEWqYdTUeiKZ+Cn7Yx2DvHSTGkIn7DMOywpFCkUWE/WCeq VE2FJN+VQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kX0Ge-0003tk-8O; Mon, 26 Oct 2020 11:02:24 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kX0Fy-0003WU-QU for linux-arm-kernel@lists.infradead.org; Mon, 26 Oct 2020 11:01:43 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A0DEE1A0C41; Mon, 26 Oct 2020 12:01:40 +0100 (CET) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 934611A0C33; Mon, 26 Oct 2020 12:01:40 +0100 (CET) Received: from localhost (fsr-ub1664-175.ea.freescale.net [10.171.82.40]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 7DF2720308; Mon, 26 Oct 2020 12:01:40 +0100 (CET) Date: Mon, 26 Oct 2020 13:01:40 +0200 From: Abel Vesa To: Lucas Stach Subject: Re: [PATCH 10/11] arm64: dts: imx8mm: add GPC node and power domains Message-ID: <20201026110140.2m7it3atlgrp5qrt@fsr-ub1664-175> References: <20200930155006.535712-1-l.stach@pengutronix.de> <20200930155006.535712-11-l.stach@pengutronix.de> <20201026105622.iqt6cej3iqog57jd@fsr-ub1664-175> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201026105622.iqt6cej3iqog57jd@fsr-ub1664-175> User-Agent: NeoMutt/20180622 X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201026_070143_129488_BFE2157C X-CRM114-Status: GOOD ( 23.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , devicetree@vger.kernel.org, Shawn Guo , Frieder Schrempf , patchwork-lst@pengutronix.de, Rob Herring , NXP Linux Team , kernel@pengutronix.de, Fabio Estevam , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 20-10-26 12:56:22, Abel Vesa wrote: > On 20-09-30 17:50:05, Lucas Stach wrote: > > This adds the DT nodes to describe the power domains available on the > > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > > domain setups, as there is now a hierarchy of domains where complete > > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also > > fine granular gating within those subsystems is possible. > > > > Note that this is still incomplete, as both VPU and DISP domains are > > missing their reset clocks. Those aren't directly sourced from the CCM, > > but have another level of clock gating in the BLKCTL of those domains, > > which needs a separate driver. > > > > Signed-off-by: Lucas Stach > > --- > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > index 76f040e4be5e..a841fb2d0458 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > @@ -4,6 +4,8 @@ > > */ > > > > #include > > +#include > > +#include > > Needs to be imx8mm-reset.h, as in 8MM, not 8MQ. > Actually, now I see what you've done here. You want to use the IMX8MQ_RESET_GPU_RESET. But I think we should avoid having reset IDs shared between i.MX8M platforms. I'll try to find another way around this myself. > > #include > > #include > > #include > > @@ -547,6 +549,61 @@ > > interrupts = ; > > #reset-cells = <1>; > > }; > > + > > + gpc: gpc@303a0000 { > > + compatible = "fsl,imx8mm-gpc"; > > + reg = <0x303a0000 0x10000>; > > + interrupt-parent = <&gic>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + > > + pgc { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + pgc_hsiomix: power-domain@0 { > > + #power-domain-cells = <0>; > > + reg = ; > > + clocks = <&clk IMX8MM_CLK_USB_BUS>; > > + }; > > + > > + pgc_pcie: power-domain@1 { > > + #power-domain-cells = <0>; > > + reg = ; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg1: power-domain@2 { > > + #power-domain-cells = <0>; > > + reg = ; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg2: power-domain@3 { > > + #power-domain-cells = <0>; > > + reg = ; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_gpumix: power-domain@4 { > > + #power-domain-cells = <0>; > > + reg = ; > > + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > + <&clk IMX8MM_CLK_GPU_AHB>; > > + }; > > + > > + pgc_gpu: power-domain@5 { > > + #power-domain-cells = <0>; > > + reg = ; > > + clocks = <&clk IMX8MM_CLK_GPU_AHB>, > > + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > + <&clk IMX8MM_CLK_GPU2D_ROOT>, > > + <&clk IMX8MM_CLK_GPU3D_ROOT>; > > + resets = <&src IMX8MQ_RESET_GPU_RESET>; > > + power-domains = <&pgc_gpumix>; > > + }; > > + }; > > + }; > > }; > > > > aips2: bus@30400000 { > > -- > > 2.20.1 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel