From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86DD3C55179 for ; Tue, 27 Oct 2020 17:13:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A54A21D24 for ; Tue, 27 Oct 2020 17:13:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603818784; bh=dvIZLbACW+xwduXQBY5j9WoNudiInwnxg8U3A+qjvdc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=rNadXKgT0SN8Fd6Udt2rgbVPCCFj4WnWvnHZHYeyzCgMmCDIMjeEDRpwq7CAm5Zgx /xv5OW8kPvIhsdPSp/EknGHJtCEbnQDOzL7bCRlbNL6TJ9gREok0QxFM7o23xYlUPB 8qaF89vI4k/dP9MEPe8oIEvGha8cgtoEyypSyKBw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1784757AbgJ0O7l (ORCPT ); Tue, 27 Oct 2020 10:59:41 -0400 Received: from mail.kernel.org ([198.145.29.99]:51126 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1773192AbgJ0Ovn (ORCPT ); Tue, 27 Oct 2020 10:51:43 -0400 Received: from localhost (83-86-74-64.cable.dynamic.v4.ziggo.nl [83.86.74.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id BBF9A207DE; Tue, 27 Oct 2020 14:51:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603810302; bh=dvIZLbACW+xwduXQBY5j9WoNudiInwnxg8U3A+qjvdc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bT11fkTw2SFxjEgXtLBji1usA2ct+oGA2fSqlDGH7yuHxGuolOKNBclOjunVzwWVs ztibfVUmBM+oR43q1vjGlBNyH+A9zs1pyLNJRkvxIHrarX+HuMprrdwLRZrwHdQdEA wm19KfUIAjxisozZ1uZi+UXEXJokm0bVQDF+4cuo= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Julien Thierry , Alexandru Elisei , Julien Thierry , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Catalin Marinas , Will Deacon , Sasha Levin , Sumit Garg Subject: [PATCH 5.8 092/633] arm64: perf: Add missing ISB in armv8pmu_enable_counter() Date: Tue, 27 Oct 2020 14:47:15 +0100 Message-Id: <20201027135527.017508351@linuxfoundation.org> X-Mailer: git-send-email 2.29.1 In-Reply-To: <20201027135522.655719020@linuxfoundation.org> References: <20201027135522.655719020@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alexandru Elisei [ Upstream commit 490d7b7c0845eacf5593db333fd2ae7715416e16 ] Writes to the PMXEVTYPER_EL0 register are not self-synchronising. In armv8pmu_enable_event(), the PE can reorder configuring the event type after we have enabled the counter and the interrupt. This can lead to an interrupt being asserted because of the previous event type that we were counting using the same counter, not the one that we've just configured. The same rationale applies to writes to the PMINTENSET_EL1 register. The PE can reorder enabling the interrupt at any point in the future after we have enabled the event. Prevent both situations from happening by adding an ISB just before we enable the event counter. Fixes: 030896885ade ("arm64: Performance counters support") Reported-by: Julien Thierry Signed-off-by: Alexandru Elisei Tested-by: Sumit Garg (Developerbox) Cc: Julien Thierry Cc: Will Deacon Cc: Mark Rutland Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Cc: Catalin Marinas Link: https://lore.kernel.org/r/20200924110706.254996-2-alexandru.elisei@arm.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- arch/arm64/kernel/perf_event.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 581602413a130..c26d84ff0e224 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -510,6 +510,11 @@ static u32 armv8pmu_event_cnten_mask(struct perf_event *event) static inline void armv8pmu_enable_counter(u32 mask) { + /* + * Make sure event configuration register writes are visible before we + * enable the counter. + * */ + isb(); write_sysreg(mask, pmcntenset_el0); } -- 2.25.1