From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04111C388F7 for ; Thu, 29 Oct 2020 00:55:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AD15420791 for ; Thu, 29 Oct 2020 00:55:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726498AbgJ2Azr (ORCPT ); Wed, 28 Oct 2020 20:55:47 -0400 Received: from mail.kernel.org ([198.145.29.99]:60520 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731657AbgJ1WRk (ORCPT ); Wed, 28 Oct 2020 18:17:40 -0400 Received: from gaia (unknown [95.145.162.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 02C65246AE; Wed, 28 Oct 2020 11:12:07 +0000 (UTC) Date: Wed, 28 Oct 2020 11:12:04 +0000 From: Catalin Marinas To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Qais Yousef , Suren Baghdasaryan , kernel-team@android.com Subject: Re: [PATCH 2/6] arm64: Allow mismatched 32-bit EL0 support Message-ID: <20201028111204.GB13345@gaia> References: <20201027215118.27003-1-will@kernel.org> <20201027215118.27003-3-will@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201027215118.27003-3-will@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On Tue, Oct 27, 2020 at 09:51:14PM +0000, Will Deacon wrote: > +static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) > +{ > + return has_cpuid_feature(entry, scope) || __allow_mismatched_32bit_el0; > +} > + > static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) > { > bool has_sre; > @@ -1803,7 +1851,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .desc = "32-bit EL0 Support", > .capability = ARM64_HAS_32BIT_EL0, > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > - .matches = has_cpuid_feature, > + .matches = has_32bit_el0, Ah, so this one reports 32-bit EL0 support even if no CPU actually supports 32-bit (passing the command line option on TX2 would come up with 32-bit EL0 in dmesg). I'd rather hide the .desc above and print the information elsewhere when have at least one CPU supporting this. -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 911D2C4363A for ; Wed, 28 Oct 2020 11:12:43 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 089B424671 for ; Wed, 28 Oct 2020 11:12:42 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="cGxOzNSt" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 089B424671 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=80PAtNQ+l/G96C2ksIb87RqbMXmDuM671C75NLAYIxI=; b=cGxOzNStsCiC+LNAEaexTIWlf wmlthgeu9JVoKjoekUS0XWOxDf5l8Q5gR0kxQLOXnxXlKJaDaxT8f0BK6TPLqHNXgHUjD1EMKMR2v ysgWJ6V0HczySj88dufY/DDATvsQWruUZAtJjerGWyCrCzeLg5/KJU1zBbgykKeN5/CFmaVqlQ8KL GVMQ1/EGzdfx/Un99BvYTDqlZpCAIzYU864HoIBDRPM1J0a+U5qUccmAtb4+kKYo1t3qtg+QrmdO7 IM3Ath99oBkoyXfbtUNhhegwvNvdMMQ9625n9MD1aeDPF8XYTL9YWpNSk6ZNBrr75ucbI9fuFNJw4 NP6I6mCKQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXjNG-00056n-Eo; Wed, 28 Oct 2020 11:12:14 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXjND-00055d-Ia for linux-arm-kernel@lists.infradead.org; Wed, 28 Oct 2020 11:12:12 +0000 Received: from gaia (unknown [95.145.162.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 02C65246AE; Wed, 28 Oct 2020 11:12:07 +0000 (UTC) Date: Wed, 28 Oct 2020 11:12:04 +0000 From: Catalin Marinas To: Will Deacon Subject: Re: [PATCH 2/6] arm64: Allow mismatched 32-bit EL0 support Message-ID: <20201028111204.GB13345@gaia> References: <20201027215118.27003-1-will@kernel.org> <20201027215118.27003-3-will@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201027215118.27003-3-will@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201028_071211_730400_F9AF2DD6 X-CRM114-Status: GOOD ( 14.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, kernel-team@android.com, Peter Zijlstra , Marc Zyngier , Qais Yousef , Greg Kroah-Hartman , Suren Baghdasaryan , Morten Rasmussen , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Oct 27, 2020 at 09:51:14PM +0000, Will Deacon wrote: > +static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) > +{ > + return has_cpuid_feature(entry, scope) || __allow_mismatched_32bit_el0; > +} > + > static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) > { > bool has_sre; > @@ -1803,7 +1851,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .desc = "32-bit EL0 Support", > .capability = ARM64_HAS_32BIT_EL0, > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > - .matches = has_cpuid_feature, > + .matches = has_32bit_el0, Ah, so this one reports 32-bit EL0 support even if no CPU actually supports 32-bit (passing the command line option on TX2 would come up with 32-bit EL0 in dmesg). I'd rather hide the .desc above and print the information elsewhere when have at least one CPU supporting this. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel