From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BFF5C55179 for ; Thu, 29 Oct 2020 00:53:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C884E20790 for ; Thu, 29 Oct 2020 00:53:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731716AbgJ1WTW (ORCPT ); Wed, 28 Oct 2020 18:19:22 -0400 Received: from mail.kernel.org ([198.145.29.99]:60530 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731736AbgJ1WRn (ORCPT ); Wed, 28 Oct 2020 18:17:43 -0400 Received: from gaia (unknown [95.145.162.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A8CC8246CE; Wed, 28 Oct 2020 11:49:48 +0000 (UTC) Date: Wed, 28 Oct 2020 11:49:46 +0000 From: Catalin Marinas To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Qais Yousef , Suren Baghdasaryan , kernel-team@android.com Subject: Re: [PATCH 2/6] arm64: Allow mismatched 32-bit EL0 support Message-ID: <20201028114945.GE13345@gaia> References: <20201027215118.27003-1-will@kernel.org> <20201027215118.27003-3-will@kernel.org> <20201028111204.GB13345@gaia> <20201028111713.GA27927@willie-the-truck> <20201028112206.GD13345@gaia> <20201028112343.GD27927@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201028112343.GD27927@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On Wed, Oct 28, 2020 at 11:23:43AM +0000, Will Deacon wrote: > On Wed, Oct 28, 2020 at 11:22:06AM +0000, Catalin Marinas wrote: > > On Wed, Oct 28, 2020 at 11:17:13AM +0000, Will Deacon wrote: > > > On Wed, Oct 28, 2020 at 11:12:04AM +0000, Catalin Marinas wrote: > > > > On Tue, Oct 27, 2020 at 09:51:14PM +0000, Will Deacon wrote: > > > > > +static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) > > > > > +{ > > > > > + return has_cpuid_feature(entry, scope) || __allow_mismatched_32bit_el0; > > > > > +} > > > > > + > > > > > static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) > > > > > { > > > > > bool has_sre; > > > > > @@ -1803,7 +1851,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > > > > > .desc = "32-bit EL0 Support", > > > > > .capability = ARM64_HAS_32BIT_EL0, > > > > > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > > > > > - .matches = has_cpuid_feature, > > > > > + .matches = has_32bit_el0, > > > > > > > > Ah, so this one reports 32-bit EL0 support even if no CPU actually > > > > supports 32-bit (passing the command line option on TX2 would come up > > > > with 32-bit EL0 in dmesg). I'd rather hide the .desc above and print the > > > > information elsewhere when have at least one CPU supporting this. > > > > > > Yeah, the problem is if a CPU with 32-bit EL0 support was late-onlined, > > > then we would have 32-bit support, so I think this is an oddity that you > > > get when the command line is passed. That said, I could nobble .desc and > > > print it from the .matches function, with a slightly different message > > > when the command line is passed. > > > > I think we could do a pr_info_once() in update_32bit_cpu_features(). > > Is that called on a system with one CPU? Ah, it's not. Anyway, I see your reasoning behind the late CPUs but I don't particularly like abusing the cpufeature support to pretend a SYSTEM_FEATURE is available before knowing any CPU has it (maybe we do it in other cases, I haven't checked). Could we not instead add a new feature for asymmetric support that's defined as ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE? This would be allowed for late CPUs and we keep the system_supports_32bit_el0() unchanged. -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B6AAC4363A for ; Wed, 28 Oct 2020 11:50:33 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 11186246CB for ; Wed, 28 Oct 2020 11:50:33 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXjxk-0003GO-NU; Wed, 28 Oct 2020 11:49:56 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXjxf-0003FW-M5 for linux-arm-kernel@lists.infradead.org; Wed, 28 Oct 2020 11:49:54 +0000 Received: from gaia (unknown [95.145.162.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A8CC8246CE; Wed, 28 Oct 2020 11:49:48 +0000 (UTC) Date: Wed, 28 Oct 2020 11:49:46 +0000 From: Catalin Marinas To: Will Deacon Subject: Re: [PATCH 2/6] arm64: Allow mismatched 32-bit EL0 support Message-ID: <20201028114945.GE13345@gaia> References: <20201027215118.27003-1-will@kernel.org> <20201027215118.27003-3-will@kernel.org> <20201028111204.GB13345@gaia> <20201028111713.GA27927@willie-the-truck> <20201028112206.GD13345@gaia> <20201028112343.GD27927@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201028112343.GD27927@willie-the-truck> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201028_074951_845650_D729A097 X-CRM114-Status: GOOD ( 27.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, kernel-team@android.com, Peter Zijlstra , Marc Zyngier , Qais Yousef , Greg Kroah-Hartman , Suren Baghdasaryan , Morten Rasmussen , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 28, 2020 at 11:23:43AM +0000, Will Deacon wrote: > On Wed, Oct 28, 2020 at 11:22:06AM +0000, Catalin Marinas wrote: > > On Wed, Oct 28, 2020 at 11:17:13AM +0000, Will Deacon wrote: > > > On Wed, Oct 28, 2020 at 11:12:04AM +0000, Catalin Marinas wrote: > > > > On Tue, Oct 27, 2020 at 09:51:14PM +0000, Will Deacon wrote: > > > > > +static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) > > > > > +{ > > > > > + return has_cpuid_feature(entry, scope) || __allow_mismatched_32bit_el0; > > > > > +} > > > > > + > > > > > static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) > > > > > { > > > > > bool has_sre; > > > > > @@ -1803,7 +1851,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > > > > > .desc = "32-bit EL0 Support", > > > > > .capability = ARM64_HAS_32BIT_EL0, > > > > > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > > > > > - .matches = has_cpuid_feature, > > > > > + .matches = has_32bit_el0, > > > > > > > > Ah, so this one reports 32-bit EL0 support even if no CPU actually > > > > supports 32-bit (passing the command line option on TX2 would come up > > > > with 32-bit EL0 in dmesg). I'd rather hide the .desc above and print the > > > > information elsewhere when have at least one CPU supporting this. > > > > > > Yeah, the problem is if a CPU with 32-bit EL0 support was late-onlined, > > > then we would have 32-bit support, so I think this is an oddity that you > > > get when the command line is passed. That said, I could nobble .desc and > > > print it from the .matches function, with a slightly different message > > > when the command line is passed. > > > > I think we could do a pr_info_once() in update_32bit_cpu_features(). > > Is that called on a system with one CPU? Ah, it's not. Anyway, I see your reasoning behind the late CPUs but I don't particularly like abusing the cpufeature support to pretend a SYSTEM_FEATURE is available before knowing any CPU has it (maybe we do it in other cases, I haven't checked). Could we not instead add a new feature for asymmetric support that's defined as ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE? This would be allowed for late CPUs and we keep the system_supports_32bit_el0() unchanged. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel