From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48996C56201 for ; Thu, 29 Oct 2020 01:00:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0156F207E8 for ; Thu, 29 Oct 2020 01:00:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603933212; bh=TxuvaTBTcDq8W2UUMV9w1n0ZdpbaMDJ1o2DdYwGgKn0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=PNtFcy9AkZ5ZpPLj1VXFFo346ZiZhApUIlqbiT4FYOetdIg7J7I1IT1Qw9z/GSbsh EtZtwgKyijtICPHXGXZTgktt8sjGmf3f2QYCHEPh01eGQ8f6KnuswVgbLSJGJFrJpu /O9mcmUuhoxMNjZ3/tDix8I8SAfnVa2b7wXF7Tb4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730143AbgJ2BAK (ORCPT ); Wed, 28 Oct 2020 21:00:10 -0400 Received: from mail.kernel.org ([198.145.29.99]:60546 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731548AbgJ1WR2 (ORCPT ); Wed, 28 Oct 2020 18:17:28 -0400 Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2255B24732; Wed, 28 Oct 2020 12:40:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603888855; bh=TxuvaTBTcDq8W2UUMV9w1n0ZdpbaMDJ1o2DdYwGgKn0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=QneAhOMcxCzrcXTfTmpJbyVrQ4l1M6wnbzY1Lo+Pw5ee0kwLy9rz7MFDvI+Daaes1 W/QHxqHxWijobKiz8vTRuUJuz9rhW1jkzmoBnTGZg3gwBWtROaYmcPSLQsSUPuXkBq bpECJeDjWeofDwqBEi4eE0FnlabFnDx+fFc6M5wU= Date: Wed, 28 Oct 2020 12:40:49 +0000 From: Will Deacon To: Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Qais Yousef , Suren Baghdasaryan , kernel-team@android.com Subject: Re: [PATCH 2/6] arm64: Allow mismatched 32-bit EL0 support Message-ID: <20201028124049.GC28091@willie-the-truck> References: <20201027215118.27003-1-will@kernel.org> <20201027215118.27003-3-will@kernel.org> <20201028111204.GB13345@gaia> <20201028111713.GA27927@willie-the-truck> <20201028112206.GD13345@gaia> <20201028112343.GD27927@willie-the-truck> <20201028114945.GE13345@gaia> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201028114945.GE13345@gaia> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On Wed, Oct 28, 2020 at 11:49:46AM +0000, Catalin Marinas wrote: > On Wed, Oct 28, 2020 at 11:23:43AM +0000, Will Deacon wrote: > > On Wed, Oct 28, 2020 at 11:22:06AM +0000, Catalin Marinas wrote: > > > On Wed, Oct 28, 2020 at 11:17:13AM +0000, Will Deacon wrote: > > > > On Wed, Oct 28, 2020 at 11:12:04AM +0000, Catalin Marinas wrote: > > > > > On Tue, Oct 27, 2020 at 09:51:14PM +0000, Will Deacon wrote: > > > > > > +static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) > > > > > > +{ > > > > > > + return has_cpuid_feature(entry, scope) || __allow_mismatched_32bit_el0; > > > > > > +} > > > > > > + > > > > > > static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) > > > > > > { > > > > > > bool has_sre; > > > > > > @@ -1803,7 +1851,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > > > > > > .desc = "32-bit EL0 Support", > > > > > > .capability = ARM64_HAS_32BIT_EL0, > > > > > > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > > > > > > - .matches = has_cpuid_feature, > > > > > > + .matches = has_32bit_el0, > > > > > > > > > > Ah, so this one reports 32-bit EL0 support even if no CPU actually > > > > > supports 32-bit (passing the command line option on TX2 would come up > > > > > with 32-bit EL0 in dmesg). I'd rather hide the .desc above and print the > > > > > information elsewhere when have at least one CPU supporting this. > > > > > > > > Yeah, the problem is if a CPU with 32-bit EL0 support was late-onlined, > > > > then we would have 32-bit support, so I think this is an oddity that you > > > > get when the command line is passed. That said, I could nobble .desc and > > > > print it from the .matches function, with a slightly different message > > > > when the command line is passed. > > > > > > I think we could do a pr_info_once() in update_32bit_cpu_features(). > > > > Is that called on a system with one CPU? > > Ah, it's not. > > Anyway, I see your reasoning behind the late CPUs but I don't > particularly like abusing the cpufeature support to pretend a > SYSTEM_FEATURE is available before knowing any CPU has it (maybe we do > it in other cases, I haven't checked). Hmm, but that's exactly what this cmdline option is about. We pretend that the system has 32-bit EL0 when normally we would say that we don't. > Could we not instead add a new feature for asymmetric support that's > defined as ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE? This would be allowed > for late CPUs and we keep the system_supports_32bit_el0() unchanged. I really don't think this gains us anything. The current users of system_supports_32bit_el0() are: - The ELF loader - CPU feature sanitisation code - Personality syscall - KVM and, afaict, all of these would need to check the new feature if we added it. I think it would also mean that at least one 32-bit capable CPU would have to boot early in order for the new feature to be advertised, which feels like an artificial restriction to me, particularly as you could just offline it immediately. That said, I have dropped the print (see below) because the whole "Detected" part is clearly bogus. Will --->8 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 813362a91995..ac6aff3a69de 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1264,7 +1264,12 @@ device_initcall(aarch32_el0_sysfs_init); static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) { - return has_cpuid_feature(entry, scope) || __allow_mismatched_32bit_el0; + if (has_cpuid_feature(entry, scope)) { + pr_info("detected: 32-bit EL0 Support\n"); + return true; + } + + return __allow_mismatched_32bit_el0; } static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) @@ -1874,7 +1879,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { }, #endif /* CONFIG_ARM64_VHE */ { - .desc = "32-bit EL0 Support", .capability = ARM64_HAS_32BIT_EL0, .type = ARM64_CPUCAP_SYSTEM_FEATURE, .matches = has_32bit_el0, From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D73FBC388F7 for ; Wed, 28 Oct 2020 12:41:28 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 49A6324735 for ; Wed, 28 Oct 2020 12:41:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="k5PdTk30"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="QneAhOMc" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 49A6324735 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=POgrsbpzVQ0biI/FknNUSoLFkpyI96fJXnI3eNj3MtY=; b=k5PdTk308d/ofc8nK8P6d66IM LRtZtLKokvos5X7dzEGCks6iAzpYEOoOp/uqmfe/MGZBWgVAai+FJSvG/isL2MzDOowyGXmgneGft 59kRd7UlL7sesligF3PYrfq/9YNorxy4PPKtseCG3ZDjJic44tsHCV5fvPC4Y6bM9xDgpy4bKh0pG SF7MSrsyx3N7QPGmhzcAOom7p+bwNXBVDitaIxyHNuVqg7ty7ntREDdZkVZg0BxJvDaos5A9shfyw S0Kcqn6QnPyJSPp7fCu6voZ5gHf1sJQvBEAHfQjQcWnKyqqG2eB2dlPshthqo7ja8+uGCyBRuV5xX 0Tx3Kc3Vw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXklB-00022x-Vg; Wed, 28 Oct 2020 12:41:01 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXkl5-00021e-Qh for linux-arm-kernel@lists.infradead.org; Wed, 28 Oct 2020 12:40:57 +0000 Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2255B24732; Wed, 28 Oct 2020 12:40:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603888855; bh=TxuvaTBTcDq8W2UUMV9w1n0ZdpbaMDJ1o2DdYwGgKn0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=QneAhOMcxCzrcXTfTmpJbyVrQ4l1M6wnbzY1Lo+Pw5ee0kwLy9rz7MFDvI+Daaes1 W/QHxqHxWijobKiz8vTRuUJuz9rhW1jkzmoBnTGZg3gwBWtROaYmcPSLQsSUPuXkBq bpECJeDjWeofDwqBEi4eE0FnlabFnDx+fFc6M5wU= Date: Wed, 28 Oct 2020 12:40:49 +0000 From: Will Deacon To: Catalin Marinas Subject: Re: [PATCH 2/6] arm64: Allow mismatched 32-bit EL0 support Message-ID: <20201028124049.GC28091@willie-the-truck> References: <20201027215118.27003-1-will@kernel.org> <20201027215118.27003-3-will@kernel.org> <20201028111204.GB13345@gaia> <20201028111713.GA27927@willie-the-truck> <20201028112206.GD13345@gaia> <20201028112343.GD27927@willie-the-truck> <20201028114945.GE13345@gaia> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201028114945.GE13345@gaia> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201028_084056_048490_A957BFC3 X-CRM114-Status: GOOD ( 34.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, kernel-team@android.com, Peter Zijlstra , Marc Zyngier , Qais Yousef , Greg Kroah-Hartman , Suren Baghdasaryan , Morten Rasmussen , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 28, 2020 at 11:49:46AM +0000, Catalin Marinas wrote: > On Wed, Oct 28, 2020 at 11:23:43AM +0000, Will Deacon wrote: > > On Wed, Oct 28, 2020 at 11:22:06AM +0000, Catalin Marinas wrote: > > > On Wed, Oct 28, 2020 at 11:17:13AM +0000, Will Deacon wrote: > > > > On Wed, Oct 28, 2020 at 11:12:04AM +0000, Catalin Marinas wrote: > > > > > On Tue, Oct 27, 2020 at 09:51:14PM +0000, Will Deacon wrote: > > > > > > +static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) > > > > > > +{ > > > > > > + return has_cpuid_feature(entry, scope) || __allow_mismatched_32bit_el0; > > > > > > +} > > > > > > + > > > > > > static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) > > > > > > { > > > > > > bool has_sre; > > > > > > @@ -1803,7 +1851,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > > > > > > .desc = "32-bit EL0 Support", > > > > > > .capability = ARM64_HAS_32BIT_EL0, > > > > > > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > > > > > > - .matches = has_cpuid_feature, > > > > > > + .matches = has_32bit_el0, > > > > > > > > > > Ah, so this one reports 32-bit EL0 support even if no CPU actually > > > > > supports 32-bit (passing the command line option on TX2 would come up > > > > > with 32-bit EL0 in dmesg). I'd rather hide the .desc above and print the > > > > > information elsewhere when have at least one CPU supporting this. > > > > > > > > Yeah, the problem is if a CPU with 32-bit EL0 support was late-onlined, > > > > then we would have 32-bit support, so I think this is an oddity that you > > > > get when the command line is passed. That said, I could nobble .desc and > > > > print it from the .matches function, with a slightly different message > > > > when the command line is passed. > > > > > > I think we could do a pr_info_once() in update_32bit_cpu_features(). > > > > Is that called on a system with one CPU? > > Ah, it's not. > > Anyway, I see your reasoning behind the late CPUs but I don't > particularly like abusing the cpufeature support to pretend a > SYSTEM_FEATURE is available before knowing any CPU has it (maybe we do > it in other cases, I haven't checked). Hmm, but that's exactly what this cmdline option is about. We pretend that the system has 32-bit EL0 when normally we would say that we don't. > Could we not instead add a new feature for asymmetric support that's > defined as ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE? This would be allowed > for late CPUs and we keep the system_supports_32bit_el0() unchanged. I really don't think this gains us anything. The current users of system_supports_32bit_el0() are: - The ELF loader - CPU feature sanitisation code - Personality syscall - KVM and, afaict, all of these would need to check the new feature if we added it. I think it would also mean that at least one 32-bit capable CPU would have to boot early in order for the new feature to be advertised, which feels like an artificial restriction to me, particularly as you could just offline it immediately. That said, I have dropped the print (see below) because the whole "Detected" part is clearly bogus. Will --->8 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 813362a91995..ac6aff3a69de 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1264,7 +1264,12 @@ device_initcall(aarch32_el0_sysfs_init); static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) { - return has_cpuid_feature(entry, scope) || __allow_mismatched_32bit_el0; + if (has_cpuid_feature(entry, scope)) { + pr_info("detected: 32-bit EL0 Support\n"); + return true; + } + + return __allow_mismatched_32bit_el0; } static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) @@ -1874,7 +1879,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = { }, #endif /* CONFIG_ARM64_VHE */ { - .desc = "32-bit EL0 Support", .capability = ARM64_HAS_32BIT_EL0, .type = ARM64_CPUCAP_SYSTEM_FEATURE, .matches = has_32bit_el0, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel