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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 18/18] hw/riscv: microchip_pfsoc: Hook the I2C1 controller
Date: Thu, 29 Oct 2020 07:13:58 -0700	[thread overview]
Message-ID: <20201029141358.3102636-19-alistair.francis@wdc.com> (raw)
In-Reply-To: <20201029141358.3102636-1-alistair.francis@wdc.com>

From: Bin Meng <bin.meng@windriver.com>

The latest SD card image [1] released by Microchip ships a Linux
kernel with built-in PolarFire SoC I2C driver support. The device
tree file includes the description for the I2C1 node hence kernel
tries to probe the I2C1 device during boot.

It is enough to create an unimplemented device for I2C1 to allow
the kernel to continue booting to the shell.

[1] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-11-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 1 +
 hw/riscv/microchip_pfsoc.c         | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index db77e9c84a..51d44637db 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -97,6 +97,7 @@ enum {
     MICROCHIP_PFSOC_MMUART2,
     MICROCHIP_PFSOC_MMUART3,
     MICROCHIP_PFSOC_MMUART4,
+    MICROCHIP_PFSOC_I2C1,
     MICROCHIP_PFSOC_GEM0,
     MICROCHIP_PFSOC_GEM1,
     MICROCHIP_PFSOC_GPIO0,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 5e31b84817..d13d6ba7b8 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -113,6 +113,7 @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
+    [MICROCHIP_PFSOC_I2C1] =            { 0x2010b000,     0x1000 },
     [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,     0x2000 },
     [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,     0x2000 },
     [MICROCHIP_PFSOC_GPIO0] =           { 0x20120000,     0x1000 },
@@ -343,6 +344,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
         serial_hd(4));
 
+    /* I2C1 */
+    create_unimplemented_device("microchip.pfsoc.i2c1",
+        memmap[MICROCHIP_PFSOC_I2C1].base,
+        memmap[MICROCHIP_PFSOC_I2C1].size);
+
     /* GEMs */
 
     nd = &nd_table[0];
-- 
2.28.0



  parent reply	other threads:[~2020-10-29 14:41 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-29 14:13 [PULL 00/18] riscv-to-apply queue Alistair Francis
2020-10-29 14:13 ` [PULL 01/18] hw/riscv: sifive_u: Allow passing custom DTB Alistair Francis
2020-10-29 14:13 ` [PULL 02/18] hw/riscv: virt: " Alistair Francis
2020-10-29 14:13 ` [PULL 03/18] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Alistair Francis
2020-10-29 14:13 ` [PULL 04/18] target/riscv: Add basic vmstate description of CPU Alistair Francis
2020-10-29 14:13 ` [PULL 05/18] target/riscv: Add PMP state description Alistair Francis
2020-10-29 14:13 ` [PULL 06/18] target/riscv: Add H extension " Alistair Francis
2020-10-29 14:13 ` [PULL 07/18] target/riscv: Add V " Alistair Francis
2020-10-29 14:13 ` [PULL 08/18] target/riscv: Add sifive_plic vmstate Alistair Francis
2020-10-29 14:13 ` [PULL 09/18] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps Alistair Francis
2020-10-29 14:13 ` [PULL 10/18] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Alistair Francis
2020-10-29 14:13 ` [PULL 11/18] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Alistair Francis
2020-10-29 14:13 ` [PULL 12/18] hw/misc: Add Microchip PolarFire SoC IOSCB module support Alistair Francis
2020-10-29 14:13 ` [PULL 13/18] hw/riscv: microchip_pfsoc: Connect the IOSCB module Alistair Francis
2020-10-29 14:13 ` [PULL 14/18] hw/misc: Add Microchip PolarFire SoC SYSREG module support Alistair Francis
2020-10-29 14:13 ` [PULL 15/18] hw/riscv: microchip_pfsoc: Connect the SYSREG module Alistair Francis
2020-10-29 14:13 ` [PULL 16/18] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 Alistair Francis
2020-10-29 14:13 ` [PULL 17/18] hw/riscv: microchip_pfsoc: Correct DDR memory map Alistair Francis
2020-10-29 14:13 ` Alistair Francis [this message]
2020-11-01 14:02 ` [PULL 00/18] riscv-to-apply queue Peter Maydell
2020-11-01 16:27   ` Bin Meng

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