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03 Nov 2020 07:19:34 -0800 IronPort-SDR: PW7nqYWDT0F28ke6svIt4DO2TqMISCY+uaoR8H72EcY6scWscudid+HQl/cZs7JSsS2SAWRV2s vyVmHBW5jr8jV2WPcyfYN4tX9KYFCR9sBE4ZcImMdjM6GDv09W6VHYs5LIbzUCtPkYNscRhANy /wGr65hJcABWP8prOd7TuwQ3yH7sqJoEjBeykGM4Lw0s2mzvrjRzz46IvUoOtCaHvcoBrhaIrq iN1znbBYKd2FToORlovEJanF9NqKZ917/8FTpDpSuJ8dTypOs6OjyGKpv7U7JvgQiWZIV/RbKp eVQ= WDCIronportException: Internal Received: from usa003000.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.60.113]) by uls-op-cesaip01.wdc.com with ESMTP; 03 Nov 2020 07:33:26 -0800 From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL v2 09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps Date: Tue, 3 Nov 2020 07:21:40 -0800 Message-Id: <20201103152150.2677566-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201103152150.2677566-1-alistair.francis@wdc.com> References: <20201103152150.2677566-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=569a91e0c=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/03 10:33:23 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng It is not easy to find out the memory map for a specific component in the PolarFire SoC as the information is scattered in different documents. Add some comments so that people can know where to get such information from the Microchip website. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-id: 1603863010-15807-2-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis --- hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 4627179cd3..6aac8497fc 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -66,6 +66,24 @@ /* GEM version */ #define GEM_REVISION 0x0107010c +/* + * The complete description of the whole PolarFire SoC memory map is scattered + * in different documents. There are several places to look at for memory maps: + * + * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA + * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from + * https://www.microsemi.com/document-portal/doc_download/ + * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, + * describes the whole picture of the PolarFire SoC memory map. + * + * 2 A zip file for PolarFire soC memory map, which can be downloaded from + * https://www.microsemi.com/document-portal/doc_download/ + * 1244581-polarfire-soc-register-map, contains the following 2 major parts: + * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm + * describes the complete integrated peripherals memory map + * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm + * describes the complete IOSCB modules memory maps + */ static const struct MemmapEntry { hwaddr base; hwaddr size; -- 2.28.0