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From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Euler Robot <euler.robot@huawei.com>,
	alistair23@gmail.com, Xinhao Zhang <zhangxinhao1@huawei.com>,
	Kai Deng <dengkai1@huawei.com>
Subject: [PULL v2 19/19] target/riscv/csr.c : add space before the open parenthesis '('
Date: Tue,  3 Nov 2020 07:21:50 -0800	[thread overview]
Message-ID: <20201103152150.2677566-20-alistair.francis@wdc.com> (raw)
In-Reply-To: <20201103152150.2677566-1-alistair.francis@wdc.com>

From: Xinhao Zhang <zhangxinhao1@huawei.com>

Fix code style. Space required before the open parenthesis '('.

Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
Signed-off-by: Kai Deng <dengkai1@huawei.com>
Reported-by: Euler Robot <euler.robot@huawei.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201030004815.4172849-1-zhangxinhao1@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e33f6cdc11..93263f8e06 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -882,7 +882,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
             return -RISCV_EXCP_ILLEGAL_INST;
         } else {
-            if((val ^ env->satp) & SATP_ASID) {
+            if ((val ^ env->satp) & SATP_ASID) {
                 tlb_flush(env_cpu(env));
             }
             env->satp = val;
-- 
2.28.0



  parent reply	other threads:[~2020-11-03 15:48 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03 15:21 [PULL v2 00/19] riscv-to-apply queue Alistair Francis
2020-11-03 15:21 ` [PULL v2 01/19] hw/riscv: sifive_u: Allow passing custom DTB Alistair Francis
2020-11-03 15:21 ` [PULL v2 02/19] hw/riscv: virt: " Alistair Francis
2020-11-03 15:21 ` [PULL v2 03/19] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Alistair Francis
2020-11-03 15:21 ` [PULL v2 04/19] target/riscv: Add basic vmstate description of CPU Alistair Francis
2020-11-03 15:21 ` [PULL v2 05/19] target/riscv: Add PMP state description Alistair Francis
2020-11-03 15:21 ` [PULL v2 06/19] target/riscv: Add H extension " Alistair Francis
2020-11-03 15:21 ` [PULL v2 07/19] target/riscv: Add V " Alistair Francis
2020-11-03 15:21 ` [PULL v2 08/19] target/riscv: Add sifive_plic vmstate Alistair Francis
2020-11-03 15:21 ` [PULL v2 09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps Alistair Francis
2020-11-03 15:21 ` [PULL v2 10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Alistair Francis
2020-11-03 15:21 ` [PULL v2 11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Alistair Francis
2020-11-03 15:21 ` [PULL v2 12/19] hw/misc: Add Microchip PolarFire SoC IOSCB module support Alistair Francis
2020-11-03 15:21 ` [PULL v2 13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module Alistair Francis
2020-11-03 15:21 ` [PULL v2 14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support Alistair Francis
2020-11-03 15:21 ` [PULL v2 15/19] hw/riscv: microchip_pfsoc: Connect the SYSREG module Alistair Francis
2020-11-03 15:21 ` [PULL v2 16/19] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 Alistair Francis
2020-11-03 15:21 ` [PULL v2 17/19] hw/riscv: microchip_pfsoc: Correct DDR memory map Alistair Francis
2020-11-03 15:21 ` [PULL v2 18/19] hw/riscv: microchip_pfsoc: Hook the I2C1 controller Alistair Francis
2020-11-03 15:21 ` Alistair Francis [this message]
2020-11-03 21:07 ` [PULL v2 00/19] riscv-to-apply queue Peter Maydell

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