* [Intel-gfx] [PATCH] drm/i915/tgl: Fix Media power gate sequence.
@ 2020-11-11 7:28 Rodrigo Vivi
2020-11-11 10:08 ` Chris Wilson
2020-11-11 19:08 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Fix Media power gate sequence. (rev2) Patchwork
0 siblings, 2 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2020-11-11 7:28 UTC (permalink / raw)
To: intel-gfx
Some media power gates are disabled by default. commit 5d86923060fc
("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
tried to enable it, but it duplicated an existent register. So, RC6
sequences ended up overwriting it.
The open question now is it should be independent of RC6 sequence,
but anyway this power gating control for now is very tied to the
RC6 sequence, so let's keep it that way for now.
Fixes: 5d86923060fc ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: stable@vger.kernel.org#v5.5+
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 20 ++++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 12 +++++-------
drivers/gpu/drm/i915/intel_pm.c | 16 ----------------
3 files changed, 21 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index ab675d35030d..b9e56859daf6 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -56,9 +56,12 @@ static inline void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
static void gen11_rc6_enable(struct intel_rc6 *rc6)
{
+ struct drm_i915_private *i915 = rc6_to_i915(rc6);
struct intel_uncore *uncore = rc6_to_uncore(rc6);
struct intel_engine_cs *engine;
enum intel_engine_id id;
+ u32 pg_enable = 0;
+ int i;
/* 2b: Program RC6 thresholds.*/
set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
@@ -102,10 +105,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
GEN6_RC_CTL_RC6_ENABLE |
GEN6_RC_CTL_EI_MODE(1);
- set(uncore, GEN9_PG_ENABLE,
- GEN9_RENDER_PG_ENABLE |
- GEN9_MEDIA_PG_ENABLE |
- GEN11_MEDIA_SAMPLER_PG_ENABLE);
+ pg_enable = GEN9_RENDER_PG_ENABLE |
+ GEN9_MEDIA_PG_ENABLE |
+ GEN11_MEDIA_SAMPLER_PG_ENABLE;
+
+ if (INTEL_GEN(i915) >= 12) {
+ /* Enable VD HCP & MFX_ENC powergate */
+ for (i = 0; i < I915_MAX_VCS; i++)
+ if (HAS_ENGINE(&i915->gt, _VCS(i)))
+ pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
+ VDN_MFX_POWERGATE_ENABLE(i);
+ }
+
+ set(uncore, GEN9_PG_ENABLE, pg_enable);
}
static void gen9_rc6_enable(struct intel_rc6 *rc6)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 39664ba553ec..28d02ec53573 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8996,10 +8996,6 @@ enum {
#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
-#define POWERGATE_ENABLE _MMIO(0xa210)
-#define VDN_HCP_POWERGATE_ENABLE(n) BIT(((n) * 2) + 3)
-#define VDN_MFX_POWERGATE_ENABLE(n) BIT(((n) * 2) + 4)
-
#define GTFIFODBG _MMIO(0x120000)
#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
@@ -9139,9 +9135,11 @@ enum {
#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
#define GEN9_PG_ENABLE _MMIO(0xA210)
-#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
-#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
-#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
+#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
+#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
+#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
+#define VDN_HCP_POWERGATE_ENABLE(n) BIT(((n) * 2) + 3)
+#define VDN_MFX_POWERGATE_ENABLE(n) BIT(((n) * 2) + 4)
#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f54375b11964..bbec56f97832 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7111,22 +7111,8 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
0, CNL_DELAY_PMRSP);
}
-static void gen12_init_clock_gating(struct drm_i915_private *i915)
-{
- unsigned int i;
-
- /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
- for (i = 0; i < I915_MAX_VCS; i++)
- if (HAS_ENGINE(&i915->gt, _VCS(i)))
- intel_uncore_rmw(&i915->uncore, POWERGATE_ENABLE, 0,
- VDN_HCP_POWERGATE_ENABLE(i) |
- VDN_MFX_POWERGATE_ENABLE(i));
-}
-
static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
{
- gen12_init_clock_gating(dev_priv);
-
/* Wa_1409120013:tgl */
I915_WRITE(ILK_DPFC_CHICKEN,
ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
@@ -7143,8 +7129,6 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
{
- gen12_init_clock_gating(dev_priv);
-
/* Wa_1409836686:dg1[a0] */
if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
--
2.26.2
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Fix Media power gate sequence.
2020-11-11 7:28 [Intel-gfx] [PATCH] drm/i915/tgl: Fix Media power gate sequence Rodrigo Vivi
@ 2020-11-11 10:08 ` Chris Wilson
2020-11-11 14:09 ` Rodrigo Vivi
2020-11-11 19:08 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Fix Media power gate sequence. (rev2) Patchwork
1 sibling, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2020-11-11 10:08 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
Quoting Rodrigo Vivi (2020-11-11 07:28:59)
> Some media power gates are disabled by default. commit 5d86923060fc
> ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
> tried to enable it, but it duplicated an existent register. So, RC6
> sequences ended up overwriting it.
>
> The open question now is it should be independent of RC6 sequence,
> but anyway this power gating control for now is very tied to the
> RC6 sequence, so let's keep it that way for now.
It's the GT rc6 and pg setup sequence, not just rc6.
> Fixes: 5d86923060fc ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: stable@vger.kernel.org#v5.5+
> Cc: Dale B Stimson <dale.b.stimson@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_rc6.c | 20 ++++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 12 +++++-------
> drivers/gpu/drm/i915/intel_pm.c | 16 ----------------
> 3 files changed, 21 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index ab675d35030d..b9e56859daf6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -56,9 +56,12 @@ static inline void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
>
> static void gen11_rc6_enable(struct intel_rc6 *rc6)
> {
> + struct drm_i915_private *i915 = rc6_to_i915(rc6);
> struct intel_uncore *uncore = rc6_to_uncore(rc6);
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> + u32 pg_enable = 0;
= 0?
> + int i;
>
> /* 2b: Program RC6 thresholds.*/
> set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> @@ -102,10 +105,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> GEN6_RC_CTL_RC6_ENABLE |
> GEN6_RC_CTL_EI_MODE(1);
>
> - set(uncore, GEN9_PG_ENABLE,
> - GEN9_RENDER_PG_ENABLE |
> - GEN9_MEDIA_PG_ENABLE |
> - GEN11_MEDIA_SAMPLER_PG_ENABLE);
> + pg_enable = GEN9_RENDER_PG_ENABLE |
> + GEN9_MEDIA_PG_ENABLE |
> + GEN11_MEDIA_SAMPLER_PG_ENABLE;
> +
> + if (INTEL_GEN(i915) >= 12) {
> + /* Enable VD HCP & MFX_ENC powergate */
/* i++; post-increment i */
> + for (i = 0; i < I915_MAX_VCS; i++)
> + if (HAS_ENGINE(&i915->gt, _VCS(i)))
Wrong gt; never use i915 for anything but device info under gt/
Oh and s/BIT/REG_BIT/.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/tgl: Fix Media power gate sequence.
2020-11-11 10:08 ` Chris Wilson
@ 2020-11-11 14:09 ` Rodrigo Vivi
2020-11-11 14:31 ` Chris Wilson
0 siblings, 1 reply; 5+ messages in thread
From: Rodrigo Vivi @ 2020-11-11 14:09 UTC (permalink / raw)
To: intel-gfx
Some media power gates are disabled by default. commit 5d86923060fc
("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
tried to enable it, but it duplicated an existent register.
So, the main PG setup sequences ended up overwriting it.
So, let's now merge this to the main PG setup sequence.
v2: (Chris): s/REG_BIT/BIT, remove useless comment,
remove useless =0, use the right gt,
remove rc6 sequence doubt from commit message.
Fixes: 5d86923060fc ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: stable@vger.kernel.org#v5.5+
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 19 +++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 12 +++++-------
drivers/gpu/drm/i915/intel_pm.c | 16 ----------------
3 files changed, 20 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index ab675d35030d..c01fa86e0d07 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -56,9 +56,12 @@ static inline void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
static void gen11_rc6_enable(struct intel_rc6 *rc6)
{
+ struct drm_i915_private *i915 = rc6_to_i915(rc6);
struct intel_uncore *uncore = rc6_to_uncore(rc6);
struct intel_engine_cs *engine;
enum intel_engine_id id;
+ u32 pg_enable;
+ int i;
/* 2b: Program RC6 thresholds.*/
set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
@@ -102,10 +105,18 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
GEN6_RC_CTL_RC6_ENABLE |
GEN6_RC_CTL_EI_MODE(1);
- set(uncore, GEN9_PG_ENABLE,
- GEN9_RENDER_PG_ENABLE |
- GEN9_MEDIA_PG_ENABLE |
- GEN11_MEDIA_SAMPLER_PG_ENABLE);
+ pg_enable = GEN9_RENDER_PG_ENABLE |
+ GEN9_MEDIA_PG_ENABLE |
+ GEN11_MEDIA_SAMPLER_PG_ENABLE;
+
+ if (INTEL_GEN(i915) >= 12) {
+ for (i = 0; i < I915_MAX_VCS; i++)
+ if (HAS_ENGINE(rc6_to_gt(rc6), _VCS(i)))
+ pg_enable |= VDN_HCP_POWERGATE_ENABLE(i) |
+ VDN_MFX_POWERGATE_ENABLE(i);
+ }
+
+ set(uncore, GEN9_PG_ENABLE, pg_enable);
}
static void gen9_rc6_enable(struct intel_rc6 *rc6)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 39664ba553ec..b4c4a8216444 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8996,10 +8996,6 @@ enum {
#define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0)
#define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1)
-#define POWERGATE_ENABLE _MMIO(0xa210)
-#define VDN_HCP_POWERGATE_ENABLE(n) BIT(((n) * 2) + 3)
-#define VDN_MFX_POWERGATE_ENABLE(n) BIT(((n) * 2) + 4)
-
#define GTFIFODBG _MMIO(0x120000)
#define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20)
#define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13)
@@ -9139,9 +9135,11 @@ enum {
#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
#define GEN9_PG_ENABLE _MMIO(0xA210)
-#define GEN9_RENDER_PG_ENABLE REG_BIT(0)
-#define GEN9_MEDIA_PG_ENABLE REG_BIT(1)
-#define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2)
+#define GEN9_RENDER_PG_ENABLE BIT(0)
+#define GEN9_MEDIA_PG_ENABLE BIT(1)
+#define GEN11_MEDIA_SAMPLER_PG_ENABLE BIT(2)
+#define VDN_HCP_POWERGATE_ENABLE(n) BIT(((n) * 2) + 3)
+#define VDN_MFX_POWERGATE_ENABLE(n) BIT(((n) * 2) + 4)
#define GEN8_PUSHBUS_CONTROL _MMIO(0xA248)
#define GEN8_PUSHBUS_ENABLE _MMIO(0xA250)
#define GEN8_PUSHBUS_SHIFT _MMIO(0xA25C)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f54375b11964..bbec56f97832 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7111,22 +7111,8 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
0, CNL_DELAY_PMRSP);
}
-static void gen12_init_clock_gating(struct drm_i915_private *i915)
-{
- unsigned int i;
-
- /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
- for (i = 0; i < I915_MAX_VCS; i++)
- if (HAS_ENGINE(&i915->gt, _VCS(i)))
- intel_uncore_rmw(&i915->uncore, POWERGATE_ENABLE, 0,
- VDN_HCP_POWERGATE_ENABLE(i) |
- VDN_MFX_POWERGATE_ENABLE(i));
-}
-
static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
{
- gen12_init_clock_gating(dev_priv);
-
/* Wa_1409120013:tgl */
I915_WRITE(ILK_DPFC_CHICKEN,
ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
@@ -7143,8 +7129,6 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
{
- gen12_init_clock_gating(dev_priv);
-
/* Wa_1409836686:dg1[a0] */
if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
--
2.26.2
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/tgl: Fix Media power gate sequence.
2020-11-11 14:09 ` Rodrigo Vivi
@ 2020-11-11 14:31 ` Chris Wilson
0 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2020-11-11 14:31 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx
Quoting Rodrigo Vivi (2020-11-11 14:09:36)
> Some media power gates are disabled by default. commit 5d86923060fc
> ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
> tried to enable it, but it duplicated an existent register.
> So, the main PG setup sequences ended up overwriting it.
>
> So, let's now merge this to the main PG setup sequence.
>
> v2: (Chris): s/REG_BIT/BIT, remove useless comment,
> remove useless =0, use the right gt,
> remove rc6 sequence doubt from commit message.
>
> Fixes: 5d86923060fc ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: stable@vger.kernel.org#v5.5+
> Cc: Dale B Stimson <dale.b.stimson@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_rc6.c | 19 +++++++++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 12 +++++-------
> drivers/gpu/drm/i915/intel_pm.c | 16 ----------------
> 3 files changed, 20 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index ab675d35030d..c01fa86e0d07 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -56,9 +56,12 @@ static inline void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
>
> static void gen11_rc6_enable(struct intel_rc6 *rc6)
> {
> + struct drm_i915_private *i915 = rc6_to_i915(rc6);
> struct intel_uncore *uncore = rc6_to_uncore(rc6);
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> + u32 pg_enable;
> + int i;
>
> /* 2b: Program RC6 thresholds.*/
> set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> @@ -102,10 +105,18 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> GEN6_RC_CTL_RC6_ENABLE |
> GEN6_RC_CTL_EI_MODE(1);
>
> - set(uncore, GEN9_PG_ENABLE,
> - GEN9_RENDER_PG_ENABLE |
> - GEN9_MEDIA_PG_ENABLE |
> - GEN11_MEDIA_SAMPLER_PG_ENABLE);
> + pg_enable = GEN9_RENDER_PG_ENABLE |
> + GEN9_MEDIA_PG_ENABLE |
> + GEN11_MEDIA_SAMPLER_PG_ENABLE;
> +
> + if (INTEL_GEN(i915) >= 12) {
> + for (i = 0; i < I915_MAX_VCS; i++)
> + if (HAS_ENGINE(rc6_to_gt(rc6), _VCS(i)))
I would have put gt = rc6_to_gt(rc6) into the locals and used gt->i915
for the singular instance.
Code motion looks ok,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Now as to why this escaped notice? I see that our rc6/power measurement test
is not reporting energy consumption for tgl. This is concerning, give me
a moment to see if there's anything obvious blocking the test.
-Chris
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Fix Media power gate sequence. (rev2)
2020-11-11 7:28 [Intel-gfx] [PATCH] drm/i915/tgl: Fix Media power gate sequence Rodrigo Vivi
2020-11-11 10:08 ` Chris Wilson
@ 2020-11-11 19:08 ` Patchwork
1 sibling, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-11-11 19:08 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/tgl: Fix Media power gate sequence. (rev2)
URL : https://patchwork.freedesktop.org/series/83723/
State : failure
== Summary ==
Applying: drm/i915/tgl: Fix Media power gate sequence.
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/gt/intel_rc6.c
M drivers/gpu/drm/i915/i915_reg.h
M drivers/gpu/drm/i915/intel_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_reg.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_reg.h
Auto-merging drivers/gpu/drm/i915/gt/intel_rc6.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/intel_rc6.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/tgl: Fix Media power gate sequence.
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2020-11-11 7:28 [Intel-gfx] [PATCH] drm/i915/tgl: Fix Media power gate sequence Rodrigo Vivi
2020-11-11 10:08 ` Chris Wilson
2020-11-11 14:09 ` Rodrigo Vivi
2020-11-11 14:31 ` Chris Wilson
2020-11-11 19:08 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Fix Media power gate sequence. (rev2) Patchwork
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