From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1104C61DD8 for ; Wed, 11 Nov 2020 16:27:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9C25720756 for ; Wed, 11 Nov 2020 16:27:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727266AbgKKQ1G (ORCPT ); Wed, 11 Nov 2020 11:27:06 -0500 Received: from foss.arm.com ([217.140.110.172]:57652 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727325AbgKKQ1F (ORCPT ); Wed, 11 Nov 2020 11:27:05 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4F040101E; Wed, 11 Nov 2020 08:27:04 -0800 (PST) Received: from e107158-lin.cambridge.arm.com (unknown [10.1.194.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E5D273F6CF; Wed, 11 Nov 2020 08:27:02 -0800 (PST) Date: Wed, 11 Nov 2020 16:27:00 +0000 From: Qais Yousef To: Will Deacon Cc: Catalin Marinas , "linux-arm-kernel@lists.infradead.org" , "linux-arch@vger.kernel.org" , Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Suren Baghdasaryan , "kernel-team@android.com" Subject: Re: [PATCH 2/6] arm64: Allow mismatched 32-bit EL0 support Message-ID: <20201111162700.p4sem2fup5qjjbqz@e107158-lin.cambridge.arm.com> References: <20201028185620.GK13345@gaia> <20201029222048.GD31375@willie-the-truck> <20201030111846.GC23196@gaia> <20201030161353.GC32582@willie-the-truck> <20201102114444.GC21082@gaia> <20201105213846.GA8600@willie-the-truck> <20201106125425.u6qoswsjfskyxtoo@e107158-lin.cambridge.arm.com> <20201106130007.GA10605@willie-the-truck> <20201106144835.q363ezyse4vc5kdg@e107158-lin.cambridge.arm.com> <20201109135259.GA14526@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20201109135259.GA14526@willie-the-truck> Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On 11/09/20 13:52, Will Deacon wrote: > On Fri, Nov 06, 2020 at 02:48:35PM +0000, Qais Yousef wrote: > > On 11/06/20 13:00, Will Deacon wrote: > > > On Fri, Nov 06, 2020 at 12:54:25PM +0000, Qais Yousef wrote: > > > > FWIW I have my v3 over here in case it's of any help. It solves the problem of > > > > HWCAP discovery when late AArch32 CPU is booted by populating boot_cpu_date > > > > with 32bit features then. > > > > > > > > git clone https://git.gitlab.arm.com/linux-arm/linux-qy.git -b asym-aarch32-upstream-v3 origin/asym-aarch32-upstream-v3 > > > > > > Cheers, I've done something similar. I was hoping to post it today, but I've > > > been side-tracked with bug fixing this morning. The main headache I ended up > > > with was allowing late-onlining of 64-bit-only CPUs if all the boot CPUs > > > are 32-bit capable. What do you do in that case? > > > > Do you mean if CPUs 0-3 were 32bit capable and we boot with maxcpus=4 then > > attempt to bring the remaining 64bit-only cpus online later? > > Right. I think we will refuse to online them. I'll post my attempt at > handling that shortly. Sorry for the delayed response. You're right, I tried that and they refuse to come online. We missed that tbh. Haven't thought what we should do yet. I tried your v2 and it failed similarly. I usually have a similar hunk in my testing to check how the kernel perceives the 32bit support when I execute a binary: diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index f447d313a9c5..a9549e55a6c8 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -611,6 +611,9 @@ static inline bool system_supports_32bit_el0(void) { u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + pr_err("System supports symmetric 32bit el0: %d\n", id_aa64pfr0_32bit_el0(pfr0)); + pr_err("System supports Asymmetric 32bit el0: %ld\n", static_branch_unlikely(&arm64_mismatched_32bit_el0)); + return id_aa64pfr0_32bit_el0(pfr0) || static_branch_unlikely(&arm64_mismatched_32bit_el0); } In your v2 both conditions are true. In my series we see the system as symmetric if we boot the 32bit capable cpus _only_. > > Haven't tried that tbh. What symptoms do you expect to see? I can try it out. > > I'm off for the remainder of the day, but can spend few mins to run an > > experiment for sure. > > No probs; I've been taking Friday afternoons off to burn holiday anyway, so > you didn't miss anything! :-) Thanks -- Qais Yousef From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96E25C388F9 for ; Wed, 11 Nov 2020 16:27:32 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 215EF20678 for ; Wed, 11 Nov 2020 16:27:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="3FAB3AFr" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 215EF20678 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bICrs0wJOLaI4VAJ80Mu3YcCBFmVYpqQSFlP30+GbAE=; b=3FAB3AFrmqK8M3M7aPpzxK6IU Lx6+V5diGwX49yl8ewuzYTOzGh6rMswuSa2EFS1IXExK/WAyhjS75sHq6DC4JC7S0h5f+O3vdQxyx ncr2/w7Q9t8NF82JAvNm82+syErQ88YUXuyt+OjNot1KBKZzlfs3T830TgK2rgaX2QhM8p2ZlsWQ8 3KeTgpy4yxWBXWfNpkWkrNV8QXIGh4bY9G+VVs9SjwpPk2ZezfszUGxmao92tnL1pqSYJTKaWKGup UrBVUQlojh52JYCLIh7fxJ286zMgOhJReW2ivlFuTqq3rsjS738S5M1euVpXjkFIfhcnn0hukWtfc n4TEG+VpQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kcsxh-0005XT-W0; Wed, 11 Nov 2020 16:27:10 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kcsxf-0005Vw-Ba for linux-arm-kernel@lists.infradead.org; Wed, 11 Nov 2020 16:27:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4F040101E; Wed, 11 Nov 2020 08:27:04 -0800 (PST) Received: from e107158-lin.cambridge.arm.com (unknown [10.1.194.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E5D273F6CF; Wed, 11 Nov 2020 08:27:02 -0800 (PST) Date: Wed, 11 Nov 2020 16:27:00 +0000 From: Qais Yousef To: Will Deacon Subject: Re: [PATCH 2/6] arm64: Allow mismatched 32-bit EL0 support Message-ID: <20201111162700.p4sem2fup5qjjbqz@e107158-lin.cambridge.arm.com> References: <20201028185620.GK13345@gaia> <20201029222048.GD31375@willie-the-truck> <20201030111846.GC23196@gaia> <20201030161353.GC32582@willie-the-truck> <20201102114444.GC21082@gaia> <20201105213846.GA8600@willie-the-truck> <20201106125425.u6qoswsjfskyxtoo@e107158-lin.cambridge.arm.com> <20201106130007.GA10605@willie-the-truck> <20201106144835.q363ezyse4vc5kdg@e107158-lin.cambridge.arm.com> <20201109135259.GA14526@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201109135259.GA14526@willie-the-truck> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_112707_622629_D8963142 X-CRM114-Status: GOOD ( 25.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "linux-arch@vger.kernel.org" , Marc Zyngier , "kernel-team@android.com" , Peter Zijlstra , Catalin Marinas , Greg Kroah-Hartman , Suren Baghdasaryan , Morten Rasmussen , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/09/20 13:52, Will Deacon wrote: > On Fri, Nov 06, 2020 at 02:48:35PM +0000, Qais Yousef wrote: > > On 11/06/20 13:00, Will Deacon wrote: > > > On Fri, Nov 06, 2020 at 12:54:25PM +0000, Qais Yousef wrote: > > > > FWIW I have my v3 over here in case it's of any help. It solves the problem of > > > > HWCAP discovery when late AArch32 CPU is booted by populating boot_cpu_date > > > > with 32bit features then. > > > > > > > > git clone https://git.gitlab.arm.com/linux-arm/linux-qy.git -b asym-aarch32-upstream-v3 origin/asym-aarch32-upstream-v3 > > > > > > Cheers, I've done something similar. I was hoping to post it today, but I've > > > been side-tracked with bug fixing this morning. The main headache I ended up > > > with was allowing late-onlining of 64-bit-only CPUs if all the boot CPUs > > > are 32-bit capable. What do you do in that case? > > > > Do you mean if CPUs 0-3 were 32bit capable and we boot with maxcpus=4 then > > attempt to bring the remaining 64bit-only cpus online later? > > Right. I think we will refuse to online them. I'll post my attempt at > handling that shortly. Sorry for the delayed response. You're right, I tried that and they refuse to come online. We missed that tbh. Haven't thought what we should do yet. I tried your v2 and it failed similarly. I usually have a similar hunk in my testing to check how the kernel perceives the 32bit support when I execute a binary: diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index f447d313a9c5..a9549e55a6c8 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -611,6 +611,9 @@ static inline bool system_supports_32bit_el0(void) { u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + pr_err("System supports symmetric 32bit el0: %d\n", id_aa64pfr0_32bit_el0(pfr0)); + pr_err("System supports Asymmetric 32bit el0: %ld\n", static_branch_unlikely(&arm64_mismatched_32bit_el0)); + return id_aa64pfr0_32bit_el0(pfr0) || static_branch_unlikely(&arm64_mismatched_32bit_el0); } In your v2 both conditions are true. In my series we see the system as symmetric if we boot the 32bit capable cpus _only_. > > Haven't tried that tbh. What symptoms do you expect to see? I can try it out. > > I'm off for the remainder of the day, but can spend few mins to run an > > experiment for sure. > > No probs; I've been taking Friday afternoons off to burn holiday anyway, so > you didn't miss anything! :-) Thanks -- Qais Yousef _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel