From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FSL_HELO_FAKE, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_IN_DEF_DKIM_WL autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0B69C83D56 for ; Mon, 16 Nov 2020 12:38:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 95EA322265 for ; Mon, 16 Nov 2020 12:38:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="nTUfK2Ei" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729198AbgKPLt5 (ORCPT ); Mon, 16 Nov 2020 06:49:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726487AbgKPLt5 (ORCPT ); Mon, 16 Nov 2020 06:49:57 -0500 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C053EC0613CF for ; Mon, 16 Nov 2020 03:49:56 -0800 (PST) Received: by mail-wm1-x344.google.com with SMTP id 19so23447285wmf.1 for ; Mon, 16 Nov 2020 03:49:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=CFJEkUj6StvnCLf3zA4XSa8BJ3U9++NnIiul0HVC8DY=; b=nTUfK2EitnQ5Q0QZZIJ6UfQATrjdCE4F3RuhLemICZ+FIa4eNeZj1jdUP59xrVtnyE wsRGi8ju0E8yAAhUqKqi4ygMnWHUbuQeVqoTv1FkbIukrUqFbNGApXG4mxG5JFLAiEes GEDmXKhmDHxx1AY5P4OHGfXHY307Dk63qu25+pSXuIsykolgBbqrylbhVDfRKQxutLfZ FbbwuqINVrnNdiE4btGAzPw9SBXpMYboa6sAmb6xKaSLydR9dXJbLV8ZSGCj4vHlY5E4 GZC0xSP1mOsVLHma5ulVWJt6la+8lzkyh6mP1/A4UmV0RE8v56gUookImTFJyFIuvTMK wFVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=CFJEkUj6StvnCLf3zA4XSa8BJ3U9++NnIiul0HVC8DY=; b=o9htipujV9fAYoMaJKigRGBJs0ujIN9/5OB0u9wEAQPkJADnDLzOirabLha6Ekf5eB XwPZMb1wLu1YGTOWArQT9P/2gCe7xjIYizjF2d4FrbFl5AXc0R51ixScO/rePyy3mk6/ uXo2dDLEyypzH9/1BzlaS3V0UCEO8ble7SbbmHCE2bEhhLUtlrKzS72bGBbS+44NpY2p GCi4NjmRzmq9MO3WgDm6yfR61ytkVjABFv1xNHDaL8ntMbIFoYaU14e2jlMoyd7Hrjdk d2yAz1jQCg5KgcgTkD3Hhe2skZRyqFOg2sa/O3sa4AyH/ZYgZ/xuGTt1/A+DZVDLpzuo RLFw== X-Gm-Message-State: AOAM53313EPXLJunGS+UcGSO7nNS1MRLhwsgGDhXZRMb8EdQs/yVbT1n qwMwOwHzlq6NYS7HfUo4QJ/W2mZKEHlaLkXp X-Google-Smtp-Source: ABdhPJw4YkJYmgRylLEqTzHlY0X6lACb5edwRo2U/kN+S0kiJOP4jgTMcfO+OOMCh+jui7yGQnaCsw== X-Received: by 2002:a1c:3b87:: with SMTP id i129mr15591490wma.134.1605527395152; Mon, 16 Nov 2020 03:49:55 -0800 (PST) Received: from google.com ([2a01:4b00:8523:2d03:58a8:7836:6672:a072]) by smtp.gmail.com with ESMTPSA id c17sm19262018wml.14.2020.11.16.03.49.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 03:49:54 -0800 (PST) Date: Mon, 16 Nov 2020 11:49:52 +0000 From: David Brazdil To: Marc Zyngier Cc: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, James Morse , Julien Thierry , Suzuki K Poulose , Catalin Marinas , Will Deacon , Dennis Zhou , Tejun Heo , Christoph Lameter , Mark Rutland , Lorenzo Pieralisi , Quentin Perret , Andrew Scull , Andrew Walbran , kernel-team@android.com Subject: Re: [PATCH v1 13/24] kvm: arm64: Add CPU entry point in nVHE hyp Message-ID: <20201116114952.ybj24wx44lofqs25@google.com> References: <20201109113233.9012-1-dbrazdil@google.com> <20201109113233.9012-14-dbrazdil@google.com> <7b8f9dec846f172c2919e1d3f3c65245@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7b8f9dec846f172c2919e1d3f3c65245@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > #ifdef CONFIG_CPU_PM > > DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp)); > > diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > b/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > index 1697d25756e9..f999a35b2c8c 100644 > > --- a/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > +++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > @@ -6,6 +6,7 @@ > > > > #include > > #include > > +#include > > This should probably be included from the file that provides init_el2_state. Agreed. This is a workaround for the fact that the arm-gic* headers don't play nice with each other (define the same constants). Including arm-gic-v3.h in kvm_asm.h will trigger macro redefine warnings in vgic*-v2.c because they include arm-gic.h. Another option is to create a header just for el2 init. Would that be preferable? Other ideas? > > > > > #include > > #include > > @@ -159,6 +160,35 @@ alternative_else_nop_endif > > ret > > SYM_CODE_END(___kvm_hyp_init) > > > > +SYM_CODE_START(__kvm_hyp_cpu_entry) > > + msr SPsel, #1 // We want to use SP_EL{1,2} > > + > > + /* > > + * Check that the core was booted in EL2. Loop indefinitely if not > > + * because it cannot be safely given to the host without installing > > KVM. > > + */ > > + mrs x1, CurrentEL > > + cmp x1, #CurrentEL_EL2 > > + b.ne . > > This is a bit brutal. Consider using a WFE/WFI loop as we have in other > places already (see __secondary_too_slow for example). Ack > > + > > + /* Initialize EL2 CPU state to sane values. */ > > + mov x29, x0 > > + init_el2_state nvhe > > + mov x0, x29 > > + > > + /* > > + * Load hyp VA of C entry function. Must do so before switching on the > > + * MMU because the struct pointer is PA and not identity-mapped in > > hyp. > > + */ > > + ldr x29, [x0, #NVHE_INIT_PSCI_CPU_ENTRY_FN] > > + > > + /* Enable MMU, set vectors and stack. */ > > + bl ___kvm_hyp_init > > + > > + /* Leave idmap. */ > > + br x29 > > To a point I made against an earlier patch: psci_cpu_entry_fn seems to be a > HYP > VA, and really needs to be documented as such, because this is pretty hard > to > follow otherwise. > > > +SYM_CODE_END(__kvm_hyp_cpu_entry) > > + > > SYM_CODE_START(__kvm_handle_stub_hvc) > > cmp x0, #HVC_SOFT_RESTART > > b.ne 1f > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny... 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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu > > #ifdef CONFIG_CPU_PM > > DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp)); > > diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > b/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > index 1697d25756e9..f999a35b2c8c 100644 > > --- a/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > +++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > @@ -6,6 +6,7 @@ > > > > #include > > #include > > +#include > > This should probably be included from the file that provides init_el2_state. Agreed. This is a workaround for the fact that the arm-gic* headers don't play nice with each other (define the same constants). Including arm-gic-v3.h in kvm_asm.h will trigger macro redefine warnings in vgic*-v2.c because they include arm-gic.h. Another option is to create a header just for el2 init. Would that be preferable? Other ideas? > > > > > #include > > #include > > @@ -159,6 +160,35 @@ alternative_else_nop_endif > > ret > > SYM_CODE_END(___kvm_hyp_init) > > > > +SYM_CODE_START(__kvm_hyp_cpu_entry) > > + msr SPsel, #1 // We want to use SP_EL{1,2} > > + > > + /* > > + * Check that the core was booted in EL2. Loop indefinitely if not > > + * because it cannot be safely given to the host without installing > > KVM. > > + */ > > + mrs x1, CurrentEL > > + cmp x1, #CurrentEL_EL2 > > + b.ne . > > This is a bit brutal. Consider using a WFE/WFI loop as we have in other > places already (see __secondary_too_slow for example). Ack > > + > > + /* Initialize EL2 CPU state to sane values. */ > > + mov x29, x0 > > + init_el2_state nvhe > > + mov x0, x29 > > + > > + /* > > + * Load hyp VA of C entry function. Must do so before switching on the > > + * MMU because the struct pointer is PA and not identity-mapped in > > hyp. > > + */ > > + ldr x29, [x0, #NVHE_INIT_PSCI_CPU_ENTRY_FN] > > + > > + /* Enable MMU, set vectors and stack. */ > > + bl ___kvm_hyp_init > > + > > + /* Leave idmap. */ > > + br x29 > > To a point I made against an earlier patch: psci_cpu_entry_fn seems to be a > HYP > VA, and really needs to be documented as such, because this is pretty hard > to > follow otherwise. > > > +SYM_CODE_END(__kvm_hyp_cpu_entry) > > + > > SYM_CODE_START(__kvm_handle_stub_hvc) > > cmp x0, #HVC_SOFT_RESTART > > b.ne 1f > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_ADSP_CUSTOM_MED,DKIM_SIGNED,DKIM_VALID,FSL_HELO_FAKE, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4107C4742C for ; Mon, 16 Nov 2020 12:47:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E9282137B for ; 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Mon, 16 Nov 2020 03:49:55 -0800 (PST) Received: from google.com ([2a01:4b00:8523:2d03:58a8:7836:6672:a072]) by smtp.gmail.com with ESMTPSA id c17sm19262018wml.14.2020.11.16.03.49.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 03:49:54 -0800 (PST) Date: Mon, 16 Nov 2020 11:49:52 +0000 From: David Brazdil To: Marc Zyngier Subject: Re: [PATCH v1 13/24] kvm: arm64: Add CPU entry point in nVHE hyp Message-ID: <20201116114952.ybj24wx44lofqs25@google.com> References: <20201109113233.9012-1-dbrazdil@google.com> <20201109113233.9012-14-dbrazdil@google.com> <7b8f9dec846f172c2919e1d3f3c65245@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <7b8f9dec846f172c2919e1d3f3c65245@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201116_064956_527999_94338A72 X-CRM114-Status: GOOD ( 21.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , kernel-team@android.com, Lorenzo Pieralisi , Andrew Walbran , Suzuki K Poulose , Catalin Marinas , Quentin Perret , linux-kernel@vger.kernel.org, James Morse , linux-arm-kernel@lists.infradead.org, Tejun Heo , Dennis Zhou , Christoph Lameter , Will Deacon , kvmarm@lists.cs.columbia.edu, Julien Thierry , Andrew Scull Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > > #ifdef CONFIG_CPU_PM > > DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp)); > > diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > b/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > index 1697d25756e9..f999a35b2c8c 100644 > > --- a/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > +++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S > > @@ -6,6 +6,7 @@ > > > > #include > > #include > > +#include > > This should probably be included from the file that provides init_el2_state. Agreed. This is a workaround for the fact that the arm-gic* headers don't play nice with each other (define the same constants). Including arm-gic-v3.h in kvm_asm.h will trigger macro redefine warnings in vgic*-v2.c because they include arm-gic.h. Another option is to create a header just for el2 init. Would that be preferable? Other ideas? > > > > > #include > > #include > > @@ -159,6 +160,35 @@ alternative_else_nop_endif > > ret > > SYM_CODE_END(___kvm_hyp_init) > > > > +SYM_CODE_START(__kvm_hyp_cpu_entry) > > + msr SPsel, #1 // We want to use SP_EL{1,2} > > + > > + /* > > + * Check that the core was booted in EL2. Loop indefinitely if not > > + * because it cannot be safely given to the host without installing > > KVM. > > + */ > > + mrs x1, CurrentEL > > + cmp x1, #CurrentEL_EL2 > > + b.ne . > > This is a bit brutal. Consider using a WFE/WFI loop as we have in other > places already (see __secondary_too_slow for example). Ack > > + > > + /* Initialize EL2 CPU state to sane values. */ > > + mov x29, x0 > > + init_el2_state nvhe > > + mov x0, x29 > > + > > + /* > > + * Load hyp VA of C entry function. Must do so before switching on the > > + * MMU because the struct pointer is PA and not identity-mapped in > > hyp. > > + */ > > + ldr x29, [x0, #NVHE_INIT_PSCI_CPU_ENTRY_FN] > > + > > + /* Enable MMU, set vectors and stack. */ > > + bl ___kvm_hyp_init > > + > > + /* Leave idmap. */ > > + br x29 > > To a point I made against an earlier patch: psci_cpu_entry_fn seems to be a > HYP > VA, and really needs to be documented as such, because this is pretty hard > to > follow otherwise. > > > +SYM_CODE_END(__kvm_hyp_cpu_entry) > > + > > SYM_CODE_START(__kvm_handle_stub_hvc) > > cmp x0, #HVC_SOFT_RESTART > > b.ne 1f > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel