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Mon, 16 Nov 2020 17:27:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8FF4DC43460 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=jcrouse@codeaurora.org Date: Mon, 16 Nov 2020 10:27:04 -0700 From: Jordan Crouse To: Rob Clark Cc: Jonathan Marek , David Airlie , freedreno , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Daniel Vetter , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Sean Paul , Christoph Hellwig Subject: Re: [Freedreno] [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance Message-ID: <20201116172703.GD16856@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Rob Clark , Jonathan Marek , David Airlie , freedreno , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Daniel Vetter , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Sean Paul , Christoph Hellwig References: <20201114151717.5369-1-jonathan@marek.ca> <20201114151717.5369-5-jonathan@marek.ca> <20201114162406.GC24411@lst.de> <50ddcadb-c630-2ef6-cdc4-724d9823fba7@marek.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Sat, Nov 14, 2020 at 11:39:45AM -0800, Rob Clark wrote: > On Sat, Nov 14, 2020 at 10:58 AM Jonathan Marek wrote: > > > > On 11/14/20 1:46 PM, Rob Clark wrote: > > > On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote: > > >> > > >> On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote: > > >>> +void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags, > > >>> + size_t range_start, size_t range_end) > > >>> +{ > > >>> + struct msm_gem_object *msm_obj = to_msm_bo(obj); > > >>> + struct device *dev = msm_obj->base.dev->dev; > > >>> + > > >>> + /* exit early if get_pages() hasn't been called yet */ > > >>> + if (!msm_obj->pages) > > >>> + return; > > >>> + > > >>> + /* TODO: sync only the specified range */ > > >>> + > > >>> + if (flags & MSM_GEM_SYNC_FOR_DEVICE) { > > >>> + dma_sync_sg_for_device(dev, msm_obj->sgt->sgl, > > >>> + msm_obj->sgt->nents, DMA_TO_DEVICE); > > >>> + } > > >>> + > > >>> + if (flags & MSM_GEM_SYNC_FOR_CPU) { > > >>> + dma_sync_sg_for_cpu(dev, msm_obj->sgt->sgl, > > >>> + msm_obj->sgt->nents, DMA_FROM_DEVICE); > > >>> + } > > >> > > >> Splitting this helper from the only caller is rather strange, epecially > > >> with the two unused arguments. And I think the way this is specified > > >> to take a range, but ignoring it is actively dangerous. User space will > > >> rely on it syncing everything sooner or later and then you are stuck. > > >> So just define a sync all primitive for now, and if you really need a > > >> range sync and have actually implemented it add a new ioctl for that. > > > > > > We do already have a split of ioctl "layer" which enforces valid ioctl > > > params, etc, and gem (or other) module code which is called by the > > > ioctl func. So I think it is fine to keep this split here. (Also, I > > > think at some point there will be a uring type of ioctl alternative > > > which would re-use the same gem func.) > > > > > > But I do agree that the range should be respected or added later.. > > > drm_ioctl() dispatch is well prepared for extending ioctls. > > > > > > And I assume there should be some validation that the range is aligned > > > to cache-line? Or can we flush a partial cache line? > > > > > > > The range is intended to be "sync at least this range", so that > > userspace doesn't have to worry about details like that. > > > > I don't think userspace can *not* worry about details like that. > Consider a case where the cpu and gpu are simultaneously accessing > different parts of a buffer (for ex, sub-allocation). There needs to > be cache-line separation between the two. There is at least one compute conformance test that I can think of that does exactly this. Jordan > BR, > -R > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 120E0C61DD8 for ; Mon, 16 Nov 2020 17:27:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C26EE221FD for ; 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Mon, 16 Nov 2020 17:27:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8FF4DC43460 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=jcrouse@codeaurora.org Date: Mon, 16 Nov 2020 10:27:04 -0700 From: Jordan Crouse To: Rob Clark Subject: Re: [Freedreno] [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance Message-ID: <20201116172703.GD16856@jcrouse1-lnx.qualcomm.com> Mail-Followup-To: Rob Clark , Jonathan Marek , David Airlie , freedreno , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Daniel Vetter , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Sean Paul , Christoph Hellwig References: <20201114151717.5369-1-jonathan@marek.ca> <20201114151717.5369-5-jonathan@marek.ca> <20201114162406.GC24411@lst.de> <50ddcadb-c630-2ef6-cdc4-724d9823fba7@marek.ca> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sean Paul , Jonathan Marek , David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , freedreno , Christoph Hellwig Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Sat, Nov 14, 2020 at 11:39:45AM -0800, Rob Clark wrote: > On Sat, Nov 14, 2020 at 10:58 AM Jonathan Marek wrote: > > > > On 11/14/20 1:46 PM, Rob Clark wrote: > > > On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote: > > >> > > >> On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote: > > >>> +void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags, > > >>> + size_t range_start, size_t range_end) > > >>> +{ > > >>> + struct msm_gem_object *msm_obj = to_msm_bo(obj); > > >>> + struct device *dev = msm_obj->base.dev->dev; > > >>> + > > >>> + /* exit early if get_pages() hasn't been called yet */ > > >>> + if (!msm_obj->pages) > > >>> + return; > > >>> + > > >>> + /* TODO: sync only the specified range */ > > >>> + > > >>> + if (flags & MSM_GEM_SYNC_FOR_DEVICE) { > > >>> + dma_sync_sg_for_device(dev, msm_obj->sgt->sgl, > > >>> + msm_obj->sgt->nents, DMA_TO_DEVICE); > > >>> + } > > >>> + > > >>> + if (flags & MSM_GEM_SYNC_FOR_CPU) { > > >>> + dma_sync_sg_for_cpu(dev, msm_obj->sgt->sgl, > > >>> + msm_obj->sgt->nents, DMA_FROM_DEVICE); > > >>> + } > > >> > > >> Splitting this helper from the only caller is rather strange, epecially > > >> with the two unused arguments. And I think the way this is specified > > >> to take a range, but ignoring it is actively dangerous. User space will > > >> rely on it syncing everything sooner or later and then you are stuck. > > >> So just define a sync all primitive for now, and if you really need a > > >> range sync and have actually implemented it add a new ioctl for that. > > > > > > We do already have a split of ioctl "layer" which enforces valid ioctl > > > params, etc, and gem (or other) module code which is called by the > > > ioctl func. So I think it is fine to keep this split here. (Also, I > > > think at some point there will be a uring type of ioctl alternative > > > which would re-use the same gem func.) > > > > > > But I do agree that the range should be respected or added later.. > > > drm_ioctl() dispatch is well prepared for extending ioctls. > > > > > > And I assume there should be some validation that the range is aligned > > > to cache-line? Or can we flush a partial cache line? > > > > > > > The range is intended to be "sync at least this range", so that > > userspace doesn't have to worry about details like that. > > > > I don't think userspace can *not* worry about details like that. > Consider a case where the cpu and gpu are simultaneously accessing > different parts of a buffer (for ex, sub-allocation). There needs to > be cache-line separation between the two. There is at least one compute conformance test that I can think of that does exactly this. Jordan > BR, > -R > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel