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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id y10sm1618407pjm.34.2020.11.18.00.31.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Nov 2020 00:31:55 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC 00/15] support subsets of bitmanip extension Date: Wed, 18 Nov 2020 16:29:38 +0800 Message-Id: <20201118083044.13992-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x630.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang This patchset implements RISC-V B-extension latest draft version (2020.10.26) Zbb, Zbs and Zba subset instructions. Specification: https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf The port is available here: https://github.com/sifive/qemu/tree/rvb-upstream-v1 To test rvb implementation, specify cpu argument with 'x-b=true' to enable B-extension support. Frank Chang (2): target/riscv: rvb: generalized reverse target/riscv: rvb: generalized or-combine Kito Cheng (13): target/riscv: reformat @sh format encoding for B-extension target/riscv: rvb: count leading/trailing zeros target/riscv: rvb: count bits set target/riscv: rvb: logic-with-negate target/riscv: rvb: pack two words into one register target/riscv: rvb: min/max instructions target/riscv: rvb: sign-extend instructions target/riscv: rvb: single-bit instructions target/riscv: rvb: shift ones target/riscv: rvb: rotate (left/right) target/riscv: rvb: address calculation target/riscv: rvb: add/sub with postfix zero-extend target/riscv: rvb: support and turn on B-extension from command line target/riscv/bitmanip_helper.c | 128 +++++ target/riscv/cpu.c | 4 + target/riscv/cpu.h | 2 + target/riscv/helper.h | 9 + target/riscv/insn32-64.decode | 37 ++ target/riscv/insn32.decode | 54 ++- target/riscv/insn_trans/trans_rvb.c.inc | 475 +++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 597 ++++++++++++++++++++++++ 9 files changed, 1301 insertions(+), 6 deletions(-) create mode 100644 target/riscv/bitmanip_helper.c create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc -- 2.17.1