From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH v2 28/28] target/arm: Implement Cortex-M55 model
Date: Thu, 19 Nov 2020 21:56:17 +0000 [thread overview]
Message-ID: <20201119215617.29887-29-peter.maydell@linaro.org> (raw)
In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org>
Now that we have implemented all the features needed by the v8.1M
architecture, we can add the model of the Cortex-M55. This is the
configuration without MVE support; we'll add MVE later.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 0013e25412f..98544db2df3 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -401,6 +401,46 @@ static void cortex_m33_initfn(Object *obj)
cpu->ctr = 0x8000c000;
}
+static void cortex_m55_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_V8_1M);
+ set_feature(&cpu->env, ARM_FEATURE_M);
+ set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
+ set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
+ cpu->midr = 0x410fd221; /* r0p1 */
+ cpu->revidr = 0;
+ cpu->pmsav7_dregion = 16;
+ cpu->sau_sregion = 8;
+ /*
+ * These are the MVFR* values for the FPU, no MVE configuration;
+ * we will update them later when we implement MVE
+ */
+ cpu->isar.mvfr0 = 0x10110221;
+ cpu->isar.mvfr1 = 0x12100011;
+ cpu->isar.mvfr2 = 0x00000040;
+ cpu->isar.id_pfr0 = 0x20000030;
+ cpu->isar.id_pfr1 = 0x00000230;
+ cpu->isar.id_dfr0 = 0x10200000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00111040;
+ cpu->isar.id_mmfr1 = 0x00000000;
+ cpu->isar.id_mmfr2 = 0x01000000;
+ cpu->isar.id_mmfr3 = 0x00000011;
+ cpu->isar.id_isar0 = 0x01103110;
+ cpu->isar.id_isar1 = 0x02212000;
+ cpu->isar.id_isar2 = 0x20232232;
+ cpu->isar.id_isar3 = 0x01111131;
+ cpu->isar.id_isar4 = 0x01310132;
+ cpu->isar.id_isar5 = 0x00000000;
+ cpu->isar.id_isar6 = 0x00000000;
+ cpu->clidr = 0x00000000; /* caches not implemented */
+ cpu->ctr = 0x8303c003;
+}
+
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
/* Dummy the TCM region regs for the moment */
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
@@ -655,6 +695,8 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
.class_init = arm_v7m_class_init },
{ .name = "cortex-m33", .initfn = cortex_m33_initfn,
.class_init = arm_v7m_class_init },
+ { .name = "cortex-m55", .initfn = cortex_m55_initfn,
+ .class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
{ .name = "ti925t", .initfn = ti925t_initfn },
--
2.20.1
next prev parent reply other threads:[~2020-11-19 22:13 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 21:55 [PATCH v2 00/28] target/arm: Implement v8.1M and Cortex-M55 Peter Maydell
2020-11-19 21:55 ` [PATCH v2 01/28] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault Peter Maydell
2020-11-19 21:55 ` [PATCH v2 02/28] target/arm: Implement v8.1M PXN extension Peter Maydell
2020-11-19 21:55 ` [PATCH v2 03/28] target/arm: Don't clobber ID_PFR1.Security on M-profile cores Peter Maydell
2020-11-19 21:55 ` [PATCH v2 04/28] target/arm: Implement VSCCLRM insn Peter Maydell
2020-11-19 21:55 ` [PATCH v2 05/28] target/arm: Implement CLRM instruction Peter Maydell
2020-11-19 21:55 ` [PATCH v2 06/28] target/arm: Enforce M-profile VMRS/VMSR register restrictions Peter Maydell
2020-11-19 21:55 ` [PATCH v2 07/28] target/arm: Refactor M-profile VMSR/VMRS handling Peter Maydell
2020-12-01 12:54 ` Richard Henderson
2020-11-19 21:55 ` [PATCH v2 08/28] target/arm: Move general-use constant expanders up in translate.c Peter Maydell
2020-11-19 21:55 ` [PATCH v2 09/28] target/arm: Implement VLDR/VSTR system register Peter Maydell
2020-12-01 13:11 ` Richard Henderson
2020-12-03 11:39 ` Peter Maydell
2020-12-03 16:14 ` Richard Henderson
2020-11-19 21:55 ` [PATCH v2 10/28] target/arm: Implement M-profile FPSCR_nzcvqc Peter Maydell
2020-12-01 13:16 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 11/28] target/arm: Use new FPCR_NZCV_MASK constant Peter Maydell
2020-11-19 21:56 ` [PATCH v2 12/28] target/arm: Factor out preserve-fp-state from full_vfp_access_check() Peter Maydell
2020-11-19 22:18 ` Philippe Mathieu-Daudé
2020-11-19 21:56 ` [PATCH v2 13/28] target/arm: Implement FPCXT_S fp system register Peter Maydell
2020-12-01 13:40 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 14/28] target/arm: Implement FPCXT_NS " Peter Maydell
2020-12-01 14:05 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 15/28] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M Peter Maydell
2020-12-01 14:28 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 16/28] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry Peter Maydell
2020-12-01 14:33 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 17/28] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures Peter Maydell
2020-12-01 14:41 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 18/28] target/arm: Implement v8.1M REVIDR register Peter Maydell
2020-12-01 14:43 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 19/28] target/arm: Implement new v8.1M NOCP check for exception return Peter Maydell
2020-12-01 14:49 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 20/28] target/arm: Implement new v8.1M VLLDM and VLSTM encodings Peter Maydell
2020-12-01 15:09 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 21/28] hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN Peter Maydell
2020-12-01 15:16 ` Richard Henderson
2020-12-01 15:22 ` Peter Maydell
2020-11-19 21:56 ` [PATCH v2 22/28] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit Peter Maydell
2020-12-01 15:19 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 23/28] target/arm: Implement CCR_S.TRD behaviour for SG insns Peter Maydell
2020-12-01 15:53 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 24/28] hw/intc/armv7m_nvic: Fix "return from inactive handler" check Peter Maydell
2020-12-01 15:58 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 25/28] target/arm: Implement M-profile "minimal RAS implementation" Peter Maydell
2020-12-01 16:04 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 26/28] hw/intc/armv7m_nvic: Implement read/write for RAS register block Peter Maydell
2020-12-01 16:11 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 27/28] hw/arm/armv7m: Correct typo in QOM object name Peter Maydell
2020-11-19 22:19 ` Philippe Mathieu-Daudé
2020-12-01 16:12 ` Richard Henderson
2020-11-19 21:56 ` Peter Maydell [this message]
2020-12-01 16:24 ` [PATCH v2 28/28] target/arm: Implement Cortex-M55 model Richard Henderson
2020-12-03 12:02 ` [PATCH v2 00/28] target/arm: Implement v8.1M and Cortex-M55 Peter Maydell
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