From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ED39C63798 for ; Wed, 25 Nov 2020 15:50:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01D46206CA for ; Wed, 25 Nov 2020 15:50:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731603AbgKYPuE (ORCPT ); Wed, 25 Nov 2020 10:50:04 -0500 Received: from foss.arm.com ([217.140.110.172]:55794 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730318AbgKYPuE (ORCPT ); Wed, 25 Nov 2020 10:50:04 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DA8FD11D4; Wed, 25 Nov 2020 07:50:03 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1657E3F7BB; Wed, 25 Nov 2020 07:50:02 -0800 (PST) From: Alexandru Elisei To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, drjones@redhat.com Cc: eric.auger@redhat.com, andre.przywara@arm.com Subject: [kvm-unit-tests PATCH 01/10] lib: arm/arm64: gicv3: Add missing barrier when sending IPIs Date: Wed, 25 Nov 2020 15:51:04 +0000 Message-Id: <20201125155113.192079-2-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125155113.192079-1-alexandru.elisei@arm.com> References: <20201125155113.192079-1-alexandru.elisei@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org One common usage for IPIs is for one CPU to write to a shared memory location, send the IPI to kick another CPU, and the receiver to read from the same location. Proper synchronization is needed to make sure that the IPI receiver reads the most recent value and not stale data (for example, the write from the sender CPU might still be in a store buffer). For GICv3, IPIs are generated with a write to the ICC_SGI1R_EL1 register. To make sure the memory stores are observable by other CPUs, we need a wmb() barrier (DSB ST), which waits for stores to complete. >From the definition of DSB from ARM DDI 0487F.b, page B2-139: "In addition, no instruction that appears in program order after the DSB instruction can alter any state of the system or perform any part of its functionality until the DSB completes other than: - Being fetched from memory and decoded. - Reading the general-purpose, SIMD and floating-point, Special-purpose, or System registers that are directly or indirectly read without causing side-effects." Similar definition for armv7 (ARM DDI 0406C.d, page A3-150). The DSB instruction is enough to prevent reordering of the GIC register write which comes in program order after the memory access. This also matches what the Linux GICv3 irqchip driver does (commit 21ec30c0ef52 ("irqchip/gic-v3: Use wmb() instead of smb_wmb() in gic_raise_softirq()")). Signed-off-by: Alexandru Elisei --- lib/arm/gic-v3.c | 3 +++ arm/gic.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c index a7e2cb819746..a6afa42d5fbe 100644 --- a/lib/arm/gic-v3.c +++ b/lib/arm/gic-v3.c @@ -77,6 +77,9 @@ void gicv3_ipi_send_mask(int irq, const cpumask_t *dest) assert(irq < 16); + /* Ensure stores are visible to other CPUs before sending the IPI */ + wmb(); + /* * For each cpu in the mask collect its peers, which are also in * the mask, in order to form target lists. diff --git a/arm/gic.c b/arm/gic.c index acb060585fae..512c83636a2e 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -275,6 +275,8 @@ static void gicv3_ipi_send_self(void) static void gicv3_ipi_send_broadcast(void) { + /* Ensure stores are visible to other CPUs before sending the IPI */ + wmb(); gicv3_write_sgi1r(1ULL << 40 | IPI_IRQ << 24); isb(); } -- 2.29.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7D9BC56202 for ; Wed, 25 Nov 2020 15:50:10 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 42D40207BC for ; Wed, 25 Nov 2020 15:50:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 42D40207BC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id AEC4A4B9E3; Wed, 25 Nov 2020 10:50:09 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eeqyC3NqHvEb; Wed, 25 Nov 2020 10:50:08 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 5A6A64B9D0; Wed, 25 Nov 2020 10:50:07 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 4B8684B9C1 for ; Wed, 25 Nov 2020 10:50:05 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QbHKaOyqL8p9 for ; Wed, 25 Nov 2020 10:50:04 -0500 (EST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 31A984B9C3 for ; Wed, 25 Nov 2020 10:50:04 -0500 (EST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DA8FD11D4; Wed, 25 Nov 2020 07:50:03 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1657E3F7BB; Wed, 25 Nov 2020 07:50:02 -0800 (PST) From: Alexandru Elisei To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, drjones@redhat.com Subject: [kvm-unit-tests PATCH 01/10] lib: arm/arm64: gicv3: Add missing barrier when sending IPIs Date: Wed, 25 Nov 2020 15:51:04 +0000 Message-Id: <20201125155113.192079-2-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125155113.192079-1-alexandru.elisei@arm.com> References: <20201125155113.192079-1-alexandru.elisei@arm.com> MIME-Version: 1.0 Cc: andre.przywara@arm.com X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu One common usage for IPIs is for one CPU to write to a shared memory location, send the IPI to kick another CPU, and the receiver to read from the same location. Proper synchronization is needed to make sure that the IPI receiver reads the most recent value and not stale data (for example, the write from the sender CPU might still be in a store buffer). For GICv3, IPIs are generated with a write to the ICC_SGI1R_EL1 register. To make sure the memory stores are observable by other CPUs, we need a wmb() barrier (DSB ST), which waits for stores to complete. >From the definition of DSB from ARM DDI 0487F.b, page B2-139: "In addition, no instruction that appears in program order after the DSB instruction can alter any state of the system or perform any part of its functionality until the DSB completes other than: - Being fetched from memory and decoded. - Reading the general-purpose, SIMD and floating-point, Special-purpose, or System registers that are directly or indirectly read without causing side-effects." Similar definition for armv7 (ARM DDI 0406C.d, page A3-150). The DSB instruction is enough to prevent reordering of the GIC register write which comes in program order after the memory access. This also matches what the Linux GICv3 irqchip driver does (commit 21ec30c0ef52 ("irqchip/gic-v3: Use wmb() instead of smb_wmb() in gic_raise_softirq()")). Signed-off-by: Alexandru Elisei --- lib/arm/gic-v3.c | 3 +++ arm/gic.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c index a7e2cb819746..a6afa42d5fbe 100644 --- a/lib/arm/gic-v3.c +++ b/lib/arm/gic-v3.c @@ -77,6 +77,9 @@ void gicv3_ipi_send_mask(int irq, const cpumask_t *dest) assert(irq < 16); + /* Ensure stores are visible to other CPUs before sending the IPI */ + wmb(); + /* * For each cpu in the mask collect its peers, which are also in * the mask, in order to form target lists. diff --git a/arm/gic.c b/arm/gic.c index acb060585fae..512c83636a2e 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -275,6 +275,8 @@ static void gicv3_ipi_send_self(void) static void gicv3_ipi_send_broadcast(void) { + /* Ensure stores are visible to other CPUs before sending the IPI */ + wmb(); gicv3_write_sgi1r(1ULL << 40 | IPI_IRQ << 24); isb(); } -- 2.29.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm