From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD588C64E75 for ; Wed, 25 Nov 2020 15:50:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 83B1A205CB for ; Wed, 25 Nov 2020 15:50:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731653AbgKYPuI (ORCPT ); Wed, 25 Nov 2020 10:50:08 -0500 Received: from foss.arm.com ([217.140.110.172]:55806 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730318AbgKYPuG (ORCPT ); Wed, 25 Nov 2020 10:50:06 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E482A11D4; Wed, 25 Nov 2020 07:50:05 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1F7E63F7BB; Wed, 25 Nov 2020 07:50:05 -0800 (PST) From: Alexandru Elisei To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, drjones@redhat.com Cc: eric.auger@redhat.com, andre.przywara@arm.com Subject: [kvm-unit-tests PATCH 03/10] arm/arm64: gic: Remove memory synchronization from ipi_clear_active_handler() Date: Wed, 25 Nov 2020 15:51:06 +0000 Message-Id: <20201125155113.192079-4-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125155113.192079-1-alexandru.elisei@arm.com> References: <20201125155113.192079-1-alexandru.elisei@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The gicv{2,3}-active test sends an IPI from the boot CPU to itself, then checks that the interrupt has been received as expected. There is no need to use inter-processor memory synchronization primitives on code that runs on the same CPU, so remove the unneeded memory barriers. The arrays are modified asynchronously (in the interrupt handler) and it is possible for the compiler to infer that they won't be changed during normal program flow and try to perform harmful optimizations (like stashing a previous read in a register and reusing it). To prevent this, for GICv2, the smp_wmb() in gicv2_ipi_send_self() is replaced with a compiler barrier. For GICv3, the wmb() barrier in gic_ipi_send_single() already implies a compiler barrier. Signed-off-by: Alexandru Elisei --- arm/gic.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index 401ffafe4299..4e947e8516a2 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -12,6 +12,7 @@ * This work is licensed under the terms of the GNU LGPL, version 2. */ #include +#include #include #include #include @@ -260,7 +261,8 @@ static void check_lpi_hits(int *expected, const char *msg) static void gicv2_ipi_send_self(void) { - smp_wmb(); + /* Prevent the compiler from optimizing memory accesses */ + barrier(); writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR); } @@ -359,6 +361,7 @@ static struct gic gicv3 = { }, }; +/* Runs on the same CPU as the sender, no need for memory synchronization */ static void ipi_clear_active_handler(struct pt_regs *regs __unused) { u32 irqstat = gic_read_iar(); @@ -375,13 +378,10 @@ static void ipi_clear_active_handler(struct pt_regs *regs __unused) writel(val, base + GICD_ICACTIVER); - smp_rmb(); /* pairs with wmb in stats_reset */ ++acked[smp_processor_id()]; check_irqnr(irqnr); - smp_wmb(); /* pairs with rmb in check_acked */ } else { ++spurious[smp_processor_id()]; - smp_wmb(); } } -- 2.29.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 912F8C6379D for ; Wed, 25 Nov 2020 15:50:12 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id F0250205CB for ; Wed, 25 Nov 2020 15:50:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F0250205CB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 9014F4BA02; Wed, 25 Nov 2020 10:50:11 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7ezOeVxvpijy; Wed, 25 Nov 2020 10:50:10 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 98F444B9CF; Wed, 25 Nov 2020 10:50:09 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 4FC7F4B9C4 for ; Wed, 25 Nov 2020 10:50:07 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5a0KIV0EsEKQ for ; Wed, 25 Nov 2020 10:50:06 -0500 (EST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 3ACED4B9C5 for ; Wed, 25 Nov 2020 10:50:06 -0500 (EST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E482A11D4; Wed, 25 Nov 2020 07:50:05 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1F7E63F7BB; Wed, 25 Nov 2020 07:50:05 -0800 (PST) From: Alexandru Elisei To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, drjones@redhat.com Subject: [kvm-unit-tests PATCH 03/10] arm/arm64: gic: Remove memory synchronization from ipi_clear_active_handler() Date: Wed, 25 Nov 2020 15:51:06 +0000 Message-Id: <20201125155113.192079-4-alexandru.elisei@arm.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201125155113.192079-1-alexandru.elisei@arm.com> References: <20201125155113.192079-1-alexandru.elisei@arm.com> MIME-Version: 1.0 Cc: andre.przywara@arm.com X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu The gicv{2,3}-active test sends an IPI from the boot CPU to itself, then checks that the interrupt has been received as expected. There is no need to use inter-processor memory synchronization primitives on code that runs on the same CPU, so remove the unneeded memory barriers. The arrays are modified asynchronously (in the interrupt handler) and it is possible for the compiler to infer that they won't be changed during normal program flow and try to perform harmful optimizations (like stashing a previous read in a register and reusing it). To prevent this, for GICv2, the smp_wmb() in gicv2_ipi_send_self() is replaced with a compiler barrier. For GICv3, the wmb() barrier in gic_ipi_send_single() already implies a compiler barrier. Signed-off-by: Alexandru Elisei --- arm/gic.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index 401ffafe4299..4e947e8516a2 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -12,6 +12,7 @@ * This work is licensed under the terms of the GNU LGPL, version 2. */ #include +#include #include #include #include @@ -260,7 +261,8 @@ static void check_lpi_hits(int *expected, const char *msg) static void gicv2_ipi_send_self(void) { - smp_wmb(); + /* Prevent the compiler from optimizing memory accesses */ + barrier(); writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR); } @@ -359,6 +361,7 @@ static struct gic gicv3 = { }, }; +/* Runs on the same CPU as the sender, no need for memory synchronization */ static void ipi_clear_active_handler(struct pt_regs *regs __unused) { u32 irqstat = gic_read_iar(); @@ -375,13 +378,10 @@ static void ipi_clear_active_handler(struct pt_regs *regs __unused) writel(val, base + GICD_ICACTIVER); - smp_rmb(); /* pairs with wmb in stats_reset */ ++acked[smp_processor_id()]; check_irqnr(irqnr); - smp_wmb(); /* pairs with rmb in check_acked */ } else { ++spurious[smp_processor_id()]; - smp_wmb(); } } -- 2.29.2 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm