From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEFA2C64E7B for ; Mon, 30 Nov 2020 23:08:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 77D1B20857 for ; Mon, 30 Nov 2020 23:08:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730974AbgK3XI2 (ORCPT ); Mon, 30 Nov 2020 18:08:28 -0500 Received: from mga01.intel.com ([192.55.52.88]:23561 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727590AbgK3XI1 (ORCPT ); Mon, 30 Nov 2020 18:08:27 -0500 IronPort-SDR: YmdvjUFTuEHZc8d7Ar+OkzNDgcHO2maEyKIvTCA9YgmpfekWCLNaYfc7MrXeeUUXEL7UmbbfR2 Tn+6e9s0olyg== X-IronPort-AV: E=McAfee;i="6000,8403,9821"; a="190917246" X-IronPort-AV: E=Sophos;i="5.78,382,1599548400"; d="scan'208";a="190917246" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2020 15:07:09 -0800 IronPort-SDR: cZDlgJaLX2BETdCJLqtbHp2k5oLEIafFOlWLOnMzqspwmeVQnQavbWx30Zc3SMdJt3rH40XUN5 G+3W2DUahoXA== X-IronPort-AV: E=Sophos;i="5.78,382,1599548400"; d="scan'208";a="404892841" Received: from smtp.ostc.intel.com ([10.54.29.231]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2020 15:07:09 -0800 Received: from mtg-dev (mtg-dev.jf.intel.com [10.54.74.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.ostc.intel.com (Postfix) with ESMTPS id A2C5D636D; Mon, 30 Nov 2020 15:07:09 -0800 (PST) Received: from mgross by mtg-dev with local (Exim 4.90_1) (envelope-from ) id 1kjsGD-000C4l-Ge; Mon, 30 Nov 2020 15:07:09 -0800 From: mgross@linux.intel.com To: linux-kernel@vger.kernel.org Cc: markgross@kernel.org, mgross@linux.intel.com, adam.r.gretzinger@intel.com, Daniele Alessandrelli , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH 02/22] dt-bindings: Add bindings for Keem Bay IPC driver Date: Mon, 30 Nov 2020 15:06:47 -0800 Message-Id: <20201130230707.46351-3-mgross@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201130230707.46351-1-mgross@linux.intel.com> References: <20201130230707.46351-1-mgross@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Daniele Alessandrelli Add DT binding documentation for the Intel Keem Bay IPC driver, which enables communication between the Computing Sub-System (CSS) and the Multimedia Sub-System (MSS) of the Intel Movidius SoC code named Keem Bay. Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Mark Gross Signed-off-by: Daniele Alessandrelli --- .../bindings/soc/intel/intel,keembay-ipc.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml diff --git a/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml new file mode 100644 index 000000000000..6e21c54d8f34 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-ipc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Intel Corporation +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-ipc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Keem Bay IPC + +maintainers: + - Daniele Alessandrelli + +description: + The Keem Bay IPC driver enables Inter-Processor Communication (IPC) with the + Visual Processor Unit (VPU) embedded in the Intel Movidius SoC code named + Keem Bay. + +properties: + compatible: + const: intel,keembay-ipc + + reg: + items: + - description: The CSS (CPU) FIFO registers + - description: The MSS (VPU) FIFO registers + + reg-names: + items: + - const: css_fifo + - const: mss_fifo + + interrupts: + items: + - description: CSS FIFO not-empty interrupt + + interrupt-controller: true + + memory-region: + items: + - description: Reserved memory region used for CSS IPC buffers + - description: Reserved memory region used for MSS IPC buffers + +required: + - compatible + - reg + - reg-names + - interrupts + - memory-region + +additionalProperties: false + +examples: + - | + #include + #include + ipc@203300f0 { + compatible = "intel,keembay-ipc"; + reg = <0x203300f0 0x310>, /* CPU TIM FIFO */ + <0x208200f0 0x310>; /* VPU TIM FIFO */ + reg-names = "css_fifo", "mss_fifo"; + interrupts = ; + memory-region = <&css_ipc_reserved>, <&mss_ipc_reserved>; + }; -- 2.17.1