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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Huacai Chen <chenhc@lemote.com>,
	qemu-devel@nongnu.org, Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH 1/3] target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
Date: Tue,  1 Dec 2020 14:28:15 +0100	[thread overview]
Message-ID: <20201201132817.2863301-2-f4bug@amsat.org> (raw)
In-Reply-To: <20201201132817.2863301-1-f4bug@amsat.org>

The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.h | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 23f8c6f96cd..05291cee4db 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -828,7 +828,7 @@ struct CPUMIPSState {
 #define CP0EBase_WG 11
     target_ulong CP0_CMGCRBase;
 /*
- * CP0 Register 16
+ * CP0 Register 16 (after Release 1)
  */
     int32_t CP0_Config0;
 #define CP0C0_M    31
@@ -837,13 +837,20 @@ struct CPUMIPSState {
 #define CP0C0_MDU  20
 #define CP0C0_MM   18
 #define CP0C0_BM   16
-#define CP0C0_Impl 16    /* 24..16 */
 #define CP0C0_BE   15
 #define CP0C0_AT   13    /* 14..13 */
 #define CP0C0_AR   10    /* 12..10 */
 #define CP0C0_MT   7     /*  9..7  */
 #define CP0C0_VI   3
 #define CP0C0_K0   0     /*  2..0  */
+/*
+ * CP0 Register 16 (before Release 1)
+ */
+#define CP0C0_Impl 16    /* 24..16 */
+#define CP0C0_IC   9     /* 11..9 */
+#define CP0C0_DC   6     /*  8..6 */
+#define CP0C0_IB   5
+#define CP0C0_DB   4
     int32_t CP0_Config1;
 #define CP0C1_M    31
 #define CP0C1_MMU  25    /* 30..25 */
-- 
2.26.2



  reply	other threads:[~2020-12-01 13:31 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-01 13:28 [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions Philippe Mathieu-Daudé
2020-12-01 13:28 ` Philippe Mathieu-Daudé [this message]
2020-12-01 13:28 ` [PATCH 2/3] target/mips: Replace CP0_Config0 magic values by proper definitions Philippe Mathieu-Daudé
2020-12-01 13:28 ` [PATCH 3/3] target/mips: Explicit Release 6 MMU types Philippe Mathieu-Daudé
2020-12-01 16:30 ` [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions Richard Henderson
2020-12-07 22:31 ` Philippe Mathieu-Daudé

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