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Mon, 7 Dec 2020 10:04:28 +0000 (GMT) Received: from linux.ibm.com (unknown [9.145.50.18]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Mon, 7 Dec 2020 10:04:28 +0000 (GMT) Date: Mon, 7 Dec 2020 12:04:26 +0200 From: Mike Rapoport To: Ard Biesheuvel Cc: Marc Zyngier , Will Deacon , Wei Li , Barry Song , Steve Capper , Catalin Marinas , Linux Kernel Mailing List , fengbaopeng2@hisilicon.com, butao@hisilicon.com, Nicolas Saenz Julienne , Linux ARM Subject: Re: [PATCH] arm64: mm: decrease the section size to reduce the memory reserved for the page map Message-ID: <20201207100426.GE1112728@linux.ibm.com> References: <20201204014443.43329-1-liwei213@huawei.com> <20201204111347.GA844@willie-the-truck> <390f5f441d99a832f4b2425b46f6d971@kernel.org> <20201207094215.GC1112728@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312,18.0.737 definitions=2020-12-07_08:2020-12-04,2020-12-07 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 suspectscore=5 mlxlogscore=999 phishscore=0 clxscore=1015 spamscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2012070063 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Dec 07, 2020 at 10:49:26AM +0100, Ard Biesheuvel wrote: > On Mon, 7 Dec 2020 at 10:42, Mike Rapoport wrote: > > > > On Mon, Dec 07, 2020 at 09:35:06AM +0000, Marc Zyngier wrote: > > > On 2020-12-07 09:09, Ard Biesheuvel wrote: > > > > (+ Marc) > > > > > > > > On Fri, 4 Dec 2020 at 12:14, Will Deacon wrote: > > > > > > > > > > On Fri, Dec 04, 2020 at 09:44:43AM +0800, Wei Li wrote: > > > > > > For the memory hole, sparse memory model that define SPARSEMEM_VMEMMAP > > > > > > do not free the reserved memory for the page map, decrease the section > > > > > > size can reduce the waste of reserved memory. > > > > > > > > > > > > Signed-off-by: Wei Li > > > > > > Signed-off-by: Baopeng Feng > > > > > > Signed-off-by: Xia Qing > > > > > > --- > > > > > > arch/arm64/include/asm/sparsemem.h | 2 +- > > > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/arch/arm64/include/asm/sparsemem.h b/arch/arm64/include/asm/sparsemem.h > > > > > > index 1f43fcc79738..8963bd3def28 100644 > > > > > > --- a/arch/arm64/include/asm/sparsemem.h > > > > > > +++ b/arch/arm64/include/asm/sparsemem.h > > > > > > @@ -7,7 +7,7 @@ > > > > > > > > > > > > #ifdef CONFIG_SPARSEMEM > > > > > > #define MAX_PHYSMEM_BITS CONFIG_ARM64_PA_BITS > > > > > > -#define SECTION_SIZE_BITS 30 > > > > > > +#define SECTION_SIZE_BITS 27 > > > > > > > > > > We chose '30' to avoid running out of bits in the page flags. What > > > > > changed? > > > > > > > > > > With this patch, I can trigger: > > > > > > > > > > ./include/linux/mmzone.h:1170:2: error: Allocator MAX_ORDER exceeds > > > > > SECTION_SIZE > > > > > #error Allocator MAX_ORDER exceeds SECTION_SIZE > > > > > > > > > > if I bump up NR_CPUS and NODES_SHIFT. > > > > > > > > > > > > > Does this mean we will run into problems with the GICv3 ITS LPI tables > > > > again if we are forced to reduce MAX_ORDER to fit inside > > > > SECTION_SIZE_BITS? > > > > > > Most probably. We are already massively constraint on platforms > > > such as TX1, and dividing the max allocatable range by 8 isn't > > > going to make it work any better... > > > > I don't think MAX_ORDER should shrink. Even if SECTION_SIZE_BITS is > > reduced it should accomodate the existing MAX_ORDER. > > > > My two pennies. > > > > But include/linux/mmzone.h:1170 has this: > > #if (MAX_ORDER - 1 + PAGE_SHIFT) > SECTION_SIZE_BITS > #error Allocator MAX_ORDER exceeds SECTION_SIZE > #endif > > and Will managed to trigger it after applying this patch. Right, because with 64K pages section size of 27 bits is not enough to accomodate MAX_ORDER (2^13 pages of 64K). Which means that definition of SECTION_SIZE_BITS should take MAX_ORDER into account either statically with #ifdef ARM64_4K_PAGES #define SECTION_SIZE_BITS #elif ARM64_16K_PAGES #define SECTION_SIZE_BITS #elif ARM64_64K_PAGES #define SECTION_SIZE_BITS #else #error "and what is the page size?" #endif or dynamically, like e.g. ia64 does: #ifdef CONFIG_FORCE_MAX_ZONEORDER #if ((CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT) > SECTION_SIZE_BITS) #undef SECTION_SIZE_BITS #define SECTION_SIZE_BITS (CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT) #endif -- Sincerely yours, Mike. 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Mon, 7 Dec 2020 10:04:28 +0000 (GMT) Received: from linux.ibm.com (unknown [9.145.50.18]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Mon, 7 Dec 2020 10:04:28 +0000 (GMT) Date: Mon, 7 Dec 2020 12:04:26 +0200 From: Mike Rapoport To: Ard Biesheuvel Subject: Re: [PATCH] arm64: mm: decrease the section size to reduce the memory reserved for the page map Message-ID: <20201207100426.GE1112728@linux.ibm.com> References: <20201204014443.43329-1-liwei213@huawei.com> <20201204111347.GA844@willie-the-truck> <390f5f441d99a832f4b2425b46f6d971@kernel.org> <20201207094215.GC1112728@linux.ibm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-12-07_08:2020-12-04, 2020-12-07 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 suspectscore=5 mlxlogscore=999 phishscore=0 clxscore=1015 spamscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2012070063 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201207_050527_022130_42643592 X-CRM114-Status: GOOD ( 37.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Barry Song , Linux ARM , Steve Capper , Marc Zyngier , Linux Kernel Mailing List , Wei Li , Catalin Marinas , butao@hisilicon.com, Will Deacon , Nicolas Saenz Julienne , fengbaopeng2@hisilicon.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Dec 07, 2020 at 10:49:26AM +0100, Ard Biesheuvel wrote: > On Mon, 7 Dec 2020 at 10:42, Mike Rapoport wrote: > > > > On Mon, Dec 07, 2020 at 09:35:06AM +0000, Marc Zyngier wrote: > > > On 2020-12-07 09:09, Ard Biesheuvel wrote: > > > > (+ Marc) > > > > > > > > On Fri, 4 Dec 2020 at 12:14, Will Deacon wrote: > > > > > > > > > > On Fri, Dec 04, 2020 at 09:44:43AM +0800, Wei Li wrote: > > > > > > For the memory hole, sparse memory model that define SPARSEMEM_VMEMMAP > > > > > > do not free the reserved memory for the page map, decrease the section > > > > > > size can reduce the waste of reserved memory. > > > > > > > > > > > > Signed-off-by: Wei Li > > > > > > Signed-off-by: Baopeng Feng > > > > > > Signed-off-by: Xia Qing > > > > > > --- > > > > > > arch/arm64/include/asm/sparsemem.h | 2 +- > > > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/arch/arm64/include/asm/sparsemem.h b/arch/arm64/include/asm/sparsemem.h > > > > > > index 1f43fcc79738..8963bd3def28 100644 > > > > > > --- a/arch/arm64/include/asm/sparsemem.h > > > > > > +++ b/arch/arm64/include/asm/sparsemem.h > > > > > > @@ -7,7 +7,7 @@ > > > > > > > > > > > > #ifdef CONFIG_SPARSEMEM > > > > > > #define MAX_PHYSMEM_BITS CONFIG_ARM64_PA_BITS > > > > > > -#define SECTION_SIZE_BITS 30 > > > > > > +#define SECTION_SIZE_BITS 27 > > > > > > > > > > We chose '30' to avoid running out of bits in the page flags. What > > > > > changed? > > > > > > > > > > With this patch, I can trigger: > > > > > > > > > > ./include/linux/mmzone.h:1170:2: error: Allocator MAX_ORDER exceeds > > > > > SECTION_SIZE > > > > > #error Allocator MAX_ORDER exceeds SECTION_SIZE > > > > > > > > > > if I bump up NR_CPUS and NODES_SHIFT. > > > > > > > > > > > > > Does this mean we will run into problems with the GICv3 ITS LPI tables > > > > again if we are forced to reduce MAX_ORDER to fit inside > > > > SECTION_SIZE_BITS? > > > > > > Most probably. We are already massively constraint on platforms > > > such as TX1, and dividing the max allocatable range by 8 isn't > > > going to make it work any better... > > > > I don't think MAX_ORDER should shrink. Even if SECTION_SIZE_BITS is > > reduced it should accomodate the existing MAX_ORDER. > > > > My two pennies. > > > > But include/linux/mmzone.h:1170 has this: > > #if (MAX_ORDER - 1 + PAGE_SHIFT) > SECTION_SIZE_BITS > #error Allocator MAX_ORDER exceeds SECTION_SIZE > #endif > > and Will managed to trigger it after applying this patch. Right, because with 64K pages section size of 27 bits is not enough to accomodate MAX_ORDER (2^13 pages of 64K). Which means that definition of SECTION_SIZE_BITS should take MAX_ORDER into account either statically with #ifdef ARM64_4K_PAGES #define SECTION_SIZE_BITS #elif ARM64_16K_PAGES #define SECTION_SIZE_BITS #elif ARM64_64K_PAGES #define SECTION_SIZE_BITS #else #error "and what is the page size?" #endif or dynamically, like e.g. ia64 does: #ifdef CONFIG_FORCE_MAX_ZONEORDER #if ((CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT) > SECTION_SIZE_BITS) #undef SECTION_SIZE_BITS #define SECTION_SIZE_BITS (CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT) #endif -- Sincerely yours, Mike. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel