From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E50FC4361B for ; Mon, 7 Dec 2020 17:02:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 71E7A2388A for ; Mon, 7 Dec 2020 17:02:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727834AbgLGRCu (ORCPT ); Mon, 7 Dec 2020 12:02:50 -0500 Received: from mail-oi1-f194.google.com ([209.85.167.194]:38604 "EHLO mail-oi1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725863AbgLGRCt (ORCPT ); Mon, 7 Dec 2020 12:02:49 -0500 Received: by mail-oi1-f194.google.com with SMTP id o25so16137094oie.5; Mon, 07 Dec 2020 09:02:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=WhUIrDtbx95VVaLpPCnUUxF3hbxbXkZibqs0hBKgFBI=; b=eZevYyfy8KW8VoIUfstmAgw4/0QpfXVEz8digP+rTxhu6gmx+NqpQRl71KGdojmkFz GUhxvMwrpyV7ijMGI3qZjwtjaYXcwuoSzSh1aM5c9OXpRW2VSzoACy81EK/2bu+GqzVa Hf5JYzJ4iPRSocbWoKmsxkopvyQULuxJdaqqyAE9t5TNIODqsre0npJ33Athh89WSxkA ioYnTvqzySxrwgAYRDg2AkzAit+qVha+JDKQrhGJbroTsyOFsr8mkpZttI1aQa53q6Qu 8rNcLC30nuDo6Pja3PJQDwE3LslUu9c2HdYH8EPXOejxQBTVC2pS/6D7vJTtagUszp2q OAuw== X-Gm-Message-State: AOAM530Edd8xi2jbLJH5sY4G4VBpLqC2RDoaH+vLb+nlS2plHttn49HR 5YGZFYXQwn3SLDtCa1ZPkg== X-Google-Smtp-Source: ABdhPJwoMHlcpltnFQNrr+DMIIKPVZojsPWQGzZZCZM4H/mZ7zsCV2lm7aLdzZNGLecptEp8zSgcjQ== X-Received: by 2002:aca:f289:: with SMTP id q131mr12905613oih.159.1607360528354; Mon, 07 Dec 2020 09:02:08 -0800 (PST) Received: from xps15 (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id j126sm3045161oib.13.2020.12.07.09.02.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:02:07 -0800 (PST) Received: (nullmailer pid 437794 invoked by uid 1000); Mon, 07 Dec 2020 17:02:06 -0000 Date: Mon, 7 Dec 2020 11:02:06 -0600 From: Rob Herring To: Liu Ying Cc: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, daniel@ffwll.ch, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, laurentiu.palcu@oss.nxp.com Subject: Re: [PATCH v3 3/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding Message-ID: <20201207170206.GA434964@robh.at.kernel.org> References: <1607311260-13983-1-git-send-email-victor.liu@nxp.com> <1607311260-13983-4-git-send-email-victor.liu@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1607311260-13983-4-git-send-email-victor.liu@nxp.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Dec 07, 2020 at 11:20:57AM +0800, Liu Ying wrote: > This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel. > > Signed-off-by: Liu Ying > --- > Note that this depends on the 'two cell binding' clock patch set which has > already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h > won't be found. > > v2->v3: > * No change. > > v1->v2: > * Use new dt binding way to add clocks in the example. > > .../bindings/display/imx/fsl,imx8qxp-dprc.yaml | 87 ++++++++++++++++++++++ > 1 file changed, 87 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml > > diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml > new file mode 100644 > index 00000000..91e9472 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel > + > +maintainers: > + - Liu Ying > + > +description: | > + The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which > + fetches display data before the display pipeline needs the data to drive > + pixels in the active display region. This data is transformed, or resolved, > + from a variety of tiled buffer formats into linear format, if needed. > + The DPR works with a double bank memory structure. This memory structure is > + implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to > + as A and B. Each bank is either 4 or 8 lines high depending on the source > + frame buffer format. > + > +properties: > + compatible: > + oneOf: > + - const: fsl,imx8qxp-dpr-channel > + - const: fsl,imx8qm-dpr-channel enum instead of oneOf+const. With that, Reviewed-by: Rob Herring > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: apb clock > + - description: b clock > + - description: rtram clock > + > + clock-names: > + items: > + - const: apb > + - const: b > + - const: rtram > + > + fsl,sc-resource: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: The SCU resource ID associated with this DPRC instance. > + > + fsl,prgs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + List of phandle which points to Prefetch Resolve Gaskets(PRGs) > + associated with this DPRC instance. > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - fsl,sc-resource > + - fsl,prgs > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + dpr-channel@56100000 { > + compatible = "fsl,imx8qxp-dpr-channel"; > + reg = <0x56100000 0x10000>; > + interrupts = ; > + clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>, > + <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>, > + <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>; > + clock-names = "apb", "b", "rtram"; > + fsl,sc-resource = ; > + fsl,prgs = <&dc0_prg4>, <&dc0_prg5>; > + power-domains = <&pd IMX_SC_R_DC_0>; > + }; > -- > 2.7.4 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CF6DC4361B for ; Mon, 7 Dec 2020 17:03:37 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1677023888 for ; Mon, 7 Dec 2020 17:03:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1677023888 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=J8Eaa0o2ktG9FZe/a4qr7h7nhD/gY4HzmLXacw2qkF8=; b=E3GL8MkwLTPkaSPcaHP6040Ox YYzKBNLAN2+fDiI+VuvwZd3Etbq7hAcLk8YBA9dEyk6n2w15pW/r43eyZ31zmKvct05EPVkiNR/gv s7cQrOXBjetg5zdORuQG3neWZ8neYQecX5cusHW0e8sp84OKYE4JzEedPKbLq3Vf/nnagN+y/smOg Dgb5BN/0i62ga8kRabdDQXsUoQmQHiEp6dppeHzEBAnPQW2uhSiBIEg+Z3/nXiUCtkgwybyqwzN/M CpPKmJjV0TpNYnYp5oSv1MB2WBZK/NL7vQjIDBHUaZjtUExvYoqG809WZ2PCd2tZZZuUIPtZWcY9m 6/W9XH0nQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmJtt-0006si-FD; Mon, 07 Dec 2020 17:02:13 +0000 Received: from mail-oi1-f195.google.com ([209.85.167.195]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmJtp-0006rU-J9 for linux-arm-kernel@lists.infradead.org; Mon, 07 Dec 2020 17:02:11 +0000 Received: by mail-oi1-f195.google.com with SMTP id k2so16113051oic.13 for ; Mon, 07 Dec 2020 09:02:08 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=WhUIrDtbx95VVaLpPCnUUxF3hbxbXkZibqs0hBKgFBI=; b=esd9HhtUNKoNPYw2i6NbAcR47gFW7UDZVQF3M4ukeop9fcJR8mPmABQKa4L+SFX+ns FXB8cDg5eTv/onqmCe/zpHs0ZGkNJWWK1a1cxlmd3edzOPxrv3fOwXMu++qxpBg47y5W 60LH22lTteQychs+JVogV1eWGpruDi2hZLDsujkOXF3egfQf0nNfNymi66pvEUTL1XuK gZFEkSeMSne3jhUrlZTifyIqIEPfLxSjRgdF66kV/T2jKUJOxZzoXWKzAl7ib62LApxv tTMCPndSl7QYaMMDgfvVXiDPVEDg8hB33HEJqF4/oZLME4u9DJqjDryNjIaCSMbSFKfJ 4r1Q== X-Gm-Message-State: AOAM530BFHtOQVOLIQ81G1jYfNQ5rT8yzuIP85AOJ4e8md3D7/7341PS c1lIiKQ8rugc7hPjvXCgRg== X-Google-Smtp-Source: ABdhPJwoMHlcpltnFQNrr+DMIIKPVZojsPWQGzZZCZM4H/mZ7zsCV2lm7aLdzZNGLecptEp8zSgcjQ== X-Received: by 2002:aca:f289:: with SMTP id q131mr12905613oih.159.1607360528354; Mon, 07 Dec 2020 09:02:08 -0800 (PST) Received: from xps15 (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id j126sm3045161oib.13.2020.12.07.09.02.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:02:07 -0800 (PST) Received: (nullmailer pid 437794 invoked by uid 1000); Mon, 07 Dec 2020 17:02:06 -0000 Date: Mon, 7 Dec 2020 11:02:06 -0600 From: Rob Herring To: Liu Ying Subject: Re: [PATCH v3 3/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding Message-ID: <20201207170206.GA434964@robh.at.kernel.org> References: <1607311260-13983-1-git-send-email-victor.liu@nxp.com> <1607311260-13983-4-git-send-email-victor.liu@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1607311260-13983-4-git-send-email-victor.liu@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201207_120209_683082_8233F3E7 X-CRM114-Status: GOOD ( 23.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mripard@kernel.org, devicetree@vger.kernel.org, daniel@ffwll.ch, tzimmermann@suse.de, airlied@linux.ie, festevam@gmail.com, s.hauer@pengutronix.de, maarten.lankhorst@linux.intel.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-imx@nxp.com, p.zabel@pengutronix.de, laurentiu.palcu@oss.nxp.com, shawnguo@kernel.org, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Dec 07, 2020 at 11:20:57AM +0800, Liu Ying wrote: > This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel. > > Signed-off-by: Liu Ying > --- > Note that this depends on the 'two cell binding' clock patch set which has > already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h > won't be found. > > v2->v3: > * No change. > > v1->v2: > * Use new dt binding way to add clocks in the example. > > .../bindings/display/imx/fsl,imx8qxp-dprc.yaml | 87 ++++++++++++++++++++++ > 1 file changed, 87 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml > > diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml > new file mode 100644 > index 00000000..91e9472 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel > + > +maintainers: > + - Liu Ying > + > +description: | > + The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which > + fetches display data before the display pipeline needs the data to drive > + pixels in the active display region. This data is transformed, or resolved, > + from a variety of tiled buffer formats into linear format, if needed. > + The DPR works with a double bank memory structure. This memory structure is > + implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to > + as A and B. Each bank is either 4 or 8 lines high depending on the source > + frame buffer format. > + > +properties: > + compatible: > + oneOf: > + - const: fsl,imx8qxp-dpr-channel > + - const: fsl,imx8qm-dpr-channel enum instead of oneOf+const. With that, Reviewed-by: Rob Herring > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: apb clock > + - description: b clock > + - description: rtram clock > + > + clock-names: > + items: > + - const: apb > + - const: b > + - const: rtram > + > + fsl,sc-resource: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: The SCU resource ID associated with this DPRC instance. > + > + fsl,prgs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + List of phandle which points to Prefetch Resolve Gaskets(PRGs) > + associated with this DPRC instance. > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - fsl,sc-resource > + - fsl,prgs > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + dpr-channel@56100000 { > + compatible = "fsl,imx8qxp-dpr-channel"; > + reg = <0x56100000 0x10000>; > + interrupts = ; > + clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>, > + <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>, > + <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>; > + clock-names = "apb", "b", "rtram"; > + fsl,sc-resource = ; > + fsl,prgs = <&dc0_prg4>, <&dc0_prg5>; > + power-domains = <&pd IMX_SC_R_DC_0>; > + }; > -- > 2.7.4 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67E71C4361B for ; Mon, 7 Dec 2020 17:02:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D7F923884 for ; Mon, 7 Dec 2020 17:02:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1D7F923884 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 63FB689A67; Mon, 7 Dec 2020 17:02:10 +0000 (UTC) Received: from mail-oi1-f194.google.com (mail-oi1-f194.google.com [209.85.167.194]) by gabe.freedesktop.org (Postfix) with ESMTPS id 28C3789A67 for ; Mon, 7 Dec 2020 17:02:09 +0000 (UTC) Received: by mail-oi1-f194.google.com with SMTP id d27so8590341oic.0 for ; Mon, 07 Dec 2020 09:02:09 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=WhUIrDtbx95VVaLpPCnUUxF3hbxbXkZibqs0hBKgFBI=; b=C3owMo6CTjuWE6g/6P8/C1lWNJU3XCs+mOUy3awKuabWnlSHell4EE9++aYkS6AA9q Y5s3dvR+u838iFeimga/Lm8NKWzBMLhPkX3WzXmIr9UQI+8A4pRDIy4atLfv/XY6goC2 unEN34YWcgqI8clH1zcdCCQdA4eFTuuyDgC6SDWdGswGaauC6GdHWvLb6z5h5BImrQic mEkJua1pBtzWcgzxvPTOBr5aUxbfeA73nNzx2fEHwWQi379N5uU3LNHffdtH8b/jSlOz tF/YqYALHwh48TtLvfnTf0WUBJQfRYZvBqbXLccPaF+U4xpD8YOF/drdgBCOPfU8F3RV Oyzw== X-Gm-Message-State: AOAM532UHVc0Hir/+Xo0j0K2orcY4Vqv6Ju4V2xDRpbDvn2hs38Dzvui veCjJyq8vRAs9epGceJtuwndHaNDyw== X-Google-Smtp-Source: ABdhPJwoMHlcpltnFQNrr+DMIIKPVZojsPWQGzZZCZM4H/mZ7zsCV2lm7aLdzZNGLecptEp8zSgcjQ== X-Received: by 2002:aca:f289:: with SMTP id q131mr12905613oih.159.1607360528354; Mon, 07 Dec 2020 09:02:08 -0800 (PST) Received: from xps15 (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id j126sm3045161oib.13.2020.12.07.09.02.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:02:07 -0800 (PST) Received: (nullmailer pid 437794 invoked by uid 1000); Mon, 07 Dec 2020 17:02:06 -0000 Date: Mon, 7 Dec 2020 11:02:06 -0600 From: Rob Herring To: Liu Ying Subject: Re: [PATCH v3 3/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding Message-ID: <20201207170206.GA434964@robh.at.kernel.org> References: <1607311260-13983-1-git-send-email-victor.liu@nxp.com> <1607311260-13983-4-git-send-email-victor.liu@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1607311260-13983-4-git-send-email-victor.liu@nxp.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, tzimmermann@suse.de, airlied@linux.ie, s.hauer@pengutronix.de, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-imx@nxp.com, laurentiu.palcu@oss.nxp.com, shawnguo@kernel.org, kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, Dec 07, 2020 at 11:20:57AM +0800, Liu Ying wrote: > This patch adds bindings for i.MX8qxp/qm Display Prefetch Resolve Channel. > > Signed-off-by: Liu Ying > --- > Note that this depends on the 'two cell binding' clock patch set which has > already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h > won't be found. > > v2->v3: > * No change. > > v1->v2: > * Use new dt binding way to add clocks in the example. > > .../bindings/display/imx/fsl,imx8qxp-dprc.yaml | 87 ++++++++++++++++++++++ > 1 file changed, 87 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml > > diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml > new file mode 100644 > index 00000000..91e9472 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel > + > +maintainers: > + - Liu Ying > + > +description: | > + The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which > + fetches display data before the display pipeline needs the data to drive > + pixels in the active display region. This data is transformed, or resolved, > + from a variety of tiled buffer formats into linear format, if needed. > + The DPR works with a double bank memory structure. This memory structure is > + implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to > + as A and B. Each bank is either 4 or 8 lines high depending on the source > + frame buffer format. > + > +properties: > + compatible: > + oneOf: > + - const: fsl,imx8qxp-dpr-channel > + - const: fsl,imx8qm-dpr-channel enum instead of oneOf+const. With that, Reviewed-by: Rob Herring > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: apb clock > + - description: b clock > + - description: rtram clock > + > + clock-names: > + items: > + - const: apb > + - const: b > + - const: rtram > + > + fsl,sc-resource: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: The SCU resource ID associated with this DPRC instance. > + > + fsl,prgs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + List of phandle which points to Prefetch Resolve Gaskets(PRGs) > + associated with this DPRC instance. > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - fsl,sc-resource > + - fsl,prgs > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + dpr-channel@56100000 { > + compatible = "fsl,imx8qxp-dpr-channel"; > + reg = <0x56100000 0x10000>; > + interrupts = ; > + clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>, > + <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>, > + <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>; > + clock-names = "apb", "b", "rtram"; > + fsl,sc-resource = ; > + fsl,prgs = <&dc0_prg4>, <&dc0_prg5>; > + power-domains = <&pd IMX_SC_R_DC_0>; > + }; > -- > 2.7.4 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel