From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB15CC2BBCA for ; Mon, 7 Dec 2020 20:49:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7C7732389F for ; Mon, 7 Dec 2020 20:49:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727457AbgLGUsw (ORCPT ); Mon, 7 Dec 2020 15:48:52 -0500 Received: from mx01.bbu.dsd.mx.bitdefender.com ([91.199.104.161]:42578 "EHLO mx01.bbu.dsd.mx.bitdefender.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727524AbgLGUsv (ORCPT ); Mon, 7 Dec 2020 15:48:51 -0500 Received: from smtp.bitdefender.com (smtp01.buh.bitdefender.com [10.17.80.75]) by mx01.bbu.dsd.mx.bitdefender.com (Postfix) with ESMTPS id EF5BE305D481; Mon, 7 Dec 2020 22:46:24 +0200 (EET) Received: from localhost.localdomain (unknown [91.199.104.27]) by smtp.bitdefender.com (Postfix) with ESMTPSA id BC8B33072784; Mon, 7 Dec 2020 22:46:24 +0200 (EET) From: =?UTF-8?q?Adalbert=20Laz=C4=83r?= To: kvm@vger.kernel.org Cc: virtualization@lists.linux-foundation.org, Paolo Bonzini , =?UTF-8?q?Mihai=20Don=C8=9Bu?= , =?UTF-8?q?Nicu=C8=99or=20C=C3=AE=C8=9Bu?= , =?UTF-8?q?Adalbert=20Laz=C4=83r?= Subject: [PATCH v11 72/81] KVM: introspection: add KVMI_VCPU_CONTROL_MSR and KVMI_VCPU_EVENT_MSR Date: Mon, 7 Dec 2020 22:46:13 +0200 Message-Id: <20201207204622.15258-73-alazar@bitdefender.com> In-Reply-To: <20201207204622.15258-1-alazar@bitdefender.com> References: <20201207204622.15258-1-alazar@bitdefender.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Mihai Donțu This command is used to enable/disable introspection for a specific MSR. The KVMI_VCPU_EVENT_MSR event is sent when the tracked MSR is going to be changed. The introspection tool can respond by allowing the guest to continue with normal execution or by discarding the change. This is meant to prevent malicious changes to MSRs such as MSR_IA32_SYSENTER_EIP. Signed-off-by: Mihai Donțu Co-developed-by: Nicușor Cîțu Signed-off-by: Nicușor Cîțu Co-developed-by: Adalbert Lazăr Signed-off-by: Adalbert Lazăr --- Documentation/virt/kvm/kvmi.rst | 79 +++++++++++ arch/x86/include/asm/kvmi_host.h | 12 ++ arch/x86/include/uapi/asm/kvmi.h | 18 +++ arch/x86/kvm/kvmi.c | 125 ++++++++++++++++++ arch/x86/kvm/kvmi.h | 3 + arch/x86/kvm/kvmi_msg.c | 52 ++++++++ arch/x86/kvm/x86.c | 3 + include/uapi/linux/kvmi.h | 2 + .../testing/selftests/kvm/x86_64/kvmi_test.c | 111 ++++++++++++++++ 9 files changed, 405 insertions(+) diff --git a/Documentation/virt/kvm/kvmi.rst b/Documentation/virt/kvm/kvmi.rst index 2bfb2bf0e778..7220f27ea5c3 100644 --- a/Documentation/virt/kvm/kvmi.rst +++ b/Documentation/virt/kvm/kvmi.rst @@ -542,6 +542,7 @@ the following events:: KVMI_VCPU_EVENT_CR KVMI_VCPU_EVENT_DESCRIPTOR KVMI_VCPU_EVENT_HYPERCALL + KVMI_VCPU_EVENT_MSR KVMI_VCPU_EVENT_XSETBV When an event is enabled, the introspection tool is notified and @@ -922,6 +923,48 @@ Returns the guest memory type for a specific guest physical address (``gpa``). * -KVM_EINVAL - the padding is not zero * -KVM_EAGAIN - the selected vCPU can't be introspected yet +22. KVMI_VCPU_CONTROL_MSR +------------------------- + +:Architectures: x86 +:Versions: >= 1 +:Parameters: + +:: + + struct kvmi_vcpu_hdr; + struct kvmi_vcpu_control_msr { + __u8 enable; + __u8 padding1; + __u16 padding2; + __u32 msr; + }; + +:Returns: + +:: + + struct kvmi_error_code + +Enables/disables introspection for a specific MSR and must be used +in addition to *KVMI_VCPU_CONTROL_EVENTS* with the *KVMI_VCPU_EVENT_MSR* +ID set. + +Currently, only MSRs within the following two ranges are supported. Trying +to control events for any other register will fail with -KVM_EINVAL:: + + 0 ... 0x00001fff + 0xc0000000 ... 0xc0001fff + +:Errors: + +* -KVM_EINVAL - the selected vCPU is invalid +* -KVM_EINVAL - the specified MSR is invalid +* -KVM_EINVAL - the padding is not zero +* -KVM_EAGAIN - the selected vCPU can't be introspected yet +* -KVM_EPERM - the interception of the selected MSR is disallowed + from userspace (KVM_X86_SET_MSR_FILTER) + Events ====== @@ -1260,3 +1303,39 @@ introspection tool. KVMI_DESC_TR ``write`` is 1 if the descriptor was written, 0 otherwise. + +9. KVMI_VCPU_EVENT_MSR +---------------------- + +:Architectures: x86 +:Versions: >= 1 +:Actions: CONTINUE, CRASH +:Parameters: + +:: + + struct kvmi_vcpu_event; + struct kvmi_vcpu_event_msr { + __u32 msr; + __u32 padding; + __u64 old_value; + __u64 new_value; + }; + +:Returns: + +:: + + struct kvmi_vcpu_hdr; + struct kvmi_vcpu_event_reply; + struct kvmi_vcpu_event_msr_reply { + __u64 new_val; + }; + +This event is sent when a model specific register is going to be changed +and the introspection has been enabled for this event and for this specific +register (see **KVMI_VCPU_CONTROL_EVENTS**). + +``kvmi_vcpu_event`` (with the vCPU state), the MSR number (``msr``), +the old value (``old_value``) and the new value (``new_value``) are sent +to the introspection tool. The *CONTINUE* action will set the ``new_val``. diff --git a/arch/x86/include/asm/kvmi_host.h b/arch/x86/include/asm/kvmi_host.h index a872277eba67..5a4fc5b80907 100644 --- a/arch/x86/include/asm/kvmi_host.h +++ b/arch/x86/include/asm/kvmi_host.h @@ -4,7 +4,10 @@ #include +struct msr_data; + #define KVMI_NUM_CR 5 +#define KVMI_NUM_MSR 0x2000 struct kvmi_monitor_interception { bool kvmi_intercepted; @@ -18,6 +21,12 @@ struct kvmi_interception { struct kvmi_monitor_interception breakpoint; struct kvmi_monitor_interception cr3w; struct kvmi_monitor_interception descriptor; + struct { + struct { + DECLARE_BITMAP(low, KVMI_NUM_MSR); + DECLARE_BITMAP(high, KVMI_NUM_MSR); + } kvmi_mask; + } msrw; }; struct kvm_vcpu_arch_introspection { @@ -51,6 +60,7 @@ void kvmi_xsetbv_event(struct kvm_vcpu *vcpu, u8 xcr, u64 old_value, u64 new_value); bool kvmi_monitor_desc_intercept(struct kvm_vcpu *vcpu, bool enable); bool kvmi_descriptor_event(struct kvm_vcpu *vcpu, u8 descriptor, bool write); +bool kvmi_msr_event(struct kvm_vcpu *vcpu, struct msr_data *msr); #else /* CONFIG_KVM_INTROSPECTION */ @@ -70,6 +80,8 @@ static inline bool kvmi_monitor_desc_intercept(struct kvm_vcpu *vcpu, bool enable) { return false; } static inline bool kvmi_descriptor_event(struct kvm_vcpu *vcpu, u8 descriptor, bool write) { return true; } +static inline bool kvmi_msr_event(struct kvm_vcpu *vcpu, struct msr_data *msr) + { return true; } #endif /* CONFIG_KVM_INTROSPECTION */ diff --git a/arch/x86/include/uapi/asm/kvmi.h b/arch/x86/include/uapi/asm/kvmi.h index 9c608ef5daa3..6ef144ddb4bb 100644 --- a/arch/x86/include/uapi/asm/kvmi.h +++ b/arch/x86/include/uapi/asm/kvmi.h @@ -141,4 +141,22 @@ struct kvmi_vcpu_event_descriptor { __u8 padding[6]; }; +struct kvmi_vcpu_control_msr { + __u8 enable; + __u8 padding1; + __u16 padding2; + __u32 msr; +}; + +struct kvmi_vcpu_event_msr { + __u32 msr; + __u32 padding; + __u64 old_value; + __u64 new_value; +}; + +struct kvmi_vcpu_event_msr_reply { + __u64 new_val; +}; + #endif /* _UAPI_ASM_X86_KVMI_H */ diff --git a/arch/x86/kvm/kvmi.c b/arch/x86/kvm/kvmi.c index 4106ae63a115..ce29e01ba7a6 100644 --- a/arch/x86/kvm/kvmi.c +++ b/arch/x86/kvm/kvmi.c @@ -16,6 +16,7 @@ void kvmi_arch_init_vcpu_events_mask(unsigned long *supported) set_bit(KVMI_VCPU_EVENT_CR, supported); set_bit(KVMI_VCPU_EVENT_HYPERCALL, supported); set_bit(KVMI_VCPU_EVENT_DESCRIPTOR, supported); + set_bit(KVMI_VCPU_EVENT_MSR, supported); set_bit(KVMI_VCPU_EVENT_TRAP, supported); set_bit(KVMI_VCPU_EVENT_XSETBV, supported); } @@ -344,6 +345,77 @@ static void kvmi_arch_disable_desc_intercept(struct kvm_vcpu *vcpu) vcpu->arch.kvmi->descriptor.kvm_intercepted = false; } +static unsigned long *msr_mask(struct kvm_vcpu *vcpu, unsigned int *msr) +{ + switch (*msr) { + case 0 ... 0x1fff: + return vcpu->arch.kvmi->msrw.kvmi_mask.low; + case 0xc0000000 ... 0xc0001fff: + *msr &= 0x1fff; + return vcpu->arch.kvmi->msrw.kvmi_mask.high; + } + + return NULL; +} + +static bool test_msr_mask(struct kvm_vcpu *vcpu, unsigned int msr) +{ + unsigned long *mask = msr_mask(vcpu, &msr); + + if (!mask) + return false; + + return !!test_bit(msr, mask); +} + +static bool msr_control(struct kvm_vcpu *vcpu, unsigned int msr, bool enable) +{ + unsigned long *mask = msr_mask(vcpu, &msr); + + if (!mask) + return false; + + if (enable) + set_bit(msr, mask); + else + clear_bit(msr, mask); + + return true; +} + +static unsigned int msr_mask_to_base(struct kvm_vcpu *vcpu, unsigned long *mask) +{ + if (mask == vcpu->arch.kvmi->msrw.kvmi_mask.high) + return 0xc0000000; + + return 0; +} + +void kvmi_control_msrw_intercept(struct kvm_vcpu *vcpu, u32 msr, bool enable) +{ + kvm_x86_ops.control_msr_intercept(vcpu, msr, MSR_TYPE_W, enable); + msr_control(vcpu, msr, enable); +} + +static void kvmi_arch_disable_msr_intercept(struct kvm_vcpu *vcpu, + unsigned long *mask) +{ + unsigned int msr_base = msr_mask_to_base(vcpu, mask); + int offset = -1; + + for (;;) { + offset = find_next_bit(mask, KVMI_NUM_MSR, offset + 1); + + if (offset >= KVMI_NUM_MSR) + break; + + kvm_x86_ops.control_msr_intercept(vcpu, msr_base + offset, + MSR_TYPE_W, false); + } + + bitmap_zero(mask, KVMI_NUM_MSR); +} + int kvmi_arch_cmd_control_intercept(struct kvm_vcpu *vcpu, unsigned int event_id, bool enable) { @@ -385,9 +457,13 @@ void kvmi_arch_breakpoint_event(struct kvm_vcpu *vcpu, u64 gva, u8 insn_len) static void kvmi_arch_restore_interception(struct kvm_vcpu *vcpu) { + struct kvmi_interception *arch_vcpui = vcpu->arch.kvmi; + kvmi_arch_disable_bp_intercept(vcpu); kvmi_arch_disable_cr3w_intercept(vcpu); kvmi_arch_disable_desc_intercept(vcpu); + kvmi_arch_disable_msr_intercept(vcpu, arch_vcpui->msrw.kvmi_mask.low); + kvmi_arch_disable_msr_intercept(vcpu, arch_vcpui->msrw.kvmi_mask.high); } bool kvmi_arch_clean_up_interception(struct kvm_vcpu *vcpu) @@ -700,3 +776,52 @@ bool kvmi_descriptor_event(struct kvm_vcpu *vcpu, u8 descriptor, bool write) return ret; } EXPORT_SYMBOL(kvmi_descriptor_event); + +static bool __kvmi_msr_event(struct kvm_vcpu *vcpu, struct msr_data *msr) +{ + struct msr_data old_msr = { + .host_initiated = true, + .index = msr->index, + }; + u64 reply_value; + u32 action; + bool ret; + + if (!test_msr_mask(vcpu, msr->index)) + return true; + if (kvm_x86_ops.get_msr(vcpu, &old_msr)) + return true; + if (old_msr.data == msr->data) + return true; + + action = kvmi_msg_send_vcpu_msr(vcpu, msr->index, old_msr.data, + msr->data, &reply_value); + switch (action) { + case KVMI_EVENT_ACTION_CONTINUE: + msr->data = reply_value; + ret = true; + break; + default: + kvmi_handle_common_event_actions(vcpu, action); + ret = false; + } + + return ret; +} + +bool kvmi_msr_event(struct kvm_vcpu *vcpu, struct msr_data *msr) +{ + struct kvm_introspection *kvmi; + bool ret = true; + + kvmi = kvmi_get(vcpu->kvm); + if (!kvmi) + return true; + + if (is_vcpu_event_enabled(vcpu, KVMI_VCPU_EVENT_MSR)) + ret = __kvmi_msr_event(vcpu, msr); + + kvmi_put(vcpu->kvm); + + return ret; +} diff --git a/arch/x86/kvm/kvmi.h b/arch/x86/kvm/kvmi.h index 92422e2e57cf..6483edbb80c5 100644 --- a/arch/x86/kvm/kvmi.h +++ b/arch/x86/kvm/kvmi.h @@ -17,5 +17,8 @@ u32 kvmi_msg_send_vcpu_trap(struct kvm_vcpu *vcpu); u32 kvmi_msg_send_vcpu_xsetbv(struct kvm_vcpu *vcpu, u8 xcr, u64 old_value, u64 new_value); u32 kvmi_msg_send_vcpu_descriptor(struct kvm_vcpu *vcpu, u8 desc, bool write); +void kvmi_control_msrw_intercept(struct kvm_vcpu *vcpu, u32 msr, bool enable); +u32 kvmi_msg_send_vcpu_msr(struct kvm_vcpu *vcpu, u32 msr, u64 old_value, + u64 new_value, u64 *ret_value); #endif diff --git a/arch/x86/kvm/kvmi_msg.c b/arch/x86/kvm/kvmi_msg.c index f0b4016820ce..6d45b1c49184 100644 --- a/arch/x86/kvm/kvmi_msg.c +++ b/arch/x86/kvm/kvmi_msg.c @@ -248,8 +248,36 @@ static int handle_vcpu_get_mtrr_type(const struct kvmi_vcpu_msg_job *job, return kvmi_msg_vcpu_reply(job, msg, 0, &rpl, sizeof(rpl)); } +static bool is_valid_msr(unsigned int msr) +{ + return msr <= 0x1fff || (msr >= 0xc0000000 && msr <= 0xc0001fff); +} + +static int handle_vcpu_control_msr(const struct kvmi_vcpu_msg_job *job, + const struct kvmi_msg_hdr *msg, + const void *_req) +{ + const struct kvmi_vcpu_control_msr *req = _req; + int ec = 0; + + if (req->padding1 || req->padding2 || req->enable > 1) + ec = -KVM_EINVAL; + else if (!is_valid_msr(req->msr)) + ec = -KVM_EINVAL; + else if (req->enable && + !kvm_msr_allowed(job->vcpu, req->msr, + KVM_MSR_FILTER_WRITE)) + ec = -KVM_EPERM; + else + kvmi_control_msrw_intercept(job->vcpu, req->msr, + req->enable == 1); + + return kvmi_msg_vcpu_reply(job, msg, ec, NULL, 0); +} + static kvmi_vcpu_msg_job_fct const msg_vcpu[] = { [KVMI_VCPU_CONTROL_CR] = handle_vcpu_control_cr, + [KVMI_VCPU_CONTROL_MSR] = handle_vcpu_control_msr, [KVMI_VCPU_GET_CPUID] = handle_vcpu_get_cpuid, [KVMI_VCPU_GET_INFO] = handle_vcpu_get_info, [KVMI_VCPU_GET_MTRR_TYPE] = handle_vcpu_get_mtrr_type, @@ -349,3 +377,27 @@ u32 kvmi_msg_send_vcpu_descriptor(struct kvm_vcpu *vcpu, u8 desc, bool write) return action; } + +u32 kvmi_msg_send_vcpu_msr(struct kvm_vcpu *vcpu, u32 msr, u64 old_value, + u64 new_value, u64 *ret_value) +{ + struct kvmi_vcpu_event_msr e; + struct kvmi_vcpu_event_msr_reply r; + int err, action; + + memset(&e, 0, sizeof(e)); + e.msr = msr; + e.old_value = old_value; + e.new_value = new_value; + + err = kvmi_send_vcpu_event(vcpu, KVMI_VCPU_EVENT_MSR, &e, sizeof(e), + &r, sizeof(r), &action); + if (err) { + action = KVMI_EVENT_ACTION_CONTINUE; + *ret_value = new_value; + } else { + *ret_value = r.new_val; + } + + return action; +} diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 7a1cd14b0a87..381e3dfba535 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1585,6 +1585,9 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, msr.index = index; msr.host_initiated = host_initiated; + if (!host_initiated && !kvmi_msr_event(vcpu, &msr)) + return 1; + return kvm_x86_ops.set_msr(vcpu, &msr); } diff --git a/include/uapi/linux/kvmi.h b/include/uapi/linux/kvmi.h index 09f78c0efc4f..c8e7f4516379 100644 --- a/include/uapi/linux/kvmi.h +++ b/include/uapi/linux/kvmi.h @@ -48,6 +48,7 @@ enum { KVMI_VCPU_GET_XSAVE = KVMI_VCPU_MESSAGE_ID(9), KVMI_VCPU_SET_XSAVE = KVMI_VCPU_MESSAGE_ID(10), KVMI_VCPU_GET_MTRR_TYPE = KVMI_VCPU_MESSAGE_ID(11), + KVMI_VCPU_CONTROL_MSR = KVMI_VCPU_MESSAGE_ID(12), KVMI_NEXT_VCPU_MESSAGE }; @@ -69,6 +70,7 @@ enum { KVMI_VCPU_EVENT_TRAP = KVMI_VCPU_EVENT_ID(4), KVMI_VCPU_EVENT_XSETBV = KVMI_VCPU_EVENT_ID(5), KVMI_VCPU_EVENT_DESCRIPTOR = KVMI_VCPU_EVENT_ID(6), + KVMI_VCPU_EVENT_MSR = KVMI_VCPU_EVENT_ID(7), KVMI_NEXT_VCPU_EVENT }; diff --git a/tools/testing/selftests/kvm/x86_64/kvmi_test.c b/tools/testing/selftests/kvm/x86_64/kvmi_test.c index d26df3a9ffff..2e07b22bc8c0 100644 --- a/tools/testing/selftests/kvm/x86_64/kvmi_test.c +++ b/tools/testing/selftests/kvm/x86_64/kvmi_test.c @@ -60,6 +60,7 @@ enum { GUEST_TEST_CR, GUEST_TEST_DESCRIPTOR, GUEST_TEST_HYPERCALL, + GUEST_TEST_MSR, GUEST_TEST_XSETBV, }; @@ -104,6 +105,15 @@ static void guest_hypercall_test(void) asm volatile(".byte 0x0f,0x01,0xc1"); } +static void guest_msr_test(void) +{ + uint64_t msr; + + msr = rdmsr(MSR_MISC_FEATURES_ENABLES); + msr |= 1; /* MSR_MISC_FEATURES_ENABLES_CPUID_FAULT */ + wrmsr(MSR_MISC_FEATURES_ENABLES, msr); +} + /* from fpu/internal.h */ static u64 xgetbv(u32 index) { @@ -161,6 +171,9 @@ static void guest_code(void) case GUEST_TEST_HYPERCALL: guest_hypercall_test(); break; + case GUEST_TEST_MSR: + guest_msr_test(); + break; case GUEST_TEST_XSETBV: guest_xsetbv_test(); break; @@ -1579,6 +1592,103 @@ static void test_event_descriptor(struct kvm_vm *vm) disable_vcpu_event(vm, event_id); } +static void cmd_control_msr(struct kvm_vm *vm, __u32 msr, __u8 enable, + int expected_err) +{ + struct { + struct kvmi_msg_hdr hdr; + struct kvmi_vcpu_hdr vcpu_hdr; + struct kvmi_vcpu_control_msr cmd; + } req = {}; + + req.cmd.msr = msr; + req.cmd.enable = enable; + + test_vcpu0_command(vm, KVMI_VCPU_CONTROL_MSR, &req.hdr, sizeof(req), + NULL, 0, expected_err); +} + +static void enable_msr_events(struct kvm_vm *vm, __u32 msr) +{ + enable_vcpu_event(vm, KVMI_VCPU_EVENT_MSR); + cmd_control_msr(vm, msr, 1, 0); +} + +static void disable_msr_events(struct kvm_vm *vm, __u32 msr) +{ + cmd_control_msr(vm, msr, 0, 0); + disable_vcpu_event(vm, KVMI_VCPU_EVENT_MSR); +} + +static void handle_msr_event(struct kvm_vm *vm, __u16 event_id, __u32 msr, + __u64 *old_value) +{ + struct kvmi_msg_hdr hdr; + struct { + struct vcpu_event vcpu_ev; + struct kvmi_vcpu_event_msr msr; + } ev; + struct { + struct vcpu_reply common; + struct kvmi_vcpu_event_msr_reply msr; + } rpl = {}; + + receive_vcpu_event(&hdr, &ev.vcpu_ev, sizeof(ev), event_id); + + pr_debug("MSR 0x%x, old 0x%llx, new 0x%llx\n", + ev.msr.msr, ev.msr.old_value, ev.msr.new_value); + + TEST_ASSERT(ev.msr.msr == msr, + "Unexpected MSR event, received MSR 0x%x, expected MSR 0x%x", + ev.msr.msr, msr); + + *old_value = rpl.msr.new_val = ev.msr.old_value; + + reply_to_event(&hdr, &ev.vcpu_ev, KVMI_EVENT_ACTION_CONTINUE, + &rpl.common, sizeof(rpl)); +} + +static void test_invalid_control_msr(struct kvm_vm *vm, __u32 msr) +{ + __u8 enable = 1, enable_inval = 2; + int expected_err = -KVM_EINVAL; + __u32 msr_inval = -1; + + cmd_control_msr(vm, msr, enable_inval, expected_err); + cmd_control_msr(vm, msr_inval, enable, expected_err); +} + +static void test_cmd_vcpu_control_msr(struct kvm_vm *vm) +{ + struct vcpu_worker_data data = { + .vm = vm, + .vcpu_id = VCPU_ID, + .test_id = GUEST_TEST_MSR, + }; + __u16 event_id = KVMI_VCPU_EVENT_MSR; + __u32 msr = MSR_MISC_FEATURES_ENABLES; + pthread_t vcpu_thread; + uint64_t msr_data; + __u64 old_value; + + enable_msr_events(vm, msr); + + vcpu_thread = start_vcpu_worker(&data); + + handle_msr_event(vm, event_id, msr, &old_value); + + wait_vcpu_worker(vcpu_thread); + + disable_msr_events(vm, msr); + + msr_data = vcpu_get_msr(vm, VCPU_ID, msr); + TEST_ASSERT(msr_data == old_value, + "Failed to block MSR 0x%x update, value 0x%lx, expected 0x%llx", + msr, msr_data, old_value); + + test_invalid_control_msr(vm, msr); +} + static void test_introspection(struct kvm_vm *vm) { srandom(time(0)); @@ -1610,6 +1720,7 @@ static void test_introspection(struct kvm_vm *vm) test_cmd_vcpu_xsave(vm); test_cmd_vcpu_get_mtrr_type(vm); test_event_descriptor(vm); + test_cmd_vcpu_control_msr(vm); unhook_introspection(vm); } From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31576C4361B for ; Mon, 7 Dec 2020 20:56:59 +0000 (UTC) Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CDBF7238E3 for ; Mon, 7 Dec 2020 20:56:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CDBF7238E3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=bitdefender.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=virtualization-bounces@lists.linux-foundation.org Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id B35BB8719F; Mon, 7 Dec 2020 20:56:58 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pkjY0wAF3Icd; Mon, 7 Dec 2020 20:56:55 +0000 (UTC) Received: from lists.linuxfoundation.org (lf-lists.osuosl.org [140.211.9.56]) by fraxinus.osuosl.org (Postfix) with ESMTP id EB1B8870BE; Mon, 7 Dec 2020 20:56:55 +0000 (UTC) Received: from lf-lists.osuosl.org (localhost [127.0.0.1]) by lists.linuxfoundation.org (Postfix) with ESMTP id C5E98C0FA7; Mon, 7 Dec 2020 20:56:55 +0000 (UTC) Received: from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133]) by lists.linuxfoundation.org (Postfix) with ESMTP id 220C7C013B for ; Mon, 7 Dec 2020 20:56:54 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by hemlock.osuosl.org (Postfix) with ESMTP id 106B987245 for ; Mon, 7 Dec 2020 20:56:54 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from hemlock.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iIkkcTq5JYHx for ; Mon, 7 Dec 2020 20:56:52 +0000 (UTC) X-Greylist: from auto-whitelisted by SQLgrey-1.7.6 Received: from mx01.bbu.dsd.mx.bitdefender.com (mx01.bbu.dsd.mx.bitdefender.com [91.199.104.161]) by hemlock.osuosl.org (Postfix) with ESMTPS id D2FA18722C for ; Mon, 7 Dec 2020 20:56:51 +0000 (UTC) Received: from smtp.bitdefender.com (smtp01.buh.bitdefender.com [10.17.80.75]) by mx01.bbu.dsd.mx.bitdefender.com (Postfix) with ESMTPS id EF5BE305D481; Mon, 7 Dec 2020 22:46:24 +0200 (EET) Received: from localhost.localdomain (unknown [91.199.104.27]) by smtp.bitdefender.com (Postfix) with ESMTPSA id BC8B33072784; Mon, 7 Dec 2020 22:46:24 +0200 (EET) From: =?UTF-8?q?Adalbert=20Laz=C4=83r?= To: kvm@vger.kernel.org Subject: [PATCH v11 72/81] KVM: introspection: add KVMI_VCPU_CONTROL_MSR and KVMI_VCPU_EVENT_MSR Date: Mon, 7 Dec 2020 22:46:13 +0200 Message-Id: <20201207204622.15258-73-alazar@bitdefender.com> In-Reply-To: <20201207204622.15258-1-alazar@bitdefender.com> References: <20201207204622.15258-1-alazar@bitdefender.com> MIME-Version: 1.0 Cc: =?UTF-8?q?Adalbert=20Laz=C4=83r?= , Paolo Bonzini , =?UTF-8?q?Mihai=20Don=C8=9Bu?= , =?UTF-8?q?Nicu=C8=99or=20C=C3=AE=C8=9Bu?= , virtualization@lists.linux-foundation.org X-BeenThere: virtualization@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux virtualization List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: virtualization-bounces@lists.linux-foundation.org Sender: "Virtualization" RnJvbTogTWloYWkgRG9uyJt1IDxtZG9udHVAYml0ZGVmZW5kZXIuY29tPgoKVGhpcyBjb21tYW5k IGlzIHVzZWQgdG8gZW5hYmxlL2Rpc2FibGUgaW50cm9zcGVjdGlvbiBmb3IgYSBzcGVjaWZpYwpN U1IuIFRoZSBLVk1JX1ZDUFVfRVZFTlRfTVNSIGV2ZW50IGlzIHNlbnQgd2hlbiB0aGUgdHJhY2tl ZCBNU1IgaXMgZ29pbmcKdG8gYmUgY2hhbmdlZC4gVGhlIGludHJvc3BlY3Rpb24gdG9vbCBjYW4g cmVzcG9uZCBieSBhbGxvd2luZyB0aGUgZ3Vlc3QKdG8gY29udGludWUgd2l0aCBub3JtYWwgZXhl Y3V0aW9uIG9yIGJ5IGRpc2NhcmRpbmcgdGhlIGNoYW5nZS4KClRoaXMgaXMgbWVhbnQgdG8gcHJl dmVudCBtYWxpY2lvdXMgY2hhbmdlcyB0byBNU1JzCnN1Y2ggYXMgTVNSX0lBMzJfU1lTRU5URVJf RUlQLgoKU2lnbmVkLW9mZi1ieTogTWloYWkgRG9uyJt1IDxtZG9udHVAYml0ZGVmZW5kZXIuY29t PgpDby1kZXZlbG9wZWQtYnk6IE5pY3XImW9yIEPDrsibdSA8bmljdS5jaXR1QGljbG91ZC5jb20+ ClNpZ25lZC1vZmYtYnk6IE5pY3XImW9yIEPDrsibdSA8bmljdS5jaXR1QGljbG91ZC5jb20+CkNv LWRldmVsb3BlZC1ieTogQWRhbGJlcnQgTGF6xINyIDxhbGF6YXJAYml0ZGVmZW5kZXIuY29tPgpT aWduZWQtb2ZmLWJ5OiBBZGFsYmVydCBMYXrEg3IgPGFsYXphckBiaXRkZWZlbmRlci5jb20+Ci0t LQogRG9jdW1lbnRhdGlvbi92aXJ0L2t2bS9rdm1pLnJzdCAgICAgICAgICAgICAgIHwgIDc5ICsr KysrKysrKysrCiBhcmNoL3g4Ni9pbmNsdWRlL2FzbS9rdm1pX2hvc3QuaCAgICAgICAgICAgICAg fCAgMTIgKysKIGFyY2gveDg2L2luY2x1ZGUvdWFwaS9hc20va3ZtaS5oICAgICAgICAgICAgICB8 ICAxOCArKysKIGFyY2gveDg2L2t2bS9rdm1pLmMgICAgICAgICAgICAgICAgICAgICAgICAgICB8 IDEyNSArKysrKysrKysrKysrKysrKysKIGFyY2gveDg2L2t2bS9rdm1pLmggICAgICAgICAgICAg ICAgICAgICAgICAgICB8ICAgMyArCiBhcmNoL3g4Ni9rdm0va3ZtaV9tc2cuYyAgICAgICAgICAg ICAgICAgICAgICAgfCAgNTIgKysrKysrKysKIGFyY2gveDg2L2t2bS94ODYuYyAgICAgICAgICAg ICAgICAgICAgICAgICAgICB8ICAgMyArCiBpbmNsdWRlL3VhcGkvbGludXgva3ZtaS5oICAgICAg ICAgICAgICAgICAgICAgfCAgIDIgKwogLi4uL3Rlc3Rpbmcvc2VsZnRlc3RzL2t2bS94ODZfNjQv a3ZtaV90ZXN0LmMgIHwgMTExICsrKysrKysrKysrKysrKysKIDkgZmlsZXMgY2hhbmdlZCwgNDA1 IGluc2VydGlvbnMoKykKCmRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL3ZpcnQva3ZtL2t2bWku cnN0IGIvRG9jdW1lbnRhdGlvbi92aXJ0L2t2bS9rdm1pLnJzdAppbmRleCAyYmZiMmJmMGU3Nzgu LjcyMjBmMjdlYTVjMyAxMDA2NDQKLS0tIGEvRG9jdW1lbnRhdGlvbi92aXJ0L2t2bS9rdm1pLnJz dAorKysgYi9Eb2N1bWVudGF0aW9uL3ZpcnQva3ZtL2t2bWkucnN0CkBAIC01NDIsNiArNTQyLDcg QEAgdGhlIGZvbGxvd2luZyBldmVudHM6OgogCUtWTUlfVkNQVV9FVkVOVF9DUgogCUtWTUlfVkNQ VV9FVkVOVF9ERVNDUklQVE9SCiAJS1ZNSV9WQ1BVX0VWRU5UX0hZUEVSQ0FMTAorCUtWTUlfVkNQ VV9FVkVOVF9NU1IKIAlLVk1JX1ZDUFVfRVZFTlRfWFNFVEJWCiAKIFdoZW4gYW4gZXZlbnQgaXMg ZW5hYmxlZCwgdGhlIGludHJvc3BlY3Rpb24gdG9vbCBpcyBub3RpZmllZCBhbmQKQEAgLTkyMiw2 ICs5MjMsNDggQEAgUmV0dXJucyB0aGUgZ3Vlc3QgbWVtb3J5IHR5cGUgZm9yIGEgc3BlY2lmaWMg Z3Vlc3QgcGh5c2ljYWwgYWRkcmVzcyAoYGBncGFgYCkuCiAqIC1LVk1fRUlOVkFMIC0gdGhlIHBh ZGRpbmcgaXMgbm90IHplcm8KICogLUtWTV9FQUdBSU4gLSB0aGUgc2VsZWN0ZWQgdkNQVSBjYW4n dCBiZSBpbnRyb3NwZWN0ZWQgeWV0CiAKKzIyLiBLVk1JX1ZDUFVfQ09OVFJPTF9NU1IKKy0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0KKworOkFyY2hpdGVjdHVyZXM6IHg4NgorOlZlcnNpb25zOiA+ PSAxCis6UGFyYW1ldGVyczoKKworOjoKKworCXN0cnVjdCBrdm1pX3ZjcHVfaGRyOworCXN0cnVj dCBrdm1pX3ZjcHVfY29udHJvbF9tc3IgeworCQlfX3U4IGVuYWJsZTsKKwkJX191OCBwYWRkaW5n MTsKKwkJX191MTYgcGFkZGluZzI7CisJCV9fdTMyIG1zcjsKKwl9OworCis6UmV0dXJuczoKKwor OjoKKworCXN0cnVjdCBrdm1pX2Vycm9yX2NvZGUKKworRW5hYmxlcy9kaXNhYmxlcyBpbnRyb3Nw ZWN0aW9uIGZvciBhIHNwZWNpZmljIE1TUiBhbmQgbXVzdCBiZSB1c2VkCitpbiBhZGRpdGlvbiB0 byAqS1ZNSV9WQ1BVX0NPTlRST0xfRVZFTlRTKiB3aXRoIHRoZSAqS1ZNSV9WQ1BVX0VWRU5UX01T UioKK0lEIHNldC4KKworQ3VycmVudGx5LCBvbmx5IE1TUnMgd2l0aGluIHRoZSBmb2xsb3dpbmcg dHdvIHJhbmdlcyBhcmUgc3VwcG9ydGVkLiBUcnlpbmcKK3RvIGNvbnRyb2wgZXZlbnRzIGZvciBh bnkgb3RoZXIgcmVnaXN0ZXIgd2lsbCBmYWlsIHdpdGggLUtWTV9FSU5WQUw6OgorCisJMCAgICAg ICAgICAuLi4gMHgwMDAwMWZmZgorCTB4YzAwMDAwMDAgLi4uIDB4YzAwMDFmZmYKKworOkVycm9y czoKKworKiAtS1ZNX0VJTlZBTCAtIHRoZSBzZWxlY3RlZCB2Q1BVIGlzIGludmFsaWQKKyogLUtW TV9FSU5WQUwgLSB0aGUgc3BlY2lmaWVkIE1TUiBpcyBpbnZhbGlkCisqIC1LVk1fRUlOVkFMIC0g dGhlIHBhZGRpbmcgaXMgbm90IHplcm8KKyogLUtWTV9FQUdBSU4gLSB0aGUgc2VsZWN0ZWQgdkNQ VSBjYW4ndCBiZSBpbnRyb3NwZWN0ZWQgeWV0CisqIC1LVk1fRVBFUk0gIC0gdGhlIGludGVyY2Vw dGlvbiBvZiB0aGUgc2VsZWN0ZWQgTVNSIGlzIGRpc2FsbG93ZWQKKyAgICAgICAgICAgICAgICBm cm9tIHVzZXJzcGFjZSAoS1ZNX1g4Nl9TRVRfTVNSX0ZJTFRFUikKKwogRXZlbnRzCiA9PT09PT0K IApAQCAtMTI2MCwzICsxMzAzLDM5IEBAIGludHJvc3BlY3Rpb24gdG9vbC4KIAlLVk1JX0RFU0Nf VFIKIAogYGB3cml0ZWBgIGlzIDEgaWYgdGhlIGRlc2NyaXB0b3Igd2FzIHdyaXR0ZW4sIDAgb3Ro ZXJ3aXNlLgorCis5LiBLVk1JX1ZDUFVfRVZFTlRfTVNSCistLS0tLS0tLS0tLS0tLS0tLS0tLS0t CisKKzpBcmNoaXRlY3R1cmVzOiB4ODYKKzpWZXJzaW9uczogPj0gMQorOkFjdGlvbnM6IENPTlRJ TlVFLCBDUkFTSAorOlBhcmFtZXRlcnM6CisKKzo6CisKKwlzdHJ1Y3Qga3ZtaV92Y3B1X2V2ZW50 OworCXN0cnVjdCBrdm1pX3ZjcHVfZXZlbnRfbXNyIHsKKwkJX191MzIgbXNyOworCQlfX3UzMiBw YWRkaW5nOworCQlfX3U2NCBvbGRfdmFsdWU7CisJCV9fdTY0IG5ld192YWx1ZTsKKwl9OworCis6 UmV0dXJuczoKKworOjoKKworCXN0cnVjdCBrdm1pX3ZjcHVfaGRyOworCXN0cnVjdCBrdm1pX3Zj cHVfZXZlbnRfcmVwbHk7CisJc3RydWN0IGt2bWlfdmNwdV9ldmVudF9tc3JfcmVwbHkgeworCQlf X3U2NCBuZXdfdmFsOworCX07CisKK1RoaXMgZXZlbnQgaXMgc2VudCB3aGVuIGEgbW9kZWwgc3Bl Y2lmaWMgcmVnaXN0ZXIgaXMgZ29pbmcgdG8gYmUgY2hhbmdlZAorYW5kIHRoZSBpbnRyb3NwZWN0 aW9uIGhhcyBiZWVuIGVuYWJsZWQgZm9yIHRoaXMgZXZlbnQgYW5kIGZvciB0aGlzIHNwZWNpZmlj CityZWdpc3RlciAoc2VlICoqS1ZNSV9WQ1BVX0NPTlRST0xfRVZFTlRTKiopLgorCitgYGt2bWlf dmNwdV9ldmVudGBgICh3aXRoIHRoZSB2Q1BVIHN0YXRlKSwgdGhlIE1TUiBudW1iZXIgKGBgbXNy YGApLAordGhlIG9sZCB2YWx1ZSAoYGBvbGRfdmFsdWVgYCkgYW5kIHRoZSBuZXcgdmFsdWUgKGBg bmV3X3ZhbHVlYGApIGFyZSBzZW50Cit0byB0aGUgaW50cm9zcGVjdGlvbiB0b29sLiBUaGUgKkNP TlRJTlVFKiBhY3Rpb24gd2lsbCBzZXQgdGhlIGBgbmV3X3ZhbGBgLgpkaWZmIC0tZ2l0IGEvYXJj aC94ODYvaW5jbHVkZS9hc20va3ZtaV9ob3N0LmggYi9hcmNoL3g4Ni9pbmNsdWRlL2FzbS9rdm1p X2hvc3QuaAppbmRleCBhODcyMjc3ZWJhNjcuLjVhNGZjNWI4MDkwNyAxMDA2NDQKLS0tIGEvYXJj aC94ODYvaW5jbHVkZS9hc20va3ZtaV9ob3N0LmgKKysrIGIvYXJjaC94ODYvaW5jbHVkZS9hc20v a3ZtaV9ob3N0LmgKQEAgLTQsNyArNCwxMCBAQAogCiAjaW5jbHVkZSA8YXNtL2t2bWkuaD4KIAor c3RydWN0IG1zcl9kYXRhOworCiAjZGVmaW5lIEtWTUlfTlVNX0NSIDUKKyNkZWZpbmUgS1ZNSV9O VU1fTVNSIDB4MjAwMAogCiBzdHJ1Y3Qga3ZtaV9tb25pdG9yX2ludGVyY2VwdGlvbiB7CiAJYm9v bCBrdm1pX2ludGVyY2VwdGVkOwpAQCAtMTgsNiArMjEsMTIgQEAgc3RydWN0IGt2bWlfaW50ZXJj ZXB0aW9uIHsKIAlzdHJ1Y3Qga3ZtaV9tb25pdG9yX2ludGVyY2VwdGlvbiBicmVha3BvaW50Owog CXN0cnVjdCBrdm1pX21vbml0b3JfaW50ZXJjZXB0aW9uIGNyM3c7CiAJc3RydWN0IGt2bWlfbW9u aXRvcl9pbnRlcmNlcHRpb24gZGVzY3JpcHRvcjsKKwlzdHJ1Y3QgeworCQlzdHJ1Y3QgeworCQkJ REVDTEFSRV9CSVRNQVAobG93LCBLVk1JX05VTV9NU1IpOworCQkJREVDTEFSRV9CSVRNQVAoaGln aCwgS1ZNSV9OVU1fTVNSKTsKKwkJfSBrdm1pX21hc2s7CisJfSBtc3J3OwogfTsKIAogc3RydWN0 IGt2bV92Y3B1X2FyY2hfaW50cm9zcGVjdGlvbiB7CkBAIC01MSw2ICs2MCw3IEBAIHZvaWQga3Zt aV94c2V0YnZfZXZlbnQoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LCB1OCB4Y3IsCiAJCSAgICAgICB1 NjQgb2xkX3ZhbHVlLCB1NjQgbmV3X3ZhbHVlKTsKIGJvb2wga3ZtaV9tb25pdG9yX2Rlc2NfaW50 ZXJjZXB0KHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwgYm9vbCBlbmFibGUpOwogYm9vbCBrdm1pX2Rl c2NyaXB0b3JfZXZlbnQoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LCB1OCBkZXNjcmlwdG9yLCBib29s IHdyaXRlKTsKK2Jvb2wga3ZtaV9tc3JfZXZlbnQoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LCBzdHJ1 Y3QgbXNyX2RhdGEgKm1zcik7CiAKICNlbHNlIC8qIENPTkZJR19LVk1fSU5UUk9TUEVDVElPTiAq LwogCkBAIC03MCw2ICs4MCw4IEBAIHN0YXRpYyBpbmxpbmUgYm9vbCBrdm1pX21vbml0b3JfZGVz Y19pbnRlcmNlcHQoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LAogCQkJCQkgICAgICAgYm9vbCBlbmFi bGUpIHsgcmV0dXJuIGZhbHNlOyB9CiBzdGF0aWMgaW5saW5lIGJvb2wga3ZtaV9kZXNjcmlwdG9y X2V2ZW50KHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwgdTggZGVzY3JpcHRvciwKIAkJCQkJIGJvb2wg d3JpdGUpIHsgcmV0dXJuIHRydWU7IH0KK3N0YXRpYyBpbmxpbmUgYm9vbCBrdm1pX21zcl9ldmVu dChzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsIHN0cnVjdCBtc3JfZGF0YSAqbXNyKQorCQkJCXsgcmV0 dXJuIHRydWU7IH0KIAogI2VuZGlmIC8qIENPTkZJR19LVk1fSU5UUk9TUEVDVElPTiAqLwogCmRp ZmYgLS1naXQgYS9hcmNoL3g4Ni9pbmNsdWRlL3VhcGkvYXNtL2t2bWkuaCBiL2FyY2gveDg2L2lu Y2x1ZGUvdWFwaS9hc20va3ZtaS5oCmluZGV4IDljNjA4ZWY1ZGFhMy4uNmVmMTQ0ZGRiNGJiIDEw MDY0NAotLS0gYS9hcmNoL3g4Ni9pbmNsdWRlL3VhcGkvYXNtL2t2bWkuaAorKysgYi9hcmNoL3g4 Ni9pbmNsdWRlL3VhcGkvYXNtL2t2bWkuaApAQCAtMTQxLDQgKzE0MSwyMiBAQCBzdHJ1Y3Qga3Zt aV92Y3B1X2V2ZW50X2Rlc2NyaXB0b3IgewogCV9fdTggcGFkZGluZ1s2XTsKIH07CiAKK3N0cnVj dCBrdm1pX3ZjcHVfY29udHJvbF9tc3IgeworCV9fdTggZW5hYmxlOworCV9fdTggcGFkZGluZzE7 CisJX191MTYgcGFkZGluZzI7CisJX191MzIgbXNyOworfTsKKworc3RydWN0IGt2bWlfdmNwdV9l dmVudF9tc3IgeworCV9fdTMyIG1zcjsKKwlfX3UzMiBwYWRkaW5nOworCV9fdTY0IG9sZF92YWx1 ZTsKKwlfX3U2NCBuZXdfdmFsdWU7Cit9OworCitzdHJ1Y3Qga3ZtaV92Y3B1X2V2ZW50X21zcl9y ZXBseSB7CisJX191NjQgbmV3X3ZhbDsKK307CisKICNlbmRpZiAvKiBfVUFQSV9BU01fWDg2X0tW TUlfSCAqLwpkaWZmIC0tZ2l0IGEvYXJjaC94ODYva3ZtL2t2bWkuYyBiL2FyY2gveDg2L2t2bS9r dm1pLmMKaW5kZXggNDEwNmFlNjNhMTE1Li5jZTI5ZTAxYmE3YTYgMTAwNjQ0Ci0tLSBhL2FyY2gv eDg2L2t2bS9rdm1pLmMKKysrIGIvYXJjaC94ODYva3ZtL2t2bWkuYwpAQCAtMTYsNiArMTYsNyBA QCB2b2lkIGt2bWlfYXJjaF9pbml0X3ZjcHVfZXZlbnRzX21hc2sodW5zaWduZWQgbG9uZyAqc3Vw cG9ydGVkKQogCXNldF9iaXQoS1ZNSV9WQ1BVX0VWRU5UX0NSLCBzdXBwb3J0ZWQpOwogCXNldF9i aXQoS1ZNSV9WQ1BVX0VWRU5UX0hZUEVSQ0FMTCwgc3VwcG9ydGVkKTsKIAlzZXRfYml0KEtWTUlf VkNQVV9FVkVOVF9ERVNDUklQVE9SLCBzdXBwb3J0ZWQpOworCXNldF9iaXQoS1ZNSV9WQ1BVX0VW RU5UX01TUiwgc3VwcG9ydGVkKTsKIAlzZXRfYml0KEtWTUlfVkNQVV9FVkVOVF9UUkFQLCBzdXBw b3J0ZWQpOwogCXNldF9iaXQoS1ZNSV9WQ1BVX0VWRU5UX1hTRVRCViwgc3VwcG9ydGVkKTsKIH0K QEAgLTM0NCw2ICszNDUsNzcgQEAgc3RhdGljIHZvaWQga3ZtaV9hcmNoX2Rpc2FibGVfZGVzY19p bnRlcmNlcHQoc3RydWN0IGt2bV92Y3B1ICp2Y3B1KQogCXZjcHUtPmFyY2gua3ZtaS0+ZGVzY3Jp cHRvci5rdm1faW50ZXJjZXB0ZWQgPSBmYWxzZTsKIH0KIAorc3RhdGljIHVuc2lnbmVkIGxvbmcg Km1zcl9tYXNrKHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwgdW5zaWduZWQgaW50ICptc3IpCit7CisJ c3dpdGNoICgqbXNyKSB7CisJY2FzZSAwIC4uLiAweDFmZmY6CisJCXJldHVybiB2Y3B1LT5hcmNo Lmt2bWktPm1zcncua3ZtaV9tYXNrLmxvdzsKKwljYXNlIDB4YzAwMDAwMDAgLi4uIDB4YzAwMDFm ZmY6CisJCSptc3IgJj0gMHgxZmZmOworCQlyZXR1cm4gdmNwdS0+YXJjaC5rdm1pLT5tc3J3Lmt2 bWlfbWFzay5oaWdoOworCX0KKworCXJldHVybiBOVUxMOworfQorCitzdGF0aWMgYm9vbCB0ZXN0 X21zcl9tYXNrKHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwgdW5zaWduZWQgaW50IG1zcikKK3sKKwl1 bnNpZ25lZCBsb25nICptYXNrID0gbXNyX21hc2sodmNwdSwgJm1zcik7CisKKwlpZiAoIW1hc2sp CisJCXJldHVybiBmYWxzZTsKKworCXJldHVybiAhIXRlc3RfYml0KG1zciwgbWFzayk7Cit9CisK K3N0YXRpYyBib29sIG1zcl9jb250cm9sKHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwgdW5zaWduZWQg aW50IG1zciwgYm9vbCBlbmFibGUpCit7CisJdW5zaWduZWQgbG9uZyAqbWFzayA9IG1zcl9tYXNr KHZjcHUsICZtc3IpOworCisJaWYgKCFtYXNrKQorCQlyZXR1cm4gZmFsc2U7CisKKwlpZiAoZW5h YmxlKQorCQlzZXRfYml0KG1zciwgbWFzayk7CisJZWxzZQorCQljbGVhcl9iaXQobXNyLCBtYXNr KTsKKworCXJldHVybiB0cnVlOworfQorCitzdGF0aWMgdW5zaWduZWQgaW50IG1zcl9tYXNrX3Rv X2Jhc2Uoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LCB1bnNpZ25lZCBsb25nICptYXNrKQoreworCWlm IChtYXNrID09IHZjcHUtPmFyY2gua3ZtaS0+bXNydy5rdm1pX21hc2suaGlnaCkKKwkJcmV0dXJu IDB4YzAwMDAwMDA7CisKKwlyZXR1cm4gMDsKK30KKwordm9pZCBrdm1pX2NvbnRyb2xfbXNyd19p bnRlcmNlcHQoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LCB1MzIgbXNyLCBib29sIGVuYWJsZSkKK3sK Kwlrdm1feDg2X29wcy5jb250cm9sX21zcl9pbnRlcmNlcHQodmNwdSwgbXNyLCBNU1JfVFlQRV9X LCBlbmFibGUpOworCW1zcl9jb250cm9sKHZjcHUsIG1zciwgZW5hYmxlKTsKK30KKworc3RhdGlj IHZvaWQga3ZtaV9hcmNoX2Rpc2FibGVfbXNyX2ludGVyY2VwdChzdHJ1Y3Qga3ZtX3ZjcHUgKnZj cHUsCisJCQkJCSAgICB1bnNpZ25lZCBsb25nICptYXNrKQoreworCXVuc2lnbmVkIGludCBtc3Jf YmFzZSA9IG1zcl9tYXNrX3RvX2Jhc2UodmNwdSwgbWFzayk7CisJaW50IG9mZnNldCA9IC0xOwor CisJZm9yICg7OykgeworCQlvZmZzZXQgPSBmaW5kX25leHRfYml0KG1hc2ssIEtWTUlfTlVNX01T Uiwgb2Zmc2V0ICsgMSk7CisKKwkJaWYgKG9mZnNldCA+PSBLVk1JX05VTV9NU1IpCisJCQlicmVh azsKKworCQlrdm1feDg2X29wcy5jb250cm9sX21zcl9pbnRlcmNlcHQodmNwdSwgbXNyX2Jhc2Ug KyBvZmZzZXQsCisJCQkJCQkgICBNU1JfVFlQRV9XLCBmYWxzZSk7CisJfQorCisJYml0bWFwX3pl cm8obWFzaywgS1ZNSV9OVU1fTVNSKTsKK30KKwogaW50IGt2bWlfYXJjaF9jbWRfY29udHJvbF9p bnRlcmNlcHQoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LAogCQkJCSAgICB1bnNpZ25lZCBpbnQgZXZl bnRfaWQsIGJvb2wgZW5hYmxlKQogewpAQCAtMzg1LDkgKzQ1NywxMyBAQCB2b2lkIGt2bWlfYXJj aF9icmVha3BvaW50X2V2ZW50KHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwgdTY0IGd2YSwgdTggaW5z bl9sZW4pCiAKIHN0YXRpYyB2b2lkIGt2bWlfYXJjaF9yZXN0b3JlX2ludGVyY2VwdGlvbihzdHJ1 Y3Qga3ZtX3ZjcHUgKnZjcHUpCiB7CisJc3RydWN0IGt2bWlfaW50ZXJjZXB0aW9uICphcmNoX3Zj cHVpID0gdmNwdS0+YXJjaC5rdm1pOworCiAJa3ZtaV9hcmNoX2Rpc2FibGVfYnBfaW50ZXJjZXB0 KHZjcHUpOwogCWt2bWlfYXJjaF9kaXNhYmxlX2NyM3dfaW50ZXJjZXB0KHZjcHUpOwogCWt2bWlf YXJjaF9kaXNhYmxlX2Rlc2NfaW50ZXJjZXB0KHZjcHUpOworCWt2bWlfYXJjaF9kaXNhYmxlX21z cl9pbnRlcmNlcHQodmNwdSwgYXJjaF92Y3B1aS0+bXNydy5rdm1pX21hc2subG93KTsKKwlrdm1p X2FyY2hfZGlzYWJsZV9tc3JfaW50ZXJjZXB0KHZjcHUsIGFyY2hfdmNwdWktPm1zcncua3ZtaV9t YXNrLmhpZ2gpOwogfQogCiBib29sIGt2bWlfYXJjaF9jbGVhbl91cF9pbnRlcmNlcHRpb24oc3Ry dWN0IGt2bV92Y3B1ICp2Y3B1KQpAQCAtNzAwLDMgKzc3Niw1MiBAQCBib29sIGt2bWlfZGVzY3Jp cHRvcl9ldmVudChzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsIHU4IGRlc2NyaXB0b3IsIGJvb2wgd3Jp dGUpCiAJcmV0dXJuIHJldDsKIH0KIEVYUE9SVF9TWU1CT0woa3ZtaV9kZXNjcmlwdG9yX2V2ZW50 KTsKKworc3RhdGljIGJvb2wgX19rdm1pX21zcl9ldmVudChzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUs IHN0cnVjdCBtc3JfZGF0YSAqbXNyKQoreworCXN0cnVjdCBtc3JfZGF0YSBvbGRfbXNyID0gewor CQkuaG9zdF9pbml0aWF0ZWQgPSB0cnVlLAorCQkuaW5kZXggPSBtc3ItPmluZGV4LAorCX07CisJ dTY0IHJlcGx5X3ZhbHVlOworCXUzMiBhY3Rpb247CisJYm9vbCByZXQ7CisKKwlpZiAoIXRlc3Rf bXNyX21hc2sodmNwdSwgbXNyLT5pbmRleCkpCisJCXJldHVybiB0cnVlOworCWlmIChrdm1feDg2 X29wcy5nZXRfbXNyKHZjcHUsICZvbGRfbXNyKSkKKwkJcmV0dXJuIHRydWU7CisJaWYgKG9sZF9t c3IuZGF0YSA9PSBtc3ItPmRhdGEpCisJCXJldHVybiB0cnVlOworCisJYWN0aW9uID0ga3ZtaV9t c2dfc2VuZF92Y3B1X21zcih2Y3B1LCBtc3ItPmluZGV4LCBvbGRfbXNyLmRhdGEsCisJCQkJCW1z ci0+ZGF0YSwgJnJlcGx5X3ZhbHVlKTsKKwlzd2l0Y2ggKGFjdGlvbikgeworCWNhc2UgS1ZNSV9F VkVOVF9BQ1RJT05fQ09OVElOVUU6CisJCW1zci0+ZGF0YSA9IHJlcGx5X3ZhbHVlOworCQlyZXQg PSB0cnVlOworCQlicmVhazsKKwlkZWZhdWx0OgorCQlrdm1pX2hhbmRsZV9jb21tb25fZXZlbnRf YWN0aW9ucyh2Y3B1LCBhY3Rpb24pOworCQlyZXQgPSBmYWxzZTsKKwl9CisKKwlyZXR1cm4gcmV0 OworfQorCitib29sIGt2bWlfbXNyX2V2ZW50KHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwgc3RydWN0 IG1zcl9kYXRhICptc3IpCit7CisJc3RydWN0IGt2bV9pbnRyb3NwZWN0aW9uICprdm1pOworCWJv b2wgcmV0ID0gdHJ1ZTsKKworCWt2bWkgPSBrdm1pX2dldCh2Y3B1LT5rdm0pOworCWlmICgha3Zt aSkKKwkJcmV0dXJuIHRydWU7CisKKwlpZiAoaXNfdmNwdV9ldmVudF9lbmFibGVkKHZjcHUsIEtW TUlfVkNQVV9FVkVOVF9NU1IpKQorCQlyZXQgPSBfX2t2bWlfbXNyX2V2ZW50KHZjcHUsIG1zcik7 CisKKwlrdm1pX3B1dCh2Y3B1LT5rdm0pOworCisJcmV0dXJuIHJldDsKK30KZGlmZiAtLWdpdCBh L2FyY2gveDg2L2t2bS9rdm1pLmggYi9hcmNoL3g4Ni9rdm0va3ZtaS5oCmluZGV4IDkyNDIyZTJl NTdjZi4uNjQ4M2VkYmI4MGM1IDEwMDY0NAotLS0gYS9hcmNoL3g4Ni9rdm0va3ZtaS5oCisrKyBi L2FyY2gveDg2L2t2bS9rdm1pLmgKQEAgLTE3LDUgKzE3LDggQEAgdTMyIGt2bWlfbXNnX3NlbmRf dmNwdV90cmFwKHN0cnVjdCBrdm1fdmNwdSAqdmNwdSk7CiB1MzIga3ZtaV9tc2dfc2VuZF92Y3B1 X3hzZXRidihzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsIHU4IHhjciwKIAkJCSAgICAgIHU2NCBvbGRf dmFsdWUsIHU2NCBuZXdfdmFsdWUpOwogdTMyIGt2bWlfbXNnX3NlbmRfdmNwdV9kZXNjcmlwdG9y KHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwgdTggZGVzYywgYm9vbCB3cml0ZSk7Cit2b2lkIGt2bWlf Y29udHJvbF9tc3J3X2ludGVyY2VwdChzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsIHUzMiBtc3IsIGJv b2wgZW5hYmxlKTsKK3UzMiBrdm1pX21zZ19zZW5kX3ZjcHVfbXNyKHN0cnVjdCBrdm1fdmNwdSAq dmNwdSwgdTMyIG1zciwgdTY0IG9sZF92YWx1ZSwKKwkJCSAgIHU2NCBuZXdfdmFsdWUsIHU2NCAq cmV0X3ZhbHVlKTsKIAogI2VuZGlmCmRpZmYgLS1naXQgYS9hcmNoL3g4Ni9rdm0va3ZtaV9tc2cu YyBiL2FyY2gveDg2L2t2bS9rdm1pX21zZy5jCmluZGV4IGYwYjQwMTY4MjBjZS4uNmQ0NWIxYzQ5 MTg0IDEwMDY0NAotLS0gYS9hcmNoL3g4Ni9rdm0va3ZtaV9tc2cuYworKysgYi9hcmNoL3g4Ni9r dm0va3ZtaV9tc2cuYwpAQCAtMjQ4LDggKzI0OCwzNiBAQCBzdGF0aWMgaW50IGhhbmRsZV92Y3B1 X2dldF9tdHJyX3R5cGUoY29uc3Qgc3RydWN0IGt2bWlfdmNwdV9tc2dfam9iICpqb2IsCiAJcmV0 dXJuIGt2bWlfbXNnX3ZjcHVfcmVwbHkoam9iLCBtc2csIDAsICZycGwsIHNpemVvZihycGwpKTsK IH0KIAorc3RhdGljIGJvb2wgaXNfdmFsaWRfbXNyKHVuc2lnbmVkIGludCBtc3IpCit7CisJcmV0 dXJuIG1zciA8PSAweDFmZmYgfHwgKG1zciA+PSAweGMwMDAwMDAwICYmIG1zciA8PSAweGMwMDAx ZmZmKTsKK30KKworc3RhdGljIGludCBoYW5kbGVfdmNwdV9jb250cm9sX21zcihjb25zdCBzdHJ1 Y3Qga3ZtaV92Y3B1X21zZ19qb2IgKmpvYiwKKwkJCQkgICBjb25zdCBzdHJ1Y3Qga3ZtaV9tc2df aGRyICptc2csCisJCQkJICAgY29uc3Qgdm9pZCAqX3JlcSkKK3sKKwljb25zdCBzdHJ1Y3Qga3Zt aV92Y3B1X2NvbnRyb2xfbXNyICpyZXEgPSBfcmVxOworCWludCBlYyA9IDA7CisKKwlpZiAocmVx LT5wYWRkaW5nMSB8fCByZXEtPnBhZGRpbmcyIHx8IHJlcS0+ZW5hYmxlID4gMSkKKwkJZWMgPSAt S1ZNX0VJTlZBTDsKKwllbHNlIGlmICghaXNfdmFsaWRfbXNyKHJlcS0+bXNyKSkKKwkJZWMgPSAt S1ZNX0VJTlZBTDsKKwllbHNlIGlmIChyZXEtPmVuYWJsZSAmJgorCQkgIWt2bV9tc3JfYWxsb3dl ZChqb2ItPnZjcHUsIHJlcS0+bXNyLAorCQkJCSAgS1ZNX01TUl9GSUxURVJfV1JJVEUpKQorCQll YyA9IC1LVk1fRVBFUk07CisJZWxzZQorCQlrdm1pX2NvbnRyb2xfbXNyd19pbnRlcmNlcHQoam9i LT52Y3B1LCByZXEtPm1zciwKKwkJCQkJICAgIHJlcS0+ZW5hYmxlID09IDEpOworCisJcmV0dXJu IGt2bWlfbXNnX3ZjcHVfcmVwbHkoam9iLCBtc2csIGVjLCBOVUxMLCAwKTsKK30KKwogc3RhdGlj IGt2bWlfdmNwdV9tc2dfam9iX2ZjdCBjb25zdCBtc2dfdmNwdVtdID0gewogCVtLVk1JX1ZDUFVf Q09OVFJPTF9DUl0gICAgICAgPSBoYW5kbGVfdmNwdV9jb250cm9sX2NyLAorCVtLVk1JX1ZDUFVf Q09OVFJPTF9NU1JdICAgICAgPSBoYW5kbGVfdmNwdV9jb250cm9sX21zciwKIAlbS1ZNSV9WQ1BV X0dFVF9DUFVJRF0gICAgICAgID0gaGFuZGxlX3ZjcHVfZ2V0X2NwdWlkLAogCVtLVk1JX1ZDUFVf R0VUX0lORk9dICAgICAgICAgPSBoYW5kbGVfdmNwdV9nZXRfaW5mbywKIAlbS1ZNSV9WQ1BVX0dF VF9NVFJSX1RZUEVdICAgID0gaGFuZGxlX3ZjcHVfZ2V0X210cnJfdHlwZSwKQEAgLTM0OSwzICsz NzcsMjcgQEAgdTMyIGt2bWlfbXNnX3NlbmRfdmNwdV9kZXNjcmlwdG9yKHN0cnVjdCBrdm1fdmNw dSAqdmNwdSwgdTggZGVzYywgYm9vbCB3cml0ZSkKIAlyZXR1cm4gYWN0aW9uOwogCiB9CisKK3Uz MiBrdm1pX21zZ19zZW5kX3ZjcHVfbXNyKHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwgdTMyIG1zciwg dTY0IG9sZF92YWx1ZSwKKwkJCSAgIHU2NCBuZXdfdmFsdWUsIHU2NCAqcmV0X3ZhbHVlKQorewor CXN0cnVjdCBrdm1pX3ZjcHVfZXZlbnRfbXNyIGU7CisJc3RydWN0IGt2bWlfdmNwdV9ldmVudF9t c3JfcmVwbHkgcjsKKwlpbnQgZXJyLCBhY3Rpb247CisKKwltZW1zZXQoJmUsIDAsIHNpemVvZihl KSk7CisJZS5tc3IgPSBtc3I7CisJZS5vbGRfdmFsdWUgPSBvbGRfdmFsdWU7CisJZS5uZXdfdmFs dWUgPSBuZXdfdmFsdWU7CisKKwllcnIgPSBrdm1pX3NlbmRfdmNwdV9ldmVudCh2Y3B1LCBLVk1J X1ZDUFVfRVZFTlRfTVNSLCAmZSwgc2l6ZW9mKGUpLAorCQkJCSAgICZyLCBzaXplb2YociksICZh Y3Rpb24pOworCWlmIChlcnIpIHsKKwkJYWN0aW9uID0gS1ZNSV9FVkVOVF9BQ1RJT05fQ09OVElO VUU7CisJCSpyZXRfdmFsdWUgPSBuZXdfdmFsdWU7CisJfSBlbHNlIHsKKwkJKnJldF92YWx1ZSA9 IHIubmV3X3ZhbDsKKwl9CisKKwlyZXR1cm4gYWN0aW9uOworfQpkaWZmIC0tZ2l0IGEvYXJjaC94 ODYva3ZtL3g4Ni5jIGIvYXJjaC94ODYva3ZtL3g4Ni5jCmluZGV4IDdhMWNkMTRiMGE4Ny4uMzgx ZTNkZmJhNTM1IDEwMDY0NAotLS0gYS9hcmNoL3g4Ni9rdm0veDg2LmMKKysrIGIvYXJjaC94ODYv a3ZtL3g4Ni5jCkBAIC0xNTg1LDYgKzE1ODUsOSBAQCBzdGF0aWMgaW50IF9fa3ZtX3NldF9tc3Io c3RydWN0IGt2bV92Y3B1ICp2Y3B1LCB1MzIgaW5kZXgsIHU2NCBkYXRhLAogCW1zci5pbmRleCA9 IGluZGV4OwogCW1zci5ob3N0X2luaXRpYXRlZCA9IGhvc3RfaW5pdGlhdGVkOwogCisJaWYgKCFo b3N0X2luaXRpYXRlZCAmJiAha3ZtaV9tc3JfZXZlbnQodmNwdSwgJm1zcikpCisJCXJldHVybiAx OworCiAJcmV0dXJuIGt2bV94ODZfb3BzLnNldF9tc3IodmNwdSwgJm1zcik7CiB9CiAKZGlmZiAt LWdpdCBhL2luY2x1ZGUvdWFwaS9saW51eC9rdm1pLmggYi9pbmNsdWRlL3VhcGkvbGludXgva3Zt aS5oCmluZGV4IDA5Zjc4YzBlZmM0Zi4uYzhlN2Y0NTE2Mzc5IDEwMDY0NAotLS0gYS9pbmNsdWRl L3VhcGkvbGludXgva3ZtaS5oCisrKyBiL2luY2x1ZGUvdWFwaS9saW51eC9rdm1pLmgKQEAgLTQ4 LDYgKzQ4LDcgQEAgZW51bSB7CiAJS1ZNSV9WQ1BVX0dFVF9YU0FWRSAgICAgICAgPSBLVk1JX1ZD UFVfTUVTU0FHRV9JRCg5KSwKIAlLVk1JX1ZDUFVfU0VUX1hTQVZFICAgICAgICA9IEtWTUlfVkNQ VV9NRVNTQUdFX0lEKDEwKSwKIAlLVk1JX1ZDUFVfR0VUX01UUlJfVFlQRSAgICA9IEtWTUlfVkNQ VV9NRVNTQUdFX0lEKDExKSwKKwlLVk1JX1ZDUFVfQ09OVFJPTF9NU1IgICAgICA9IEtWTUlfVkNQ VV9NRVNTQUdFX0lEKDEyKSwKIAogCUtWTUlfTkVYVF9WQ1BVX01FU1NBR0UKIH07CkBAIC02OSw2 ICs3MCw3IEBAIGVudW0gewogCUtWTUlfVkNQVV9FVkVOVF9UUkFQICAgICAgID0gS1ZNSV9WQ1BV X0VWRU5UX0lEKDQpLAogCUtWTUlfVkNQVV9FVkVOVF9YU0VUQlYgICAgID0gS1ZNSV9WQ1BVX0VW RU5UX0lEKDUpLAogCUtWTUlfVkNQVV9FVkVOVF9ERVNDUklQVE9SID0gS1ZNSV9WQ1BVX0VWRU5U X0lEKDYpLAorCUtWTUlfVkNQVV9FVkVOVF9NU1IgICAgICAgID0gS1ZNSV9WQ1BVX0VWRU5UX0lE KDcpLAogCiAJS1ZNSV9ORVhUX1ZDUFVfRVZFTlQKIH07CmRpZmYgLS1naXQgYS90b29scy90ZXN0 aW5nL3NlbGZ0ZXN0cy9rdm0veDg2XzY0L2t2bWlfdGVzdC5jIGIvdG9vbHMvdGVzdGluZy9zZWxm dGVzdHMva3ZtL3g4Nl82NC9rdm1pX3Rlc3QuYwppbmRleCBkMjZkZjNhOWZmZmYuLjJlMDdiMjJi YzhjMCAxMDA2NDQKLS0tIGEvdG9vbHMvdGVzdGluZy9zZWxmdGVzdHMva3ZtL3g4Nl82NC9rdm1p X3Rlc3QuYworKysgYi90b29scy90ZXN0aW5nL3NlbGZ0ZXN0cy9rdm0veDg2XzY0L2t2bWlfdGVz dC5jCkBAIC02MCw2ICs2MCw3IEBAIGVudW0gewogCUdVRVNUX1RFU1RfQ1IsCiAJR1VFU1RfVEVT VF9ERVNDUklQVE9SLAogCUdVRVNUX1RFU1RfSFlQRVJDQUxMLAorCUdVRVNUX1RFU1RfTVNSLAog CUdVRVNUX1RFU1RfWFNFVEJWLAogfTsKIApAQCAtMTA0LDYgKzEwNSwxNSBAQCBzdGF0aWMgdm9p ZCBndWVzdF9oeXBlcmNhbGxfdGVzdCh2b2lkKQogCWFzbSB2b2xhdGlsZSgiLmJ5dGUgMHgwZiww eDAxLDB4YzEiKTsKIH0KIAorc3RhdGljIHZvaWQgZ3Vlc3RfbXNyX3Rlc3Qodm9pZCkKK3sKKwl1 aW50NjRfdCBtc3I7CisKKwltc3IgPSByZG1zcihNU1JfTUlTQ19GRUFUVVJFU19FTkFCTEVTKTsK Kwltc3IgfD0gMTsgLyogTVNSX01JU0NfRkVBVFVSRVNfRU5BQkxFU19DUFVJRF9GQVVMVCAqLwor CXdybXNyKE1TUl9NSVNDX0ZFQVRVUkVTX0VOQUJMRVMsIG1zcik7Cit9CisKIC8qIGZyb20gZnB1 L2ludGVybmFsLmggKi8KIHN0YXRpYyB1NjQgeGdldGJ2KHUzMiBpbmRleCkKIHsKQEAgLTE2MSw2 ICsxNzEsOSBAQCBzdGF0aWMgdm9pZCBndWVzdF9jb2RlKHZvaWQpCiAJCWNhc2UgR1VFU1RfVEVT VF9IWVBFUkNBTEw6CiAJCQlndWVzdF9oeXBlcmNhbGxfdGVzdCgpOwogCQkJYnJlYWs7CisJCWNh c2UgR1VFU1RfVEVTVF9NU1I6CisJCQlndWVzdF9tc3JfdGVzdCgpOworCQkJYnJlYWs7CiAJCWNh c2UgR1VFU1RfVEVTVF9YU0VUQlY6CiAJCQlndWVzdF94c2V0YnZfdGVzdCgpOwogCQkJYnJlYWs7 CkBAIC0xNTc5LDYgKzE1OTIsMTAzIEBAIHN0YXRpYyB2b2lkIHRlc3RfZXZlbnRfZGVzY3JpcHRv cihzdHJ1Y3Qga3ZtX3ZtICp2bSkKIAlkaXNhYmxlX3ZjcHVfZXZlbnQodm0sIGV2ZW50X2lkKTsK IH0KIAorc3RhdGljIHZvaWQgY21kX2NvbnRyb2xfbXNyKHN0cnVjdCBrdm1fdm0gKnZtLCBfX3Uz MiBtc3IsIF9fdTggZW5hYmxlLAorCQkJICAgIGludCBleHBlY3RlZF9lcnIpCit7CisJc3RydWN0 IHsKKwkJc3RydWN0IGt2bWlfbXNnX2hkciBoZHI7CisJCXN0cnVjdCBrdm1pX3ZjcHVfaGRyIHZj cHVfaGRyOworCQlzdHJ1Y3Qga3ZtaV92Y3B1X2NvbnRyb2xfbXNyIGNtZDsKKwl9IHJlcSA9IHt9 OworCisJcmVxLmNtZC5tc3IgPSBtc3I7CisJcmVxLmNtZC5lbmFibGUgPSBlbmFibGU7CisKKwl0 ZXN0X3ZjcHUwX2NvbW1hbmQodm0sIEtWTUlfVkNQVV9DT05UUk9MX01TUiwgJnJlcS5oZHIsIHNp emVvZihyZXEpLAorCQkJICAgICBOVUxMLCAwLCBleHBlY3RlZF9lcnIpOworfQorCitzdGF0aWMg dm9pZCBlbmFibGVfbXNyX2V2ZW50cyhzdHJ1Y3Qga3ZtX3ZtICp2bSwgX191MzIgbXNyKQorewor CWVuYWJsZV92Y3B1X2V2ZW50KHZtLCBLVk1JX1ZDUFVfRVZFTlRfTVNSKTsKKwljbWRfY29udHJv bF9tc3Iodm0sIG1zciwgMSwgMCk7Cit9CisKK3N0YXRpYyB2b2lkIGRpc2FibGVfbXNyX2V2ZW50 cyhzdHJ1Y3Qga3ZtX3ZtICp2bSwgX191MzIgbXNyKQoreworCWNtZF9jb250cm9sX21zcih2bSwg bXNyLCAwLCAwKTsKKwlkaXNhYmxlX3ZjcHVfZXZlbnQodm0sIEtWTUlfVkNQVV9FVkVOVF9NU1Ip OworfQorCitzdGF0aWMgdm9pZCBoYW5kbGVfbXNyX2V2ZW50KHN0cnVjdCBrdm1fdm0gKnZtLCBf X3UxNiBldmVudF9pZCwgX191MzIgbXNyLAorCQkJICAgICBfX3U2NCAqb2xkX3ZhbHVlKQorewor CXN0cnVjdCBrdm1pX21zZ19oZHIgaGRyOworCXN0cnVjdCB7CisJCXN0cnVjdCB2Y3B1X2V2ZW50 IHZjcHVfZXY7CisJCXN0cnVjdCBrdm1pX3ZjcHVfZXZlbnRfbXNyIG1zcjsKKwl9IGV2OworCXN0 cnVjdCB7CisJCXN0cnVjdCB2Y3B1X3JlcGx5IGNvbW1vbjsKKwkJc3RydWN0IGt2bWlfdmNwdV9l dmVudF9tc3JfcmVwbHkgbXNyOworCX0gcnBsID0ge307CisKKwlyZWNlaXZlX3ZjcHVfZXZlbnQo JmhkciwgJmV2LnZjcHVfZXYsIHNpemVvZihldiksIGV2ZW50X2lkKTsKKworCXByX2RlYnVnKCJN U1IgMHgleCwgb2xkIDB4JWxseCwgbmV3IDB4JWxseFxuIiwKKwkJIGV2Lm1zci5tc3IsIGV2Lm1z ci5vbGRfdmFsdWUsIGV2Lm1zci5uZXdfdmFsdWUpOworCisJVEVTVF9BU1NFUlQoZXYubXNyLm1z ciA9PSBtc3IsCisJCSJVbmV4cGVjdGVkIE1TUiBldmVudCwgcmVjZWl2ZWQgTVNSIDB4JXgsIGV4 cGVjdGVkIE1TUiAweCV4IiwKKwkJZXYubXNyLm1zciwgbXNyKTsKKworCSpvbGRfdmFsdWUgPSBy cGwubXNyLm5ld192YWwgPSBldi5tc3Iub2xkX3ZhbHVlOworCisJcmVwbHlfdG9fZXZlbnQoJmhk ciwgJmV2LnZjcHVfZXYsIEtWTUlfRVZFTlRfQUNUSU9OX0NPTlRJTlVFLAorCQkJJnJwbC5jb21t b24sIHNpemVvZihycGwpKTsKK30KKworc3RhdGljIHZvaWQgdGVzdF9pbnZhbGlkX2NvbnRyb2xf bXNyKHN0cnVjdCBrdm1fdm0gKnZtLCBfX3UzMiBtc3IpCit7CisJX191OCBlbmFibGUgPSAxLCBl bmFibGVfaW52YWwgPSAyOworCWludCBleHBlY3RlZF9lcnIgPSAtS1ZNX0VJTlZBTDsKKwlfX3Uz MiBtc3JfaW52YWwgPSAtMTsKKworCWNtZF9jb250cm9sX21zcih2bSwgbXNyLCBlbmFibGVfaW52 YWwsIGV4cGVjdGVkX2Vycik7CisJY21kX2NvbnRyb2xfbXNyKHZtLCBtc3JfaW52YWwsIGVuYWJs ZSwgZXhwZWN0ZWRfZXJyKTsKK30KKworc3RhdGljIHZvaWQgdGVzdF9jbWRfdmNwdV9jb250cm9s X21zcihzdHJ1Y3Qga3ZtX3ZtICp2bSkKK3sKKwlzdHJ1Y3QgdmNwdV93b3JrZXJfZGF0YSBkYXRh ID0geworCQkudm0gPSB2bSwKKwkJLnZjcHVfaWQgPSBWQ1BVX0lELAorCQkudGVzdF9pZCA9IEdV RVNUX1RFU1RfTVNSLAorCX07CisJX191MTYgZXZlbnRfaWQgPSBLVk1JX1ZDUFVfRVZFTlRfTVNS OworCV9fdTMyIG1zciA9IE1TUl9NSVNDX0ZFQVRVUkVTX0VOQUJMRVM7CisJcHRocmVhZF90IHZj cHVfdGhyZWFkOworCXVpbnQ2NF90IG1zcl9kYXRhOworCV9fdTY0IG9sZF92YWx1ZTsKKworCWVu YWJsZV9tc3JfZXZlbnRzKHZtLCBtc3IpOworCisJdmNwdV90aHJlYWQgPSBzdGFydF92Y3B1X3dv cmtlcigmZGF0YSk7CisKKwloYW5kbGVfbXNyX2V2ZW50KHZtLCBldmVudF9pZCwgbXNyLCAmb2xk X3ZhbHVlKTsKKworCXdhaXRfdmNwdV93b3JrZXIodmNwdV90aHJlYWQpOworCisJZGlzYWJsZV9t c3JfZXZlbnRzKHZtLCBtc3IpOworCisJbXNyX2RhdGEgPSB2Y3B1X2dldF9tc3Iodm0sIFZDUFVf SUQsIG1zcik7CisJVEVTVF9BU1NFUlQobXNyX2RhdGEgPT0gb2xkX3ZhbHVlLAorCQkiRmFpbGVk IHRvIGJsb2NrIE1TUiAweCV4IHVwZGF0ZSwgdmFsdWUgMHglbHgsIGV4cGVjdGVkIDB4JWxseCIs CisJCW1zciwgbXNyX2RhdGEsIG9sZF92YWx1ZSk7CisKKwl0ZXN0X2ludmFsaWRfY29udHJvbF9t c3Iodm0sIG1zcik7Cit9CisKIHN0YXRpYyB2b2lkIHRlc3RfaW50cm9zcGVjdGlvbihzdHJ1Y3Qg a3ZtX3ZtICp2bSkKIHsKIAlzcmFuZG9tKHRpbWUoMCkpOwpAQCAtMTYxMCw2ICsxNzIwLDcgQEAg c3RhdGljIHZvaWQgdGVzdF9pbnRyb3NwZWN0aW9uKHN0cnVjdCBrdm1fdm0gKnZtKQogCXRlc3Rf Y21kX3ZjcHVfeHNhdmUodm0pOwogCXRlc3RfY21kX3ZjcHVfZ2V0X210cnJfdHlwZSh2bSk7CiAJ dGVzdF9ldmVudF9kZXNjcmlwdG9yKHZtKTsKKwl0ZXN0X2NtZF92Y3B1X2NvbnRyb2xfbXNyKHZt KTsKIAogCXVuaG9va19pbnRyb3NwZWN0aW9uKHZtKTsKIH0KX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX18KVmlydHVhbGl6YXRpb24gbWFpbGluZyBsaXN0ClZp cnR1YWxpemF0aW9uQGxpc3RzLmxpbnV4LWZvdW5kYXRpb24ub3JnCmh0dHBzOi8vbGlzdHMubGlu dXhmb3VuZGF0aW9uLm9yZy9tYWlsbWFuL2xpc3RpbmZvL3ZpcnR1YWxpemF0aW9u