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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH v2 06/24] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness
Date: Tue,  8 Dec 2020 12:01:00 -0600	[thread overview]
Message-ID: <20201208180118.157911-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20201208180118.157911-1-richard.henderson@linaro.org>

Adjust the interface to match what has been done to the
TCGv_i32 load/store functions.

This is less obvious, because at present the only user of
these functions, trans_VLDST_multiple, also wants to manipulate
the endianness to speed up loading multiple bytes.  Thus we
retain an "internal" interface which is identical to the
current gen_aa32_{ld,st}_i64 interface.

The "new" interface will gain users as we remove the legacy
interfaces, gen_aa32_ld64 and gen_aa32_st64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate.c          | 78 +++++++++++++++++++--------------
 target/arm/translate-neon.c.inc |  6 ++-
 2 files changed, 49 insertions(+), 35 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index ef9192cf6b..f6007c23a6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -916,6 +916,37 @@ static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
     tcg_temp_free(addr);
 }
 
+static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
+                                     TCGv_i32 a32, int index, MemOp opc)
+{
+    TCGv addr = gen_aa32_addr(s, a32, opc);
+
+    tcg_gen_qemu_ld_i64(val, addr, index, opc);
+
+    /* Not needed for user-mode BE32, where we use MO_BE instead.  */
+    if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
+        tcg_gen_rotri_i64(val, val, 32);
+    }
+    tcg_temp_free(addr);
+}
+
+static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
+                                     TCGv_i32 a32, int index, MemOp opc)
+{
+    TCGv addr = gen_aa32_addr(s, a32, opc);
+
+    /* Not needed for user-mode BE32, where we use MO_BE instead.  */
+    if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
+        TCGv_i64 tmp = tcg_temp_new_i64();
+        tcg_gen_rotri_i64(tmp, val, 32);
+        tcg_gen_qemu_st_i64(tmp, addr, index, opc);
+        tcg_temp_free_i64(tmp);
+    } else {
+        tcg_gen_qemu_st_i64(val, addr, index, opc);
+    }
+    tcg_temp_free(addr);
+}
+
 static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
                             int index, MemOp opc)
 {
@@ -928,6 +959,18 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
     gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc));
 }
 
+static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+                            int index, MemOp opc)
+{
+    gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc));
+}
+
+static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+                            int index, MemOp opc)
+{
+    gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc));
+}
+
 #define DO_GEN_LD(SUFF, OPC)                                            \
     static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
                                          TCGv_i32 a32, int index)       \
@@ -942,47 +985,16 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
         gen_aa32_st_i32(s, val, a32, index, OPC);                       \
     }
 
-static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
-                            int index, MemOp opc)
-{
-    TCGv addr = gen_aa32_addr(s, a32, opc);
-    tcg_gen_qemu_ld_i64(val, addr, index, opc);
-
-    /* Not needed for user-mode BE32, where we use MO_BE instead.  */
-    if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
-        tcg_gen_rotri_i64(val, val, 32);
-    }
-
-    tcg_temp_free(addr);
-}
-
 static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
                                  TCGv_i32 a32, int index)
 {
-    gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data);
-}
-
-static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
-                            int index, MemOp opc)
-{
-    TCGv addr = gen_aa32_addr(s, a32, opc);
-
-    /* Not needed for user-mode BE32, where we use MO_BE instead.  */
-    if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
-        TCGv_i64 tmp = tcg_temp_new_i64();
-        tcg_gen_rotri_i64(tmp, val, 32);
-        tcg_gen_qemu_st_i64(tmp, addr, index, opc);
-        tcg_temp_free_i64(tmp);
-    } else {
-        tcg_gen_qemu_st_i64(val, addr, index, opc);
-    }
-    tcg_temp_free(addr);
+    gen_aa32_ld_i64(s, val, a32, index, MO_Q);
 }
 
 static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
                                  TCGv_i32 a32, int index)
 {
-    gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);
+    gen_aa32_st_i64(s, val, a32, index, MO_Q);
 }
 
 DO_GEN_LD(8u, MO_UB)
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index c82aa1412e..18d9042130 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -494,11 +494,13 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
                 int tt = a->vd + reg + spacing * xs;
 
                 if (a->l) {
-                    gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
+                    gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx,
+                                             endian | size);
                     neon_store_element64(tt, n, size, tmp64);
                 } else {
                     neon_load_element64(tmp64, tt, n, size);
-                    gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
+                    gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx,
+                                             endian | size);
                 }
                 tcg_gen_add_i32(addr, addr, tmp);
             }
-- 
2.25.1



  parent reply	other threads:[~2020-12-08 18:09 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-08 18:00 [PATCH v2 00/24] target/arm: enforce alignment Richard Henderson
2020-12-08 18:00 ` [PATCH v2 01/24] target/arm: Fix decode of align in VLDST_single Richard Henderson
2020-12-08 18:00 ` [PATCH v2 02/24] target/arm: Add ALIGN_MEM to TBFLAG_ANY Richard Henderson
2021-01-07 15:42   ` Peter Maydell
2021-01-07 19:58     ` Richard Henderson
2020-12-08 18:00 ` [PATCH v2 03/24] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Richard Henderson
2021-01-07 15:51   ` Peter Maydell
2020-12-08 18:00 ` [PATCH v2 04/24] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Richard Henderson
2021-01-07 15:56   ` Peter Maydell
2020-12-08 18:00 ` [PATCH v2 05/24] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Richard Henderson
2021-01-07 16:00   ` Peter Maydell
2021-01-07 20:37     ` Richard Henderson
2020-12-08 18:01 ` Richard Henderson [this message]
2021-01-07 16:02   ` [PATCH v2 06/24] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Peter Maydell
2020-12-08 18:01 ` [PATCH v2 07/24] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
2021-01-07 16:08   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 08/24] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2021-01-07 16:09   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 09/24] target/arm: Enforce alignment for LDM/STM Richard Henderson
2021-01-07 16:10   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 10/24] target/arm: Enforce alignment for RFE Richard Henderson
2021-01-07 16:10   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 11/24] target/arm: Enforce alignment for SRS Richard Henderson
2021-01-07 16:10   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 12/24] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2021-01-07 16:13   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 13/24] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2021-01-07 16:14   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 14/24] target/arm: Enforce alignment for VLD1 (all lanes) Richard Henderson
2021-01-07 16:26   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 15/24] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2021-01-07 16:40   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 16/24] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2021-01-07 16:46   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 17/24] target/arm: Use finalize_memop for aa64 gpr load/store Richard Henderson
2021-01-07 17:30   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 18/24] target/arm: Use finalize_memop for aa64 fpr load/store Richard Henderson
2021-01-07 17:30   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 19/24] target/arm: Enforce alignment for aa64 load-acq/store-rel Richard Henderson
2021-01-07 17:32   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 20/24] target/arm: Use MemOp for size + endian in aa64 vector ld/st Richard Henderson
2021-01-07 17:32   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 21/24] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Richard Henderson
2021-01-07 17:35   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 22/24] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Richard Henderson
2021-01-07 17:36   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 23/24] target/arm: Enforce alignment for sve LD1R Richard Henderson
2021-01-07 17:37   ` Peter Maydell
2020-12-08 18:01 ` [PATCH v2 24/24] target/arm: Enforce alignment for sve unpredicated LDR/STR Richard Henderson
2021-01-07 17:39   ` Peter Maydell
2021-01-07 22:02     ` Richard Henderson
2021-01-08 17:22       ` Peter Maydell

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