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Wed, 9 Dec 2020 08:39:24 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 427EBA4057; Wed, 9 Dec 2020 08:39:22 +0000 (GMT) Received: from linux.vnet.ibm.com (unknown [9.126.150.29]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Wed, 9 Dec 2020 08:39:22 +0000 (GMT) Date: Wed, 9 Dec 2020 14:09:21 +0530 From: Srikar Dronamraju To: Gautham R Shenoy Cc: Anton Blanchard , Vaidyanathan Srinivasan , Michael Ellerman , Michael Neuling , Nicholas Piggin , Nathan Lynch , Peter Zijlstra , Valentin Schneider , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache Message-ID: <20201209083921.GL528281@linux.vnet.ibm.com> Reply-To: Srikar Dronamraju References: <1607057327-29822-1-git-send-email-ego@linux.vnet.ibm.com> <1607057327-29822-4-git-send-email-ego@linux.vnet.ibm.com> <20201207131138.GJ528281@linux.vnet.ibm.com> <20201208175647.GC14206@in.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <20201208175647.GC14206@in.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343,18.0.737 definitions=2020-12-09_07:2020-12-08,2020-12-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 priorityscore=1501 adultscore=0 mlxscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 suspectscore=1 impostorscore=0 clxscore=1015 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2012090056 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Gautham R Shenoy [2020-12-08 23:26:47]: > > The drawback of this is even if cpus 0,2,4,6 are released L1 cache will not > > be released. Is this as expected? > > cacheinfo populates the cache->shared_cpu_map on the basis of which > CPUs share the common device-tree node for a particular cache. There > is one l1-cache object in the device-tree for a CPU node corresponding > to a big-core. That the L1 is further split between the threads of the > core is shown using ibm,thread-groups. > Yes. > The ideal thing would be to add a "group_leader" field to "struct > cache" so that we can create separate cache objects , one per thread > group. I will take a stab at this in the v2. > I am not saying this needs to be done immediately. We could add a TODO and get it done later. Your patch is not making it worse. Its just that there is still something more left to be done. -- Thanks and Regards Srikar Dronamraju From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCC97C433FE for ; Wed, 9 Dec 2020 08:41:36 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09C7A23AA8 for ; Wed, 9 Dec 2020 08:41:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 09C7A23AA8 Authentication-Results: mail.kernel.org; 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Wed, 9 Dec 2020 03:39:29 -0500 Received: from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com [169.51.49.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 35afek9x2j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Dec 2020 03:39:28 -0500 Received: from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1]) by ppma03ams.nl.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 0B98Y8cE022565; Wed, 9 Dec 2020 08:39:26 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma03ams.nl.ibm.com with ESMTP id 3581u84cmt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 09 Dec 2020 08:39:26 +0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 0B98dOdi24576374 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 9 Dec 2020 08:39:24 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4470EA4051; Wed, 9 Dec 2020 08:39:24 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 427EBA4057; Wed, 9 Dec 2020 08:39:22 +0000 (GMT) Received: from linux.vnet.ibm.com (unknown [9.126.150.29]) by d06av23.portsmouth.uk.ibm.com (Postfix) with SMTP; Wed, 9 Dec 2020 08:39:22 +0000 (GMT) Date: Wed, 9 Dec 2020 14:09:21 +0530 From: Srikar Dronamraju To: Gautham R Shenoy Subject: Re: [PATCH 3/3] powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache Message-ID: <20201209083921.GL528281@linux.vnet.ibm.com> References: <1607057327-29822-1-git-send-email-ego@linux.vnet.ibm.com> <1607057327-29822-4-git-send-email-ego@linux.vnet.ibm.com> <20201207131138.GJ528281@linux.vnet.ibm.com> <20201208175647.GC14206@in.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <20201208175647.GC14206@in.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2020-12-09_07:2020-12-08, 2020-12-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 priorityscore=1501 adultscore=0 mlxscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 suspectscore=1 impostorscore=0 clxscore=1015 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2012090056 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Srikar Dronamraju Cc: Nathan Lynch , Michael Neuling , Vaidyanathan Srinivasan , Peter Zijlstra , linux-kernel@vger.kernel.org, Nicholas Piggin , linuxppc-dev@lists.ozlabs.org, Valentin Schneider Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" * Gautham R Shenoy [2020-12-08 23:26:47]: > > The drawback of this is even if cpus 0,2,4,6 are released L1 cache will not > > be released. Is this as expected? > > cacheinfo populates the cache->shared_cpu_map on the basis of which > CPUs share the common device-tree node for a particular cache. There > is one l1-cache object in the device-tree for a CPU node corresponding > to a big-core. That the L1 is further split between the threads of the > core is shown using ibm,thread-groups. > Yes. > The ideal thing would be to add a "group_leader" field to "struct > cache" so that we can create separate cache objects , one per thread > group. I will take a stab at this in the v2. > I am not saying this needs to be done immediately. We could add a TODO and get it done later. Your patch is not making it worse. Its just that there is still something more left to be done. -- Thanks and Regards Srikar Dronamraju