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Wed, 9 Dec 2020 09:07:17 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EB88513605D; Wed, 9 Dec 2020 09:07:16 +0000 (GMT) Received: from sofia.ibm.com (unknown [9.199.49.37]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 9 Dec 2020 09:07:16 +0000 (GMT) Received: by sofia.ibm.com (Postfix, from userid 1000) id C63D82E35A0; Wed, 9 Dec 2020 14:37:09 +0530 (IST) Date: Wed, 9 Dec 2020 14:37:09 +0530 From: Gautham R Shenoy To: Srikar Dronamraju Cc: Gautham R Shenoy , Anton Blanchard , Vaidyanathan Srinivasan , Michael Ellerman , Michael Neuling , Nicholas Piggin , Nathan Lynch , Peter Zijlstra , Valentin Schneider , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache Message-ID: <20201209090709.GB13125@in.ibm.com> Reply-To: ego@linux.vnet.ibm.com References: <1607057327-29822-1-git-send-email-ego@linux.vnet.ibm.com> <1607057327-29822-4-git-send-email-ego@linux.vnet.ibm.com> <20201207131138.GJ528281@linux.vnet.ibm.com> <20201208175647.GC14206@in.ibm.com> <20201209083921.GL528281@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201209083921.GL528281@linux.vnet.ibm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343,18.0.737 definitions=2020-12-09_07:2020-12-08,2020-12-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 mlxlogscore=999 adultscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2012090060 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 09, 2020 at 02:09:21PM +0530, Srikar Dronamraju wrote: > * Gautham R Shenoy [2020-12-08 23:26:47]: > > > > The drawback of this is even if cpus 0,2,4,6 are released L1 cache will not > > > be released. Is this as expected? > > > > cacheinfo populates the cache->shared_cpu_map on the basis of which > > CPUs share the common device-tree node for a particular cache. There > > is one l1-cache object in the device-tree for a CPU node corresponding > > to a big-core. That the L1 is further split between the threads of the > > core is shown using ibm,thread-groups. > > > > Yes. > > > The ideal thing would be to add a "group_leader" field to "struct > > cache" so that we can create separate cache objects , one per thread > > group. I will take a stab at this in the v2. > > > > I am not saying this needs to be done immediately. We could add a TODO and > get it done later. Your patch is not making it worse. Its just that there is > still something more left to be done. Yeah, it needs to be fixed but it may not be a 5.11 target. For now I will fix this patch to take care of the build errors on !PPC64 !SMT configs. I will post a separate series for making cacheinfo.c aware of thread-groups at the time of construction of the cache-chain. > > -- > Thanks and Regards > Srikar Dronamraju From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03BE3C4361B for ; Wed, 9 Dec 2020 09:09:18 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0BD2D23B40 for ; Wed, 9 Dec 2020 09:09:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0BD2D23B40 Authentication-Results: mail.kernel.org; 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Wed, 9 Dec 2020 09:07:17 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EB88513605D; Wed, 9 Dec 2020 09:07:16 +0000 (GMT) Received: from sofia.ibm.com (unknown [9.199.49.37]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 9 Dec 2020 09:07:16 +0000 (GMT) Received: by sofia.ibm.com (Postfix, from userid 1000) id C63D82E35A0; Wed, 9 Dec 2020 14:37:09 +0530 (IST) Date: Wed, 9 Dec 2020 14:37:09 +0530 From: Gautham R Shenoy To: Srikar Dronamraju Subject: Re: [PATCH 3/3] powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache Message-ID: <20201209090709.GB13125@in.ibm.com> References: <1607057327-29822-1-git-send-email-ego@linux.vnet.ibm.com> <1607057327-29822-4-git-send-email-ego@linux.vnet.ibm.com> <20201207131138.GJ528281@linux.vnet.ibm.com> <20201208175647.GC14206@in.ibm.com> <20201209083921.GL528281@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201209083921.GL528281@linux.vnet.ibm.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2020-12-09_07:2020-12-08, 2020-12-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 mlxlogscore=999 adultscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2012090060 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ego@linux.vnet.ibm.com Cc: Nathan Lynch , Gautham R Shenoy , Michael Neuling , Vaidyanathan Srinivasan , Peter Zijlstra , linux-kernel@vger.kernel.org, Nicholas Piggin , linuxppc-dev@lists.ozlabs.org, Valentin Schneider Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Wed, Dec 09, 2020 at 02:09:21PM +0530, Srikar Dronamraju wrote: > * Gautham R Shenoy [2020-12-08 23:26:47]: > > > > The drawback of this is even if cpus 0,2,4,6 are released L1 cache will not > > > be released. Is this as expected? > > > > cacheinfo populates the cache->shared_cpu_map on the basis of which > > CPUs share the common device-tree node for a particular cache. There > > is one l1-cache object in the device-tree for a CPU node corresponding > > to a big-core. That the L1 is further split between the threads of the > > core is shown using ibm,thread-groups. > > > > Yes. > > > The ideal thing would be to add a "group_leader" field to "struct > > cache" so that we can create separate cache objects , one per thread > > group. I will take a stab at this in the v2. > > > > I am not saying this needs to be done immediately. We could add a TODO and > get it done later. Your patch is not making it worse. Its just that there is > still something more left to be done. Yeah, it needs to be fixed but it may not be a 5.11 target. For now I will fix this patch to take care of the build errors on !PPC64 !SMT configs. I will post a separate series for making cacheinfo.c aware of thread-groups at the time of construction of the cache-chain. > > -- > Thanks and Regards > Srikar Dronamraju