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[79.176.44.197]) by smtp.gmail.com with ESMTPSA id a21sm4561894wmb.38.2020.12.09.10.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Dec 2020 10:07:44 -0800 (PST) Date: Wed, 9 Dec 2020 13:07:42 -0500 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Subject: [PULL v2 12/65] acpi/gpex: Build tables for pxb Message-ID: <20201209180546.721296-13-mst@redhat.com> References: <20201209180546.721296-1-mst@redhat.com> MIME-Version: 1.0 In-Reply-To: <20201209180546.721296-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=63.128.21.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jiahui Cen , Shannon Zhao , Yubo Miao , qemu-arm@nongnu.org, Igor Mammedov Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Yubo Miao The resources of pxbs are obtained by crs_build and the resources used by pxbs would be moved from the resources defined for host-bridge. The resources for pxb are composed of following two parts: 1. The bar space of the pci-bridge/pcie-root-port behined it 2. The config space of devices behind it. Signed-off-by: Yubo Miao Signed-off-by: Jiahui Cen Message-Id: <20201119014841.7298-6-cenjiahui@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/hw/pci-host/gpex.h | 1 + hw/arm/virt-acpi-build.c | 6 +++-- hw/pci-host/gpex-acpi.c | 54 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 2 deletions(-) diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index d52ea80d4e..d48a020a95 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -59,6 +59,7 @@ struct GPEXConfig { MemMapEntry mmio64; MemMapEntry pio; int irq; + PCIBus *bus; }; int gpex_set_irq_num(GPEXHost *s, int index, int gsi); diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9747a6458f..e0bed9037c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -153,7 +153,8 @@ static void acpi_dsdt_add_virtio(Aml *scope, } static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, - uint32_t irq, bool use_highmem, bool highmem_ecam) + uint32_t irq, bool use_highmem, bool highmem_ecam, + VirtMachineState *vms) { int ecam_id = VIRT_ECAM_ID(highmem_ecam); struct GPEXConfig cfg = { @@ -161,6 +162,7 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, .pio = memmap[VIRT_PCIE_PIO], .ecam = memmap[ecam_id], .irq = irq, + .bus = vms->bus, }; if (use_highmem) { @@ -609,7 +611,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), - vms->highmem, vms->highmem_ecam); + vms->highmem, vms->highmem_ecam, vms); if (vms->acpi_dev) { build_ged_aml(scope, "\\_SB."GED_DEVICE, HOTPLUG_HANDLER(vms->acpi_dev), diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 32a9f2796d..7f20ee1c98 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -1,6 +1,10 @@ #include "qemu/osdep.h" #include "hw/acpi/aml-build.h" #include "hw/pci-host/gpex.h" +#include "hw/arm/virt.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pcie_host.h" static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) { @@ -124,7 +128,57 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) { int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; Aml *method, *crs, *dev, *rbuf; + PCIBus *bus = cfg->bus; + CrsRangeSet crs_range_set; + /* start to construct the tables for pxb */ + crs_range_set_init(&crs_range_set); + if (bus) { + QLIST_FOREACH(bus, &bus->child, sibling) { + uint8_t bus_num = pci_bus_num(bus); + uint8_t numa_node = pci_bus_numa_node(bus); + + if (!pci_bus_is_root(bus)) { + continue; + } + + /* + * 0 - (nr_pcie_buses - 1) is the bus range for the main + * host-bridge and it equals the MIN of the + * busNr defined for pxb-pcie. + */ + if (bus_num < nr_pcie_buses) { + nr_pcie_buses = bus_num; + } + + dev = aml_device("PC%.02X", bus_num); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device"))); + if (numa_node != NUMA_NODE_UNASSIGNED) { + aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); + } + + acpi_dsdt_add_pci_route_table(dev, cfg->irq); + + /* + * Resources defined for PXBs are composed by the folling parts: + * 1. The resources the pci-brige/pcie-root-port need. + * 2. The resources the devices behind pxb need. + */ + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); + aml_append(dev, aml_name_decl("_CRS", crs)); + + acpi_dsdt_add_pci_osc(dev); + + aml_append(scope, dev); + } + } + crs_range_set_free(&crs_range_set); + + /* tables for the main */ dev = aml_device("%s", "PCI0"); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); -- MST