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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "Huang, Sean Z" <sean.z.huang@intel.com>
Cc: Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time
Date: Wed, 9 Dec 2020 10:07:59 -0800	[thread overview]
Message-ID: <20201209180759.GB3405@intel.com> (raw)
In-Reply-To: <20201209070307.2304-3-sean.z.huang@intel.com>

On Tue, Dec 08, 2020 at 11:02:56PM -0800, Huang, Sean Z wrote:
> Set the KCR init during the boot time, which is
> required by hardware, to allow us doing further
> protection operation such as sending commands to
> GPU or TEE.
> 
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> ---
>  drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
>  drivers/gpu/drm/i915/pxp/intel_pxp.h | 6 ++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index ba43b2c923c7..c4815950567d 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,12 @@
>  #include "intel_pxp.h"
>  #include "intel_pxp_context.h"
>  
> +/* KCR register definitions */
> +#define KCR_INIT            _MMIO(0x320f0)
> +#define KCR_INIT_MASK_SHIFT (16)
> +/* Setting KCR Init bit is required after system boot */
> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
> +
>  int intel_pxp_init(struct intel_pxp *pxp)
>  {
>  	struct intel_gt *gt = container_of(pxp, struct intel_gt, pxp);
> @@ -16,6 +22,8 @@ int intel_pxp_init(struct intel_pxp *pxp)
>  
>  	intel_pxp_ctx_init(&pxp->ctx);
>  
> +	intel_uncore_write(gt->uncore, KCR_INIT, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
> +
>  	drm_info(&gt->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 7c3d49a6a3ab..b906bf7dea90 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -15,6 +15,7 @@ struct intel_pxp {
>  #ifdef CONFIG_DRM_I915_PXP
>  int intel_pxp_init(struct intel_pxp *pxp);
>  void intel_pxp_uninit(struct intel_pxp *pxp);
> +int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval);
>  #else
>  static inline int intel_pxp_init(struct intel_pxp *pxp)
>  {
> @@ -24,6 +25,11 @@ static inline int intel_pxp_init(struct intel_pxp *pxp)
>  static inline void intel_pxp_uninit(struct intel_pxp *pxp)
>  {
>  }
> +
> +static inline int intel_pxp_reg_read(struct intel_pxp *pxp, u32 offset, u32 *regval)
> +{
> +	return 0;
> +}

I'm wondering if some other patch in this series will explain the need for this,
but as is right now, this shouldn't be here on this patch... and maybe not even at all.
Let's minimize the wraps and use the already provided read/write functions.

>  #endif
>  
>  #endif /* __INTEL_PXP_PM_H__ */
> -- 
> 2.17.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2020-12-09 18:08 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-09  7:02 [Intel-gfx] [RFC-v3 00/13] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2020-12-09  7:02 ` [Intel-gfx] [RFC-v3 01/13] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
2020-12-09 18:05   ` Rodrigo Vivi
2020-12-09 18:42     ` Huang, Sean Z
2020-12-10  9:36   ` Joonas Lahtinen
2020-12-10 16:53   ` Jani Nikula
2020-12-09  7:02 ` [Intel-gfx] [RFC-v3 02/13] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
2020-12-09 18:07   ` Rodrigo Vivi [this message]
2020-12-09 18:48     ` Huang, Sean Z
2020-12-10 16:55   ` Jani Nikula
2020-12-09  7:02 ` [Intel-gfx] [RFC-v3 03/13] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
2020-12-10 10:12   ` Joonas Lahtinen
2020-12-10 17:00   ` Jani Nikula
2020-12-09  7:02 ` [Intel-gfx] [RFC-v3 04/13] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
2020-12-09  9:58   ` kernel test robot
2020-12-10 10:42   ` Joonas Lahtinen
2020-12-09  7:02 ` [Intel-gfx] [RFC-v3 05/13] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
2020-12-10 10:47   ` Joonas Lahtinen
2020-12-10 17:05   ` Jani Nikula
2020-12-09  7:03 ` [Intel-gfx] [RFC-v3 06/13] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
2020-12-10 11:02   ` Joonas Lahtinen
2020-12-10 17:06   ` Jani Nikula
2020-12-09  7:03 ` [Intel-gfx] [RFC-v3 07/13] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
2020-12-10 10:51   ` Joonas Lahtinen
2020-12-09  7:03 ` [Intel-gfx] [RFC-v3 08/13] drm/i915/pxp: Enable PXP power management Huang, Sean Z
2020-12-09  7:03 ` [Intel-gfx] [RFC-v3 09/13] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
2020-12-09  7:03 ` [Intel-gfx] [RFC-v3 10/13] mei: pxp: export pavp client to me client bus Huang, Sean Z
2020-12-09  7:03 ` [Intel-gfx] [RFC-v3 11/13] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
2020-12-10  9:13   ` Joonas Lahtinen
2020-12-09  7:03 ` [Intel-gfx] [RFC-v3 12/13] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
2020-12-09  7:03 ` [Intel-gfx] [RFC-v3 13/13] drm/i915/pxp: Add plane decryption support Huang, Sean Z
2020-12-09  7:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session (rev3) Patchwork
2020-12-09  7:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-09  9:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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