* [PATCH v11 00/25] i386 cleanup PART 1
@ 2020-12-11 8:31 Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 01/25] accel/tcg: split CpusAccel into three TCG variants Claudio Fontana
` (26 more replies)
0 siblings, 27 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Jason Wang, Marcelo Tosatti, qemu-devel, Peter Xu,
Dario Faggioli, Cameron Esfahani, haxm-team, Claudio Fontana,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Colin Xu
Hello, this is version 11 of the cleanup.
The series has been split into two separate parts,
and this is PART 1.
v10 -> v11: small tweaks for !CONFIG_USER_ONLY
* make transaction_failed and do_unaligned_access
consistently !CONFIG_USER_ONLY.
* hw/mips/jazz: wrap mips_jazz_do_transaction_failed in
CONFIG_TCG && !CONFIG_USER_ONLY
* arm: wrap arm_cpu_synchronize_from_tb in CONFIG_TCG
* arm: wrap arm_v7m_exec_interrupt in CONFIG_TCG
* mips: wrap mips_cpu_synchronize_from_tb in CONFIG_TCG
* mips: do not make mips_cpu_do_interrupt !CONFIG_USER_ONLY
* ppc: protect cpu_exec_enter/exit in CONFIG_TCG
v9 -> v10: minor tweaks and fixes
* in "i386: split cpu accelerators from cpu.c",
use kvm/kvm-cpu.c, hvf/hvf-cpu.c, tcg/tcg-cpu.c.
Easier to understand compared to editing multiple cpu.c files,
and matches the header files if needed (kvm-cpu.h).
* in "accel: replace struct CpusAccel with AccelOpsClass",
make it a bit more consistent, by naming the files defining
the AccelOpsClass types "...-accel-ops.c" instead of the old
naming "...-cpus.c".
* in "cpu: move cc->transaction_failed to tcg_ops",
protect with CONFIG_TCG the use of tcg_ops for hw/misc/jazz.c,
#include "exec/memattrs.h" (Philippe, Eduardo)
* in "cpu: Move synchronize_from_tb() to tcg_ops",
#include "hw/core/cpu.h" (Philippe, Eduardo)
do not remove the comment about struct TcgCpuOperations (Philippe)
* in "accel/tcg: split TCG-only code from cpu_exec_realizefn",
invert tcg_target_initialized set order (Alex)
* in "i386: move TCG cpu class initialization out of helper.c",
extract helper-tcg.h, tcg-cpu.c, and tcg-cpu.h directly into
tcg/, avoiding the extra move later to tcg/ (Alex)
v8 -> v9: move additional methods to CPUClass->tcg_ops
do_unaligned_access, transaction_failed and do_interrupt.
do_interrupt is a bit tricky, as the same code is reused
(albeit not usually directly) for KVM under certain odd conditions.
Change arm, as the only user of do_interrupt callback for KVM,
to instead call the target function directly arm_do_interrupt.
v7 -> v8: add missing CONFIG_TCGs, fix bugs
* add the prerequisite patches for "3 tcg" at the beginning of the
series for convenience (already reviewed, queued by RH).
* add CONFIG_TCG to TCGCpuOperations and tcg_ops variable use
* reduce the scope of the realizefn refactoring, do not
introduce a separate cpu_accel_realize, and instead use the
existing cpu_exec_realizefn, there is not enough benefit
to introduce a new function.
* fix bugs in user mode due to attempt to move the tcg_region_init()
early, so it could be done just once in tcg_init() for both
softmmu and user mode. Unfortunately it needs to remain deferred
for user mode, as it needs to be done after prologue init and
after the GUEST_BASE has been set.
v6 -> v7: integrate TCGCpuOperations, refactored cpu_exec_realizefn
* integrate TCGCpuOperations (Eduardo)
Taken some refactoring from Eduardo for Tcg-only operations on
CPUClass.
* refactored cpu_exec_realizefn
The other main change is a refactoring of cpu_exec_realizefn,
directly linked to the effort of making many cpu_exec operations
TCG-only (Eduardo series above):
cpu_exec_realizefn is actually a TCG-only thing, with the
exception of a couple things that can be done in base cpu code.
This changes all targets realizefn, so I guess I have to Cc:
the Multiverse? (Universe was already CCed for all accelerators).
v5 -> v6: remove MODULE_INIT_ACCEL_CPU
instead, use a call to accel_init_interfaces().
* The class lookups are now general and performed in accel/
new AccelCPUClass for new archs are supported as new
ones appear in the class hierarchy, no need for stubs.
* Split the code a bit better
v4 -> v5: centralized and simplified initializations
I put in Cc: Emilio G. Cota, specifically because in patch 8
I (re)moved for user-mode the call to tcg_regions_init().
The call happens now inside the tcg AccelClass machine_init,
(so earlier). This seems to work fine, but thought to get the
author opinion on this.
Rebased on "tcg-cpus: split into 3 tcg variants" series
(queued by Richard), to avoid some code churn:
https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg04356.html
* Extended AccelClass to user-mode.
user-mode now does not call tcg_exec_init directly,
instead it uses the tcg accel class, and its init_machine method.
Since user-mode does not define or use a machine state,
the machine is just passed as NULL.
The immediate advantage is that now we can call current_accel()
from both user mode and softmmu, so we can work out the correct
class to use for accelerator initializations.
* QOMification of CpusAccelOps
simple QOMification of CpusAccelOps abstract class.
* Centralized all accel_cpu_init, so only one per cpu-arch,
plus one for all accels will remain.
So we can expect accel_cpu_init() to be limited to:
softmmu/cpus.c - initializes the chosen softmmu accel ops for the cpus module.
target/ARCH/cpu.c - initializes the chosen arch-specific cpu accelerator.
These changes are meant to address concerns/issues (Paolo):
1) the use of if (tcg_enabled()) and similar in the module_init call path
2) the excessive number of accel_cpu_init() to hunt down in the codebase.
* Fixed wrong use of host_cpu_class_init (Eduardo)
v3 -> v4: QOMification of X86CPUAccelClass
In this version I basically QOMified X86CPUAccel, taking the
suggestions from Eduardo as the starting point,
but stopping just short of making it an actual QOM interface,
using a plain abstract class, and then subclasses for the
actual objects.
Initialization is still using the existing qemu initialization
framework (module_call_init), which is I still think is better
than the alternatives proposed, in the current state.
Possibly some improvements could be developed in the future here.
In this case, effort should be put in keeping things extendible,
in order not to be blocked once accelerators also become modules.
Motivation and higher level steps:
https://lists.gnu.org/archive/html/qemu-devel/2020-05/msg04628.html
Looking forward to your comments on this proposal,
Ciao,
Claudio
Claudio Fontana (16):
accel/tcg: split CpusAccel into three TCG variants
accel/tcg: split tcg_start_vcpu_thread
accel/tcg: rename tcg-cpus functions to match module name
i386: move kvm accel files into kvm/
i386: move whpx accel files into whpx/
i386: move hax accel files into hax/
i386: hvf: remove stale MAINTAINERS entry for old hvf stubs
i386: move TCG accel files into tcg/
i386: move cpu dump out of helper.c into cpu-dump.c
i386: move TCG cpu class initialization out of helper.c
target/riscv: remove CONFIG_TCG, as it is always TCG
accel/tcg: split TCG-only code from cpu_exec_realizefn
target/arm: do not use cc->do_interrupt for KVM directly
cpu: move cc->do_interrupt to tcg_ops
cpu: move cc->transaction_failed to tcg_ops
cpu: move do_unaligned_access to tcg_ops
Eduardo Habkost (9):
tcg: cpu_exec_{enter,exit} helpers
tcg: make CPUClass.cpu_exec_* optional
tcg: Make CPUClass.debug_excp_handler optional
cpu: Remove unnecessary noop methods
cpu: Introduce TCGCpuOperations struct
cpu: Move synchronize_from_tb() to tcg_ops
cpu: Move cpu_exec_* to tcg_ops
cpu: Move tlb_fill to tcg_ops
cpu: Move debug_excp_handler to tcg_ops
meson.build | 1 +
accel/tcg/tcg-cpus-icount.h | 17 +
accel/tcg/tcg-cpus-rr.h | 21 +
accel/tcg/tcg-cpus.h | 12 +-
include/hw/core/cpu.h | 73 ++--
include/hw/core/tcg-cpu-ops.h | 81 ++++
target/i386/cpu.h | 100 +----
target/i386/{ => hax}/hax-cpus.h | 0
target/i386/{ => hax}/hax-i386.h | 6 +-
target/i386/{ => hax}/hax-interface.h | 0
target/i386/{ => hax}/hax-posix.h | 0
target/i386/{ => hax}/hax-windows.h | 0
target/i386/{ => kvm}/hyperv-proto.h | 0
target/i386/{ => kvm}/hyperv.h | 0
target/i386/{ => kvm}/kvm_i386.h | 0
target/i386/kvm/trace.h | 1 +
target/i386/tcg/helper-tcg.h | 112 ++++++
target/i386/tcg/tcg-cpu.h | 15 +
target/i386/{ => whpx}/whp-dispatch.h | 0
target/i386/{ => whpx}/whpx-cpus.h | 0
accel/tcg/cpu-exec.c | 70 +++-
accel/tcg/cputlb.c | 6 +-
accel/tcg/tcg-all.c | 13 +-
accel/tcg/tcg-cpus-icount.c | 147 +++++++
accel/tcg/tcg-cpus-mttcg.c | 140 +++++++
accel/tcg/tcg-cpus-rr.c | 305 +++++++++++++++
accel/tcg/tcg-cpus.c | 504 +-----------------------
accel/tcg/user-exec.c | 6 +-
cpu.c | 66 ++--
hw/core/cpu.c | 19 +-
hw/i386/fw_cfg.c | 2 +-
hw/i386/intel_iommu.c | 2 +-
hw/i386/kvm/apic.c | 2 +-
hw/i386/kvm/clock.c | 2 +-
hw/i386/microvm.c | 2 +-
hw/i386/pc.c | 2 +-
hw/i386/x86.c | 2 +-
hw/mips/jazz.c | 9 +-
softmmu/icount.c | 2 +-
target/alpha/cpu.c | 12 +-
target/arm/cpu.c | 22 +-
target/arm/cpu64.c | 5 +-
target/arm/cpu_tcg.c | 10 +-
target/arm/helper.c | 4 +
target/arm/kvm64.c | 6 +-
target/avr/cpu.c | 10 +-
target/avr/helper.c | 4 +-
target/cris/cpu.c | 28 +-
target/cris/helper.c | 4 +-
target/hppa/cpu.c | 14 +-
target/i386/cpu-dump.c | 537 +++++++++++++++++++++++++
target/i386/cpu.c | 35 +-
target/i386/{ => hax}/hax-all.c | 0
target/i386/{ => hax}/hax-cpus.c | 0
target/i386/{ => hax}/hax-mem.c | 0
target/i386/{ => hax}/hax-posix.c | 0
target/i386/{ => hax}/hax-windows.c | 0
target/i386/helper.c | 539 +-------------------------
target/i386/{ => kvm}/hyperv-stub.c | 0
target/i386/{ => kvm}/hyperv.c | 0
target/i386/{ => kvm}/kvm-stub.c | 0
target/i386/{ => kvm}/kvm.c | 0
target/i386/machine.c | 4 +-
target/i386/{ => tcg}/bpt_helper.c | 1 +
target/i386/{ => tcg}/cc_helper.c | 1 +
target/i386/{ => tcg}/excp_helper.c | 1 +
target/i386/{ => tcg}/fpu_helper.c | 33 +-
target/i386/{ => tcg}/int_helper.c | 1 +
target/i386/{ => tcg}/mem_helper.c | 1 +
target/i386/{ => tcg}/misc_helper.c | 1 +
target/i386/{ => tcg}/mpx_helper.c | 1 +
target/i386/{ => tcg}/seg_helper.c | 1 +
target/i386/{ => tcg}/smm_helper.c | 2 +
target/i386/{ => tcg}/svm_helper.c | 1 +
target/i386/tcg/tcg-cpu.c | 71 ++++
target/i386/{ => tcg}/tcg-stub.c | 0
target/i386/{ => tcg}/translate.c | 1 +
target/i386/{ => whpx}/whpx-all.c | 0
target/i386/{ => whpx}/whpx-cpus.c | 0
target/lm32/cpu.c | 10 +-
target/m68k/cpu.c | 10 +-
target/microblaze/cpu.c | 14 +-
target/mips/cpu.c | 21 +-
target/moxie/cpu.c | 6 +-
target/nios2/cpu.c | 10 +-
target/openrisc/cpu.c | 8 +-
target/riscv/cpu.c | 17 +-
target/riscv/cpu_helper.c | 2 +-
target/rx/cpu.c | 10 +-
target/s390x/cpu.c | 12 +-
target/s390x/excp_helper.c | 2 +-
target/sh4/cpu.c | 12 +-
target/sparc/cpu.c | 14 +-
target/tilegx/cpu.c | 8 +-
target/tricore/cpu.c | 6 +-
target/unicore32/cpu.c | 8 +-
target/xtensa/cpu.c | 14 +-
target/xtensa/helper.c | 4 +-
MAINTAINERS | 11 +-
accel/tcg/meson.build | 9 +-
target/i386/hax/meson.build | 7 +
target/i386/kvm/meson.build | 3 +
target/i386/kvm/trace-events | 7 +
target/i386/meson.build | 32 +-
target/i386/tcg/meson.build | 14 +
target/i386/trace-events | 6 -
target/i386/whpx/meson.build | 4 +
target/ppc/translate_init.c.inc | 24 +-
108 files changed, 1901 insertions(+), 1494 deletions(-)
create mode 100644 accel/tcg/tcg-cpus-icount.h
create mode 100644 accel/tcg/tcg-cpus-rr.h
create mode 100644 include/hw/core/tcg-cpu-ops.h
rename target/i386/{ => hax}/hax-cpus.h (100%)
rename target/i386/{ => hax}/hax-i386.h (95%)
rename target/i386/{ => hax}/hax-interface.h (100%)
rename target/i386/{ => hax}/hax-posix.h (100%)
rename target/i386/{ => hax}/hax-windows.h (100%)
rename target/i386/{ => kvm}/hyperv-proto.h (100%)
rename target/i386/{ => kvm}/hyperv.h (100%)
rename target/i386/{ => kvm}/kvm_i386.h (100%)
create mode 100644 target/i386/kvm/trace.h
create mode 100644 target/i386/tcg/helper-tcg.h
create mode 100644 target/i386/tcg/tcg-cpu.h
rename target/i386/{ => whpx}/whp-dispatch.h (100%)
rename target/i386/{ => whpx}/whpx-cpus.h (100%)
create mode 100644 accel/tcg/tcg-cpus-icount.c
create mode 100644 accel/tcg/tcg-cpus-mttcg.c
create mode 100644 accel/tcg/tcg-cpus-rr.c
create mode 100644 target/i386/cpu-dump.c
rename target/i386/{ => hax}/hax-all.c (100%)
rename target/i386/{ => hax}/hax-cpus.c (100%)
rename target/i386/{ => hax}/hax-mem.c (100%)
rename target/i386/{ => hax}/hax-posix.c (100%)
rename target/i386/{ => hax}/hax-windows.c (100%)
rename target/i386/{ => kvm}/hyperv-stub.c (100%)
rename target/i386/{ => kvm}/hyperv.c (100%)
rename target/i386/{ => kvm}/kvm-stub.c (100%)
rename target/i386/{ => kvm}/kvm.c (100%)
rename target/i386/{ => tcg}/bpt_helper.c (99%)
rename target/i386/{ => tcg}/cc_helper.c (99%)
rename target/i386/{ => tcg}/excp_helper.c (99%)
rename target/i386/{ => tcg}/fpu_helper.c (99%)
rename target/i386/{ => tcg}/int_helper.c (99%)
rename target/i386/{ => tcg}/mem_helper.c (99%)
rename target/i386/{ => tcg}/misc_helper.c (99%)
rename target/i386/{ => tcg}/mpx_helper.c (99%)
rename target/i386/{ => tcg}/seg_helper.c (99%)
rename target/i386/{ => tcg}/smm_helper.c (99%)
rename target/i386/{ => tcg}/svm_helper.c (99%)
create mode 100644 target/i386/tcg/tcg-cpu.c
rename target/i386/{ => tcg}/tcg-stub.c (100%)
rename target/i386/{ => tcg}/translate.c (99%)
rename target/i386/{ => whpx}/whpx-all.c (100%)
rename target/i386/{ => whpx}/whpx-cpus.c (100%)
create mode 100644 target/i386/hax/meson.build
create mode 100644 target/i386/kvm/meson.build
create mode 100644 target/i386/kvm/trace-events
create mode 100644 target/i386/tcg/meson.build
create mode 100644 target/i386/whpx/meson.build
--
2.26.2
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v11 01/25] accel/tcg: split CpusAccel into three TCG variants
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 02/25] accel/tcg: split tcg_start_vcpu_thread Claudio Fontana
` (25 subsequent siblings)
26 siblings, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Philippe Mathieu-Daudé,
Eduardo Habkost, Paul Durrant, Jason Wang, Marcelo Tosatti,
qemu-devel, Peter Xu, Dario Faggioli, Cameron Esfahani,
haxm-team, Claudio Fontana, Anthony Perard, Bruce Rogers,
Olaf Hering, Emilio G . Cota, Colin Xu
split up the CpusAccel tcg_cpus into three TCG variants:
tcg_cpus_rr (single threaded, round robin cpus)
tcg_cpus_icount (same as rr, but with instruction counting enabled)
tcg_cpus_mttcg (multi-threaded cpus)
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
accel/tcg/tcg-cpus-icount.h | 17 ++
accel/tcg/tcg-cpus-mttcg.h | 21 ++
accel/tcg/tcg-cpus-rr.h | 20 ++
accel/tcg/tcg-cpus.h | 13 +-
accel/tcg/tcg-all.c | 8 +-
accel/tcg/tcg-cpus-icount.c | 147 +++++++++++
accel/tcg/tcg-cpus-mttcg.c | 117 +++++++++
accel/tcg/tcg-cpus-rr.c | 270 ++++++++++++++++++++
accel/tcg/tcg-cpus.c | 484 ++----------------------------------
softmmu/icount.c | 2 +-
accel/tcg/meson.build | 9 +-
11 files changed, 646 insertions(+), 462 deletions(-)
create mode 100644 accel/tcg/tcg-cpus-icount.h
create mode 100644 accel/tcg/tcg-cpus-mttcg.h
create mode 100644 accel/tcg/tcg-cpus-rr.h
create mode 100644 accel/tcg/tcg-cpus-icount.c
create mode 100644 accel/tcg/tcg-cpus-mttcg.c
create mode 100644 accel/tcg/tcg-cpus-rr.c
diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h
new file mode 100644
index 0000000000..cbcf76b413
--- /dev/null
+++ b/accel/tcg/tcg-cpus-icount.h
@@ -0,0 +1,17 @@
+/*
+ * QEMU TCG Single Threaded vCPUs implementation using instruction counting
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TCG_CPUS_ICOUNT_H
+#define TCG_CPUS_ICOUNT_H
+
+void handle_icount_deadline(void);
+void prepare_icount_for_run(CPUState *cpu);
+void process_icount_data(CPUState *cpu);
+
+#endif /* TCG_CPUS_ICOUNT_H */
diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h
new file mode 100644
index 0000000000..d1bd771f49
--- /dev/null
+++ b/accel/tcg/tcg-cpus-mttcg.h
@@ -0,0 +1,21 @@
+/*
+ * QEMU TCG Multi Threaded vCPUs implementation
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TCG_CPUS_MTTCG_H
+#define TCG_CPUS_MTTCG_H
+
+/*
+ * In the multi-threaded case each vCPU has its own thread. The TLS
+ * variable current_cpu can be used deep in the code to find the
+ * current CPUState for a given thread.
+ */
+
+void *tcg_cpu_thread_fn(void *arg);
+
+#endif /* TCG_CPUS_MTTCG_H */
diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h
new file mode 100644
index 0000000000..1936fd16ab
--- /dev/null
+++ b/accel/tcg/tcg-cpus-rr.h
@@ -0,0 +1,20 @@
+/*
+ * QEMU TCG Single Threaded vCPUs implementation
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TCG_CPUS_RR_H
+#define TCG_CPUS_RR_H
+
+#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
+
+/* Kick all RR vCPUs. */
+void qemu_cpu_kick_rr_cpus(CPUState *unused);
+
+void *tcg_rr_cpu_thread_fn(void *arg);
+
+#endif /* TCG_CPUS_RR_H */
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h
index 8b1d9d2abc..279ba72e1f 100644
--- a/accel/tcg/tcg-cpus.h
+++ b/accel/tcg/tcg-cpus.h
@@ -1,5 +1,7 @@
/*
- * Accelerator CPUS Interface
+ * QEMU TCG vCPU common functionality
+ *
+ * Functionality common to all TCG vcpu variants: mttcg, rr and icount.
*
* Copyright 2020 SUSE LLC
*
@@ -12,6 +14,13 @@
#include "sysemu/cpus.h"
-extern const CpusAccel tcg_cpus;
+extern const CpusAccel tcg_cpus_mttcg;
+extern const CpusAccel tcg_cpus_icount;
+extern const CpusAccel tcg_cpus_rr;
+
+void tcg_start_vcpu_thread(CPUState *cpu);
+void qemu_tcg_destroy_vcpu(CPUState *cpu);
+int tcg_cpu_exec(CPUState *cpu);
+void tcg_handle_interrupt(CPUState *cpu, int mask);
#endif /* TCG_CPUS_H */
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index fa1208158f..e42a028043 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -104,8 +104,14 @@ static int tcg_init(MachineState *ms)
tcg_exec_init(s->tb_size * 1024 * 1024);
mttcg_enabled = s->mttcg_enabled;
- cpus_register_accel(&tcg_cpus);
+ if (mttcg_enabled) {
+ cpus_register_accel(&tcg_cpus_mttcg);
+ } else if (icount_enabled()) {
+ cpus_register_accel(&tcg_cpus_icount);
+ } else {
+ cpus_register_accel(&tcg_cpus_rr);
+ }
return 0;
}
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c
new file mode 100644
index 0000000000..d3af3afb6d
--- /dev/null
+++ b/accel/tcg/tcg-cpus-icount.c
@@ -0,0 +1,147 @@
+/*
+ * QEMU TCG Single Threaded vCPUs implementation using instruction counting
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2014 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "sysemu/tcg.h"
+#include "sysemu/replay.h"
+#include "qemu/main-loop.h"
+#include "qemu/guest-random.h"
+#include "exec/exec-all.h"
+#include "hw/boards.h"
+
+#include "tcg-cpus.h"
+#include "tcg-cpus-icount.h"
+#include "tcg-cpus-rr.h"
+
+static int64_t tcg_get_icount_limit(void)
+{
+ int64_t deadline;
+
+ if (replay_mode != REPLAY_MODE_PLAY) {
+ /*
+ * Include all the timers, because they may need an attention.
+ * Too long CPU execution may create unnecessary delay in UI.
+ */
+ deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
+ QEMU_TIMER_ATTR_ALL);
+ /* Check realtime timers, because they help with input processing */
+ deadline = qemu_soonest_timeout(deadline,
+ qemu_clock_deadline_ns_all(QEMU_CLOCK_REALTIME,
+ QEMU_TIMER_ATTR_ALL));
+
+ /*
+ * Maintain prior (possibly buggy) behaviour where if no deadline
+ * was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more than
+ * INT32_MAX nanoseconds ahead, we still use INT32_MAX
+ * nanoseconds.
+ */
+ if ((deadline < 0) || (deadline > INT32_MAX)) {
+ deadline = INT32_MAX;
+ }
+
+ return icount_round(deadline);
+ } else {
+ return replay_get_instructions();
+ }
+}
+
+static void notify_aio_contexts(void)
+{
+ /* Wake up other AioContexts. */
+ qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
+ qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL);
+}
+
+void handle_icount_deadline(void)
+{
+ assert(qemu_in_vcpu_thread());
+ int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
+ QEMU_TIMER_ATTR_ALL);
+
+ if (deadline == 0) {
+ notify_aio_contexts();
+ }
+}
+
+void prepare_icount_for_run(CPUState *cpu)
+{
+ int insns_left;
+
+ /*
+ * These should always be cleared by process_icount_data after
+ * each vCPU execution. However u16.high can be raised
+ * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
+ */
+ g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
+ g_assert(cpu->icount_extra == 0);
+
+ cpu->icount_budget = tcg_get_icount_limit();
+ insns_left = MIN(0xffff, cpu->icount_budget);
+ cpu_neg(cpu)->icount_decr.u16.low = insns_left;
+ cpu->icount_extra = cpu->icount_budget - insns_left;
+
+ replay_mutex_lock();
+
+ if (cpu->icount_budget == 0 && replay_has_checkpoint()) {
+ notify_aio_contexts();
+ }
+}
+
+void process_icount_data(CPUState *cpu)
+{
+ /* Account for executed instructions */
+ icount_update(cpu);
+
+ /* Reset the counters */
+ cpu_neg(cpu)->icount_decr.u16.low = 0;
+ cpu->icount_extra = 0;
+ cpu->icount_budget = 0;
+
+ replay_account_executed_instructions();
+
+ replay_mutex_unlock();
+}
+
+static void icount_handle_interrupt(CPUState *cpu, int mask)
+{
+ int old_mask = cpu->interrupt_request;
+
+ tcg_handle_interrupt(cpu, mask);
+ if (qemu_cpu_is_self(cpu) &&
+ !cpu->can_do_io
+ && (mask & ~old_mask) != 0) {
+ cpu_abort(cpu, "Raised interrupt while not in I/O function");
+ }
+}
+
+const CpusAccel tcg_cpus_icount = {
+ .create_vcpu_thread = tcg_start_vcpu_thread,
+ .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
+
+ .handle_interrupt = icount_handle_interrupt,
+ .get_virtual_clock = icount_get,
+ .get_elapsed_ticks = icount_get,
+};
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c
new file mode 100644
index 0000000000..dac724fc85
--- /dev/null
+++ b/accel/tcg/tcg-cpus-mttcg.c
@@ -0,0 +1,117 @@
+/*
+ * QEMU TCG Multi Threaded vCPUs implementation
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2014 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "sysemu/tcg.h"
+#include "sysemu/replay.h"
+#include "qemu/main-loop.h"
+#include "qemu/guest-random.h"
+#include "exec/exec-all.h"
+#include "hw/boards.h"
+
+#include "tcg-cpus.h"
+#include "tcg-cpus-mttcg.h"
+
+/*
+ * In the multi-threaded case each vCPU has its own thread. The TLS
+ * variable current_cpu can be used deep in the code to find the
+ * current CPUState for a given thread.
+ */
+
+void *tcg_cpu_thread_fn(void *arg)
+{
+ CPUState *cpu = arg;
+
+ assert(tcg_enabled());
+ g_assert(!icount_enabled());
+
+ rcu_register_thread();
+ tcg_register_thread();
+
+ qemu_mutex_lock_iothread();
+ qemu_thread_get_self(cpu->thread);
+
+ cpu->thread_id = qemu_get_thread_id();
+ cpu->can_do_io = 1;
+ current_cpu = cpu;
+ cpu_thread_signal_created(cpu);
+ qemu_guest_random_seed_thread_part2(cpu->random_seed);
+
+ /* process any pending work */
+ cpu->exit_request = 1;
+
+ do {
+ if (cpu_can_run(cpu)) {
+ int r;
+ qemu_mutex_unlock_iothread();
+ r = tcg_cpu_exec(cpu);
+ qemu_mutex_lock_iothread();
+ switch (r) {
+ case EXCP_DEBUG:
+ cpu_handle_guest_debug(cpu);
+ break;
+ case EXCP_HALTED:
+ /*
+ * during start-up the vCPU is reset and the thread is
+ * kicked several times. If we don't ensure we go back
+ * to sleep in the halted state we won't cleanly
+ * start-up when the vCPU is enabled.
+ *
+ * cpu->halted should ensure we sleep in wait_io_event
+ */
+ g_assert(cpu->halted);
+ break;
+ case EXCP_ATOMIC:
+ qemu_mutex_unlock_iothread();
+ cpu_exec_step_atomic(cpu);
+ qemu_mutex_lock_iothread();
+ default:
+ /* Ignore everything else? */
+ break;
+ }
+ }
+
+ qatomic_mb_set(&cpu->exit_request, 0);
+ qemu_wait_io_event(cpu);
+ } while (!cpu->unplug || cpu_can_run(cpu));
+
+ qemu_tcg_destroy_vcpu(cpu);
+ qemu_mutex_unlock_iothread();
+ rcu_unregister_thread();
+ return NULL;
+}
+
+static void mttcg_kick_vcpu_thread(CPUState *cpu)
+{
+ cpu_exit(cpu);
+}
+
+const CpusAccel tcg_cpus_mttcg = {
+ .create_vcpu_thread = tcg_start_vcpu_thread,
+ .kick_vcpu_thread = mttcg_kick_vcpu_thread,
+
+ .handle_interrupt = tcg_handle_interrupt,
+};
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c
new file mode 100644
index 0000000000..ad50a3765f
--- /dev/null
+++ b/accel/tcg/tcg-cpus-rr.c
@@ -0,0 +1,270 @@
+/*
+ * QEMU TCG Single Threaded vCPUs implementation
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2014 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "sysemu/tcg.h"
+#include "sysemu/replay.h"
+#include "qemu/main-loop.h"
+#include "qemu/guest-random.h"
+#include "exec/exec-all.h"
+#include "hw/boards.h"
+
+#include "tcg-cpus.h"
+#include "tcg-cpus-rr.h"
+#include "tcg-cpus-icount.h"
+
+/* Kick all RR vCPUs */
+void qemu_cpu_kick_rr_cpus(CPUState *unused)
+{
+ CPUState *cpu;
+
+ CPU_FOREACH(cpu) {
+ cpu_exit(cpu);
+ };
+}
+
+/*
+ * TCG vCPU kick timer
+ *
+ * The kick timer is responsible for moving single threaded vCPU
+ * emulation on to the next vCPU. If more than one vCPU is running a
+ * timer event with force a cpu->exit so the next vCPU can get
+ * scheduled.
+ *
+ * The timer is removed if all vCPUs are idle and restarted again once
+ * idleness is complete.
+ */
+
+static QEMUTimer *tcg_kick_vcpu_timer;
+static CPUState *tcg_current_rr_cpu;
+
+#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
+
+static inline int64_t qemu_tcg_next_kick(void)
+{
+ return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
+}
+
+/* Kick the currently round-robin scheduled vCPU to next */
+static void qemu_cpu_kick_rr_next_cpu(void)
+{
+ CPUState *cpu;
+ do {
+ cpu = qatomic_mb_read(&tcg_current_rr_cpu);
+ if (cpu) {
+ cpu_exit(cpu);
+ }
+ } while (cpu != qatomic_mb_read(&tcg_current_rr_cpu));
+}
+
+static void kick_tcg_thread(void *opaque)
+{
+ timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
+ qemu_cpu_kick_rr_next_cpu();
+}
+
+static void start_tcg_kick_timer(void)
+{
+ if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
+ tcg_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ kick_tcg_thread, NULL);
+ }
+ if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) {
+ timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
+ }
+}
+
+static void stop_tcg_kick_timer(void)
+{
+ if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) {
+ timer_del(tcg_kick_vcpu_timer);
+ }
+}
+
+static void qemu_tcg_rr_wait_io_event(void)
+{
+ CPUState *cpu;
+
+ while (all_cpu_threads_idle()) {
+ stop_tcg_kick_timer();
+ qemu_cond_wait_iothread(first_cpu->halt_cond);
+ }
+
+ start_tcg_kick_timer();
+
+ CPU_FOREACH(cpu) {
+ qemu_wait_io_event_common(cpu);
+ }
+}
+
+/*
+ * Destroy any remaining vCPUs which have been unplugged and have
+ * finished running
+ */
+static void deal_with_unplugged_cpus(void)
+{
+ CPUState *cpu;
+
+ CPU_FOREACH(cpu) {
+ if (cpu->unplug && !cpu_can_run(cpu)) {
+ qemu_tcg_destroy_vcpu(cpu);
+ break;
+ }
+ }
+}
+
+/*
+ * In the single-threaded case each vCPU is simulated in turn. If
+ * there is more than a single vCPU we create a simple timer to kick
+ * the vCPU and ensure we don't get stuck in a tight loop in one vCPU.
+ * This is done explicitly rather than relying on side-effects
+ * elsewhere.
+ */
+
+void *tcg_rr_cpu_thread_fn(void *arg)
+{
+ CPUState *cpu = arg;
+
+ assert(tcg_enabled());
+ rcu_register_thread();
+ tcg_register_thread();
+
+ qemu_mutex_lock_iothread();
+ qemu_thread_get_self(cpu->thread);
+
+ cpu->thread_id = qemu_get_thread_id();
+ cpu->can_do_io = 1;
+ cpu_thread_signal_created(cpu);
+ qemu_guest_random_seed_thread_part2(cpu->random_seed);
+
+ /* wait for initial kick-off after machine start */
+ while (first_cpu->stopped) {
+ qemu_cond_wait_iothread(first_cpu->halt_cond);
+
+ /* process any pending work */
+ CPU_FOREACH(cpu) {
+ current_cpu = cpu;
+ qemu_wait_io_event_common(cpu);
+ }
+ }
+
+ start_tcg_kick_timer();
+
+ cpu = first_cpu;
+
+ /* process any pending work */
+ cpu->exit_request = 1;
+
+ while (1) {
+ qemu_mutex_unlock_iothread();
+ replay_mutex_lock();
+ qemu_mutex_lock_iothread();
+
+ if (icount_enabled()) {
+ /* Account partial waits to QEMU_CLOCK_VIRTUAL. */
+ icount_account_warp_timer();
+ /*
+ * Run the timers here. This is much more efficient than
+ * waking up the I/O thread and waiting for completion.
+ */
+ handle_icount_deadline();
+ }
+
+ replay_mutex_unlock();
+
+ if (!cpu) {
+ cpu = first_cpu;
+ }
+
+ while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) {
+
+ qatomic_mb_set(&tcg_current_rr_cpu, cpu);
+ current_cpu = cpu;
+
+ qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
+ (cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
+
+ if (cpu_can_run(cpu)) {
+ int r;
+
+ qemu_mutex_unlock_iothread();
+ if (icount_enabled()) {
+ prepare_icount_for_run(cpu);
+ }
+ r = tcg_cpu_exec(cpu);
+ if (icount_enabled()) {
+ process_icount_data(cpu);
+ }
+ qemu_mutex_lock_iothread();
+
+ if (r == EXCP_DEBUG) {
+ cpu_handle_guest_debug(cpu);
+ break;
+ } else if (r == EXCP_ATOMIC) {
+ qemu_mutex_unlock_iothread();
+ cpu_exec_step_atomic(cpu);
+ qemu_mutex_lock_iothread();
+ break;
+ }
+ } else if (cpu->stop) {
+ if (cpu->unplug) {
+ cpu = CPU_NEXT(cpu);
+ }
+ break;
+ }
+
+ cpu = CPU_NEXT(cpu);
+ } /* while (cpu && !cpu->exit_request).. */
+
+ /* Does not need qatomic_mb_set because a spurious wakeup is okay. */
+ qatomic_set(&tcg_current_rr_cpu, NULL);
+
+ if (cpu && cpu->exit_request) {
+ qatomic_mb_set(&cpu->exit_request, 0);
+ }
+
+ if (icount_enabled() && all_cpu_threads_idle()) {
+ /*
+ * When all cpus are sleeping (e.g in WFI), to avoid a deadlock
+ * in the main_loop, wake it up in order to start the warp timer.
+ */
+ qemu_notify_event();
+ }
+
+ qemu_tcg_rr_wait_io_event();
+ deal_with_unplugged_cpus();
+ }
+
+ rcu_unregister_thread();
+ return NULL;
+}
+
+const CpusAccel tcg_cpus_rr = {
+ .create_vcpu_thread = tcg_start_vcpu_thread,
+ .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
+
+ .handle_interrupt = tcg_handle_interrupt,
+};
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c
index da1c63d8f6..f2b9bbf99e 100644
--- a/accel/tcg/tcg-cpus.c
+++ b/accel/tcg/tcg-cpus.c
@@ -1,5 +1,7 @@
/*
- * QEMU System Emulator
+ * QEMU TCG vCPU common functionality
+ *
+ * Functionality common to all TCG vCPU variants: mttcg, rr and icount.
*
* Copyright (c) 2003-2008 Fabrice Bellard
* Copyright (c) 2014 Red Hat Inc.
@@ -33,436 +35,12 @@
#include "hw/boards.h"
#include "tcg-cpus.h"
+#include "tcg-cpus-mttcg.h"
+#include "tcg-cpus-rr.h"
-/* Kick all RR vCPUs */
-static void qemu_cpu_kick_rr_cpus(void)
-{
- CPUState *cpu;
+/* common functionality among all TCG variants */
- CPU_FOREACH(cpu) {
- cpu_exit(cpu);
- };
-}
-
-static void tcg_kick_vcpu_thread(CPUState *cpu)
-{
- if (qemu_tcg_mttcg_enabled()) {
- cpu_exit(cpu);
- } else {
- qemu_cpu_kick_rr_cpus();
- }
-}
-
-/*
- * TCG vCPU kick timer
- *
- * The kick timer is responsible for moving single threaded vCPU
- * emulation on to the next vCPU. If more than one vCPU is running a
- * timer event with force a cpu->exit so the next vCPU can get
- * scheduled.
- *
- * The timer is removed if all vCPUs are idle and restarted again once
- * idleness is complete.
- */
-
-static QEMUTimer *tcg_kick_vcpu_timer;
-static CPUState *tcg_current_rr_cpu;
-
-#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
-
-static inline int64_t qemu_tcg_next_kick(void)
-{
- return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
-}
-
-/* Kick the currently round-robin scheduled vCPU to next */
-static void qemu_cpu_kick_rr_next_cpu(void)
-{
- CPUState *cpu;
- do {
- cpu = qatomic_mb_read(&tcg_current_rr_cpu);
- if (cpu) {
- cpu_exit(cpu);
- }
- } while (cpu != qatomic_mb_read(&tcg_current_rr_cpu));
-}
-
-static void kick_tcg_thread(void *opaque)
-{
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
- qemu_cpu_kick_rr_next_cpu();
-}
-
-static void start_tcg_kick_timer(void)
-{
- assert(!mttcg_enabled);
- if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
- tcg_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
- kick_tcg_thread, NULL);
- }
- if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) {
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
- }
-}
-
-static void stop_tcg_kick_timer(void)
-{
- assert(!mttcg_enabled);
- if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) {
- timer_del(tcg_kick_vcpu_timer);
- }
-}
-
-static void qemu_tcg_destroy_vcpu(CPUState *cpu)
-{
-}
-
-static void qemu_tcg_rr_wait_io_event(void)
-{
- CPUState *cpu;
-
- while (all_cpu_threads_idle()) {
- stop_tcg_kick_timer();
- qemu_cond_wait_iothread(first_cpu->halt_cond);
- }
-
- start_tcg_kick_timer();
-
- CPU_FOREACH(cpu) {
- qemu_wait_io_event_common(cpu);
- }
-}
-
-static int64_t tcg_get_icount_limit(void)
-{
- int64_t deadline;
-
- if (replay_mode != REPLAY_MODE_PLAY) {
- /*
- * Include all the timers, because they may need an attention.
- * Too long CPU execution may create unnecessary delay in UI.
- */
- deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
- QEMU_TIMER_ATTR_ALL);
- /* Check realtime timers, because they help with input processing */
- deadline = qemu_soonest_timeout(deadline,
- qemu_clock_deadline_ns_all(QEMU_CLOCK_REALTIME,
- QEMU_TIMER_ATTR_ALL));
-
- /*
- * Maintain prior (possibly buggy) behaviour where if no deadline
- * was set (as there is no QEMU_CLOCK_VIRTUAL timer) or it is more than
- * INT32_MAX nanoseconds ahead, we still use INT32_MAX
- * nanoseconds.
- */
- if ((deadline < 0) || (deadline > INT32_MAX)) {
- deadline = INT32_MAX;
- }
-
- return icount_round(deadline);
- } else {
- return replay_get_instructions();
- }
-}
-
-static void notify_aio_contexts(void)
-{
- /* Wake up other AioContexts. */
- qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
- qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL);
-}
-
-static void handle_icount_deadline(void)
-{
- assert(qemu_in_vcpu_thread());
- if (icount_enabled()) {
- int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
- QEMU_TIMER_ATTR_ALL);
-
- if (deadline == 0) {
- notify_aio_contexts();
- }
- }
-}
-
-static void prepare_icount_for_run(CPUState *cpu)
-{
- if (icount_enabled()) {
- int insns_left;
-
- /*
- * These should always be cleared by process_icount_data after
- * each vCPU execution. However u16.high can be raised
- * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
- */
- g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
- g_assert(cpu->icount_extra == 0);
-
- cpu->icount_budget = tcg_get_icount_limit();
- insns_left = MIN(0xffff, cpu->icount_budget);
- cpu_neg(cpu)->icount_decr.u16.low = insns_left;
- cpu->icount_extra = cpu->icount_budget - insns_left;
-
- replay_mutex_lock();
-
- if (cpu->icount_budget == 0 && replay_has_checkpoint()) {
- notify_aio_contexts();
- }
- }
-}
-
-static void process_icount_data(CPUState *cpu)
-{
- if (icount_enabled()) {
- /* Account for executed instructions */
- icount_update(cpu);
-
- /* Reset the counters */
- cpu_neg(cpu)->icount_decr.u16.low = 0;
- cpu->icount_extra = 0;
- cpu->icount_budget = 0;
-
- replay_account_executed_instructions();
-
- replay_mutex_unlock();
- }
-}
-
-static int tcg_cpu_exec(CPUState *cpu)
-{
- int ret;
-#ifdef CONFIG_PROFILER
- int64_t ti;
-#endif
-
- assert(tcg_enabled());
-#ifdef CONFIG_PROFILER
- ti = profile_getclock();
-#endif
- cpu_exec_start(cpu);
- ret = cpu_exec(cpu);
- cpu_exec_end(cpu);
-#ifdef CONFIG_PROFILER
- qatomic_set(&tcg_ctx->prof.cpu_exec_time,
- tcg_ctx->prof.cpu_exec_time + profile_getclock() - ti);
-#endif
- return ret;
-}
-
-/*
- * Destroy any remaining vCPUs which have been unplugged and have
- * finished running
- */
-static void deal_with_unplugged_cpus(void)
-{
- CPUState *cpu;
-
- CPU_FOREACH(cpu) {
- if (cpu->unplug && !cpu_can_run(cpu)) {
- qemu_tcg_destroy_vcpu(cpu);
- cpu_thread_signal_destroyed(cpu);
- break;
- }
- }
-}
-
-/*
- * Single-threaded TCG
- *
- * In the single-threaded case each vCPU is simulated in turn. If
- * there is more than a single vCPU we create a simple timer to kick
- * the vCPU and ensure we don't get stuck in a tight loop in one vCPU.
- * This is done explicitly rather than relying on side-effects
- * elsewhere.
- */
-
-static void *tcg_rr_cpu_thread_fn(void *arg)
-{
- CPUState *cpu = arg;
-
- assert(tcg_enabled());
- rcu_register_thread();
- tcg_register_thread();
-
- qemu_mutex_lock_iothread();
- qemu_thread_get_self(cpu->thread);
-
- cpu->thread_id = qemu_get_thread_id();
- cpu->can_do_io = 1;
- cpu_thread_signal_created(cpu);
- qemu_guest_random_seed_thread_part2(cpu->random_seed);
-
- /* wait for initial kick-off after machine start */
- while (first_cpu->stopped) {
- qemu_cond_wait_iothread(first_cpu->halt_cond);
-
- /* process any pending work */
- CPU_FOREACH(cpu) {
- current_cpu = cpu;
- qemu_wait_io_event_common(cpu);
- }
- }
-
- start_tcg_kick_timer();
-
- cpu = first_cpu;
-
- /* process any pending work */
- cpu->exit_request = 1;
-
- while (1) {
- qemu_mutex_unlock_iothread();
- replay_mutex_lock();
- qemu_mutex_lock_iothread();
- /* Account partial waits to QEMU_CLOCK_VIRTUAL. */
- icount_account_warp_timer();
-
- /*
- * Run the timers here. This is much more efficient than
- * waking up the I/O thread and waiting for completion.
- */
- handle_icount_deadline();
-
- replay_mutex_unlock();
-
- if (!cpu) {
- cpu = first_cpu;
- }
-
- while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) {
-
- qatomic_mb_set(&tcg_current_rr_cpu, cpu);
- current_cpu = cpu;
-
- qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
- (cpu->singlestep_enabled & SSTEP_NOTIMER) == 0);
-
- if (cpu_can_run(cpu)) {
- int r;
-
- qemu_mutex_unlock_iothread();
- prepare_icount_for_run(cpu);
-
- r = tcg_cpu_exec(cpu);
-
- process_icount_data(cpu);
- qemu_mutex_lock_iothread();
-
- if (r == EXCP_DEBUG) {
- cpu_handle_guest_debug(cpu);
- break;
- } else if (r == EXCP_ATOMIC) {
- qemu_mutex_unlock_iothread();
- cpu_exec_step_atomic(cpu);
- qemu_mutex_lock_iothread();
- break;
- }
- } else if (cpu->stop) {
- if (cpu->unplug) {
- cpu = CPU_NEXT(cpu);
- }
- break;
- }
-
- cpu = CPU_NEXT(cpu);
- } /* while (cpu && !cpu->exit_request).. */
-
- /* Does not need qatomic_mb_set because a spurious wakeup is okay. */
- qatomic_set(&tcg_current_rr_cpu, NULL);
-
- if (cpu && cpu->exit_request) {
- qatomic_mb_set(&cpu->exit_request, 0);
- }
-
- if (icount_enabled() && all_cpu_threads_idle()) {
- /*
- * When all cpus are sleeping (e.g in WFI), to avoid a deadlock
- * in the main_loop, wake it up in order to start the warp timer.
- */
- qemu_notify_event();
- }
-
- qemu_tcg_rr_wait_io_event();
- deal_with_unplugged_cpus();
- }
-
- rcu_unregister_thread();
- return NULL;
-}
-
-/*
- * Multi-threaded TCG
- *
- * In the multi-threaded case each vCPU has its own thread. The TLS
- * variable current_cpu can be used deep in the code to find the
- * current CPUState for a given thread.
- */
-
-static void *tcg_cpu_thread_fn(void *arg)
-{
- CPUState *cpu = arg;
-
- assert(tcg_enabled());
- g_assert(!icount_enabled());
-
- rcu_register_thread();
- tcg_register_thread();
-
- qemu_mutex_lock_iothread();
- qemu_thread_get_self(cpu->thread);
-
- cpu->thread_id = qemu_get_thread_id();
- cpu->can_do_io = 1;
- current_cpu = cpu;
- cpu_thread_signal_created(cpu);
- qemu_guest_random_seed_thread_part2(cpu->random_seed);
-
- /* process any pending work */
- cpu->exit_request = 1;
-
- do {
- if (cpu_can_run(cpu)) {
- int r;
- qemu_mutex_unlock_iothread();
- r = tcg_cpu_exec(cpu);
- qemu_mutex_lock_iothread();
- switch (r) {
- case EXCP_DEBUG:
- cpu_handle_guest_debug(cpu);
- break;
- case EXCP_HALTED:
- /*
- * during start-up the vCPU is reset and the thread is
- * kicked several times. If we don't ensure we go back
- * to sleep in the halted state we won't cleanly
- * start-up when the vCPU is enabled.
- *
- * cpu->halted should ensure we sleep in wait_io_event
- */
- g_assert(cpu->halted);
- break;
- case EXCP_ATOMIC:
- qemu_mutex_unlock_iothread();
- cpu_exec_step_atomic(cpu);
- qemu_mutex_lock_iothread();
- default:
- /* Ignore everything else? */
- break;
- }
- }
-
- qatomic_mb_set(&cpu->exit_request, 0);
- qemu_wait_io_event(cpu);
- } while (!cpu->unplug || cpu_can_run(cpu));
-
- qemu_tcg_destroy_vcpu(cpu);
- cpu_thread_signal_destroyed(cpu);
- qemu_mutex_unlock_iothread();
- rcu_unregister_thread();
- return NULL;
-}
-
-static void tcg_start_vcpu_thread(CPUState *cpu)
+void tcg_start_vcpu_thread(CPUState *cpu)
{
char thread_name[VCPU_THREAD_NAME_SIZE];
static QemuCond *single_tcg_halt_cond;
@@ -518,29 +96,36 @@ static void tcg_start_vcpu_thread(CPUState *cpu)
}
}
-static int64_t tcg_get_virtual_clock(void)
+void qemu_tcg_destroy_vcpu(CPUState *cpu)
{
- if (icount_enabled()) {
- return icount_get();
- }
- return cpu_get_clock();
+ cpu_thread_signal_destroyed(cpu);
}
-static int64_t tcg_get_elapsed_ticks(void)
+int tcg_cpu_exec(CPUState *cpu)
{
- if (icount_enabled()) {
- return icount_get();
- }
- return cpu_get_ticks();
+ int ret;
+#ifdef CONFIG_PROFILER
+ int64_t ti;
+#endif
+ assert(tcg_enabled());
+#ifdef CONFIG_PROFILER
+ ti = profile_getclock();
+#endif
+ cpu_exec_start(cpu);
+ ret = cpu_exec(cpu);
+ cpu_exec_end(cpu);
+#ifdef CONFIG_PROFILER
+ qatomic_set(&tcg_ctx->prof.cpu_exec_time,
+ tcg_ctx->prof.cpu_exec_time + profile_getclock() - ti);
+#endif
+ return ret;
}
/* mask must never be zero, except for A20 change call */
-static void tcg_handle_interrupt(CPUState *cpu, int mask)
+void tcg_handle_interrupt(CPUState *cpu, int mask)
{
- int old_mask;
g_assert(qemu_mutex_iothread_locked());
- old_mask = cpu->interrupt_request;
cpu->interrupt_request |= mask;
/*
@@ -551,20 +136,5 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
qemu_cpu_kick(cpu);
} else {
qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1);
- if (icount_enabled() &&
- !cpu->can_do_io
- && (mask & ~old_mask) != 0) {
- cpu_abort(cpu, "Raised interrupt while not in I/O function");
- }
}
}
-
-const CpusAccel tcg_cpus = {
- .create_vcpu_thread = tcg_start_vcpu_thread,
- .kick_vcpu_thread = tcg_kick_vcpu_thread,
-
- .handle_interrupt = tcg_handle_interrupt,
-
- .get_virtual_clock = tcg_get_virtual_clock,
- .get_elapsed_ticks = tcg_get_elapsed_ticks,
-};
diff --git a/softmmu/icount.c b/softmmu/icount.c
index 020a201a01..dbcd8c3594 100644
--- a/softmmu/icount.c
+++ b/softmmu/icount.c
@@ -396,7 +396,7 @@ void icount_start_warp_timer(void)
void icount_account_warp_timer(void)
{
- if (!icount_enabled() || !icount_sleep) {
+ if (!icount_sleep) {
return;
}
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 19b9343d5b..f39aab0a0c 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -12,4 +12,11 @@ tcg_ss.add(when: 'CONFIG_SOFTMMU', if_false: files('user-exec-stub.c'))
tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin-gen.c'), libdl])
specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
-specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files('tcg-all.c', 'cputlb.c', 'tcg-cpus.c'))
+specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files(
+ 'tcg-all.c',
+ 'cputlb.c',
+ 'tcg-cpus.c',
+ 'tcg-cpus-mttcg.c',
+ 'tcg-cpus-icount.c',
+ 'tcg-cpus-rr.c'
+))
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 02/25] accel/tcg: split tcg_start_vcpu_thread
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 01/25] accel/tcg: split CpusAccel into three TCG variants Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 03/25] accel/tcg: rename tcg-cpus functions to match module name Claudio Fontana
` (24 subsequent siblings)
26 siblings, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Jason Wang, Marcelo Tosatti, qemu-devel, Peter Xu,
Dario Faggioli, Cameron Esfahani, haxm-team, Claudio Fontana,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Colin Xu
after the initial split into 3 tcg variants, we proceed to also
split tcg_start_vcpu_thread.
We actually split it in 2 this time, since the icount variant
just uses the round robin function.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-cpus-mttcg.h | 21 --------------
accel/tcg/tcg-cpus-rr.h | 3 +-
accel/tcg/tcg-cpus.h | 1 -
accel/tcg/tcg-all.c | 5 ++++
accel/tcg/tcg-cpus-icount.c | 2 +-
accel/tcg/tcg-cpus-mttcg.c | 29 +++++++++++++++++--
accel/tcg/tcg-cpus-rr.c | 39 +++++++++++++++++++++++--
accel/tcg/tcg-cpus.c | 58 -------------------------------------
8 files changed, 71 insertions(+), 87 deletions(-)
delete mode 100644 accel/tcg/tcg-cpus-mttcg.h
diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h
deleted file mode 100644
index d1bd771f49..0000000000
--- a/accel/tcg/tcg-cpus-mttcg.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * QEMU TCG Multi Threaded vCPUs implementation
- *
- * Copyright 2020 SUSE LLC
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef TCG_CPUS_MTTCG_H
-#define TCG_CPUS_MTTCG_H
-
-/*
- * In the multi-threaded case each vCPU has its own thread. The TLS
- * variable current_cpu can be used deep in the code to find the
- * current CPUState for a given thread.
- */
-
-void *tcg_cpu_thread_fn(void *arg);
-
-#endif /* TCG_CPUS_MTTCG_H */
diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h
index 1936fd16ab..2e5943eda9 100644
--- a/accel/tcg/tcg-cpus-rr.h
+++ b/accel/tcg/tcg-cpus-rr.h
@@ -15,6 +15,7 @@
/* Kick all RR vCPUs. */
void qemu_cpu_kick_rr_cpus(CPUState *unused);
-void *tcg_rr_cpu_thread_fn(void *arg);
+/* start the round robin vcpu thread */
+void rr_start_vcpu_thread(CPUState *cpu);
#endif /* TCG_CPUS_RR_H */
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h
index 279ba72e1f..b7ca954e13 100644
--- a/accel/tcg/tcg-cpus.h
+++ b/accel/tcg/tcg-cpus.h
@@ -18,7 +18,6 @@ extern const CpusAccel tcg_cpus_mttcg;
extern const CpusAccel tcg_cpus_icount;
extern const CpusAccel tcg_cpus_rr;
-void tcg_start_vcpu_thread(CPUState *cpu);
void qemu_tcg_destroy_vcpu(CPUState *cpu);
int tcg_cpu_exec(CPUState *cpu);
void tcg_handle_interrupt(CPUState *cpu, int mask);
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index e42a028043..1ac0b76515 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -105,6 +105,11 @@ static int tcg_init(MachineState *ms)
tcg_exec_init(s->tb_size * 1024 * 1024);
mttcg_enabled = s->mttcg_enabled;
+ /*
+ * Initialize TCG regions
+ */
+ tcg_region_init();
+
if (mttcg_enabled) {
cpus_register_accel(&tcg_cpus_mttcg);
} else if (icount_enabled()) {
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c
index d3af3afb6d..82dbe2cacf 100644
--- a/accel/tcg/tcg-cpus-icount.c
+++ b/accel/tcg/tcg-cpus-icount.c
@@ -138,7 +138,7 @@ static void icount_handle_interrupt(CPUState *cpu, int mask)
}
const CpusAccel tcg_cpus_icount = {
- .create_vcpu_thread = tcg_start_vcpu_thread,
+ .create_vcpu_thread = rr_start_vcpu_thread,
.kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
.handle_interrupt = icount_handle_interrupt,
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c
index dac724fc85..f2b892a380 100644
--- a/accel/tcg/tcg-cpus-mttcg.c
+++ b/accel/tcg/tcg-cpus-mttcg.c
@@ -33,7 +33,6 @@
#include "hw/boards.h"
#include "tcg-cpus.h"
-#include "tcg-cpus-mttcg.h"
/*
* In the multi-threaded case each vCPU has its own thread. The TLS
@@ -41,7 +40,7 @@
* current CPUState for a given thread.
*/
-void *tcg_cpu_thread_fn(void *arg)
+static void *tcg_cpu_thread_fn(void *arg)
{
CPUState *cpu = arg;
@@ -109,8 +108,32 @@ static void mttcg_kick_vcpu_thread(CPUState *cpu)
cpu_exit(cpu);
}
+static void mttcg_start_vcpu_thread(CPUState *cpu)
+{
+ char thread_name[VCPU_THREAD_NAME_SIZE];
+
+ g_assert(tcg_enabled());
+
+ parallel_cpus = (current_machine->smp.max_cpus > 1);
+
+ cpu->thread = g_malloc0(sizeof(QemuThread));
+ cpu->halt_cond = g_malloc0(sizeof(QemuCond));
+ qemu_cond_init(cpu->halt_cond);
+
+ /* create a thread per vCPU with TCG (MTTCG) */
+ snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG",
+ cpu->cpu_index);
+
+ qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn,
+ cpu, QEMU_THREAD_JOINABLE);
+
+#ifdef _WIN32
+ cpu->hThread = qemu_thread_get_handle(cpu->thread);
+#endif
+}
+
const CpusAccel tcg_cpus_mttcg = {
- .create_vcpu_thread = tcg_start_vcpu_thread,
+ .create_vcpu_thread = mttcg_start_vcpu_thread,
.kick_vcpu_thread = mttcg_kick_vcpu_thread,
.handle_interrupt = tcg_handle_interrupt,
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c
index ad50a3765f..f3b262bec7 100644
--- a/accel/tcg/tcg-cpus-rr.c
+++ b/accel/tcg/tcg-cpus-rr.c
@@ -144,7 +144,7 @@ static void deal_with_unplugged_cpus(void)
* elsewhere.
*/
-void *tcg_rr_cpu_thread_fn(void *arg)
+static void *tcg_rr_cpu_thread_fn(void *arg)
{
CPUState *cpu = arg;
@@ -262,8 +262,43 @@ void *tcg_rr_cpu_thread_fn(void *arg)
return NULL;
}
+void rr_start_vcpu_thread(CPUState *cpu)
+{
+ char thread_name[VCPU_THREAD_NAME_SIZE];
+ static QemuCond *single_tcg_halt_cond;
+ static QemuThread *single_tcg_cpu_thread;
+
+ g_assert(tcg_enabled());
+ parallel_cpus = false;
+
+ if (!single_tcg_cpu_thread) {
+ cpu->thread = g_malloc0(sizeof(QemuThread));
+ cpu->halt_cond = g_malloc0(sizeof(QemuCond));
+ qemu_cond_init(cpu->halt_cond);
+
+ /* share a single thread for all cpus with TCG */
+ snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG");
+ qemu_thread_create(cpu->thread, thread_name,
+ tcg_rr_cpu_thread_fn,
+ cpu, QEMU_THREAD_JOINABLE);
+
+ single_tcg_halt_cond = cpu->halt_cond;
+ single_tcg_cpu_thread = cpu->thread;
+#ifdef _WIN32
+ cpu->hThread = qemu_thread_get_handle(cpu->thread);
+#endif
+ } else {
+ /* we share the thread */
+ cpu->thread = single_tcg_cpu_thread;
+ cpu->halt_cond = single_tcg_halt_cond;
+ cpu->thread_id = first_cpu->thread_id;
+ cpu->can_do_io = 1;
+ cpu->created = true;
+ }
+}
+
const CpusAccel tcg_cpus_rr = {
- .create_vcpu_thread = tcg_start_vcpu_thread,
+ .create_vcpu_thread = rr_start_vcpu_thread,
.kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
.handle_interrupt = tcg_handle_interrupt,
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c
index f2b9bbf99e..86fd09545a 100644
--- a/accel/tcg/tcg-cpus.c
+++ b/accel/tcg/tcg-cpus.c
@@ -35,67 +35,9 @@
#include "hw/boards.h"
#include "tcg-cpus.h"
-#include "tcg-cpus-mttcg.h"
-#include "tcg-cpus-rr.h"
/* common functionality among all TCG variants */
-void tcg_start_vcpu_thread(CPUState *cpu)
-{
- char thread_name[VCPU_THREAD_NAME_SIZE];
- static QemuCond *single_tcg_halt_cond;
- static QemuThread *single_tcg_cpu_thread;
- static int tcg_region_inited;
-
- assert(tcg_enabled());
- /*
- * Initialize TCG regions--once. Now is a good time, because:
- * (1) TCG's init context, prologue and target globals have been set up.
- * (2) qemu_tcg_mttcg_enabled() works now (TCG init code runs before the
- * -accel flag is processed, so the check doesn't work then).
- */
- if (!tcg_region_inited) {
- tcg_region_inited = 1;
- tcg_region_init();
- parallel_cpus = qemu_tcg_mttcg_enabled() && current_machine->smp.max_cpus > 1;
- }
-
- if (qemu_tcg_mttcg_enabled() || !single_tcg_cpu_thread) {
- cpu->thread = g_malloc0(sizeof(QemuThread));
- cpu->halt_cond = g_malloc0(sizeof(QemuCond));
- qemu_cond_init(cpu->halt_cond);
-
- if (qemu_tcg_mttcg_enabled()) {
- /* create a thread per vCPU with TCG (MTTCG) */
- snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG",
- cpu->cpu_index);
-
- qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn,
- cpu, QEMU_THREAD_JOINABLE);
-
- } else {
- /* share a single thread for all cpus with TCG */
- snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG");
- qemu_thread_create(cpu->thread, thread_name,
- tcg_rr_cpu_thread_fn,
- cpu, QEMU_THREAD_JOINABLE);
-
- single_tcg_halt_cond = cpu->halt_cond;
- single_tcg_cpu_thread = cpu->thread;
- }
-#ifdef _WIN32
- cpu->hThread = qemu_thread_get_handle(cpu->thread);
-#endif
- } else {
- /* For non-MTTCG cases we share the thread */
- cpu->thread = single_tcg_cpu_thread;
- cpu->halt_cond = single_tcg_halt_cond;
- cpu->thread_id = first_cpu->thread_id;
- cpu->can_do_io = 1;
- cpu->created = true;
- }
-}
-
void qemu_tcg_destroy_vcpu(CPUState *cpu)
{
cpu_thread_signal_destroyed(cpu);
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 03/25] accel/tcg: rename tcg-cpus functions to match module name
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 01/25] accel/tcg: split CpusAccel into three TCG variants Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 02/25] accel/tcg: split tcg_start_vcpu_thread Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 04/25] i386: move kvm accel files into kvm/ Claudio Fontana
` (23 subsequent siblings)
26 siblings, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Philippe Mathieu-Daudé,
Eduardo Habkost, Paul Durrant, Jason Wang, Marcelo Tosatti,
qemu-devel, Peter Xu, Dario Faggioli, Cameron Esfahani,
haxm-team, Claudio Fontana, Anthony Perard, Bruce Rogers,
Olaf Hering, Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-cpus-icount.h | 6 +--
accel/tcg/tcg-cpus-rr.h | 2 +-
accel/tcg/tcg-cpus.h | 6 +--
accel/tcg/tcg-cpus-icount.c | 24 ++++++------
accel/tcg/tcg-cpus-mttcg.c | 10 ++---
accel/tcg/tcg-cpus-rr.c | 74 ++++++++++++++++++-------------------
accel/tcg/tcg-cpus.c | 6 +--
7 files changed, 64 insertions(+), 64 deletions(-)
diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h
index cbcf76b413..b695939dfa 100644
--- a/accel/tcg/tcg-cpus-icount.h
+++ b/accel/tcg/tcg-cpus-icount.h
@@ -10,8 +10,8 @@
#ifndef TCG_CPUS_ICOUNT_H
#define TCG_CPUS_ICOUNT_H
-void handle_icount_deadline(void);
-void prepare_icount_for_run(CPUState *cpu);
-void process_icount_data(CPUState *cpu);
+void icount_handle_deadline(void);
+void icount_prepare_for_run(CPUState *cpu);
+void icount_process_data(CPUState *cpu);
#endif /* TCG_CPUS_ICOUNT_H */
diff --git a/accel/tcg/tcg-cpus-rr.h b/accel/tcg/tcg-cpus-rr.h
index 2e5943eda9..54f6ae6e86 100644
--- a/accel/tcg/tcg-cpus-rr.h
+++ b/accel/tcg/tcg-cpus-rr.h
@@ -13,7 +13,7 @@
#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
/* Kick all RR vCPUs. */
-void qemu_cpu_kick_rr_cpus(CPUState *unused);
+void rr_kick_vcpu_thread(CPUState *unused);
/* start the round robin vcpu thread */
void rr_start_vcpu_thread(CPUState *cpu);
diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h
index b7ca954e13..d6893a32f8 100644
--- a/accel/tcg/tcg-cpus.h
+++ b/accel/tcg/tcg-cpus.h
@@ -18,8 +18,8 @@ extern const CpusAccel tcg_cpus_mttcg;
extern const CpusAccel tcg_cpus_icount;
extern const CpusAccel tcg_cpus_rr;
-void qemu_tcg_destroy_vcpu(CPUState *cpu);
-int tcg_cpu_exec(CPUState *cpu);
-void tcg_handle_interrupt(CPUState *cpu, int mask);
+void tcg_cpus_destroy(CPUState *cpu);
+int tcg_cpus_exec(CPUState *cpu);
+void tcg_cpus_handle_interrupt(CPUState *cpu, int mask);
#endif /* TCG_CPUS_H */
diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c
index 82dbe2cacf..9f45432275 100644
--- a/accel/tcg/tcg-cpus-icount.c
+++ b/accel/tcg/tcg-cpus-icount.c
@@ -36,7 +36,7 @@
#include "tcg-cpus-icount.h"
#include "tcg-cpus-rr.h"
-static int64_t tcg_get_icount_limit(void)
+static int64_t icount_get_limit(void)
{
int64_t deadline;
@@ -68,37 +68,37 @@ static int64_t tcg_get_icount_limit(void)
}
}
-static void notify_aio_contexts(void)
+static void icount_notify_aio_contexts(void)
{
/* Wake up other AioContexts. */
qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL);
}
-void handle_icount_deadline(void)
+void icount_handle_deadline(void)
{
assert(qemu_in_vcpu_thread());
int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
QEMU_TIMER_ATTR_ALL);
if (deadline == 0) {
- notify_aio_contexts();
+ icount_notify_aio_contexts();
}
}
-void prepare_icount_for_run(CPUState *cpu)
+void icount_prepare_for_run(CPUState *cpu)
{
int insns_left;
/*
- * These should always be cleared by process_icount_data after
+ * These should always be cleared by icount_process_data after
* each vCPU execution. However u16.high can be raised
- * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt
+ * asynchronously by cpu_exit/cpu_interrupt/tcg_cpus_handle_interrupt
*/
g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0);
g_assert(cpu->icount_extra == 0);
- cpu->icount_budget = tcg_get_icount_limit();
+ cpu->icount_budget = icount_get_limit();
insns_left = MIN(0xffff, cpu->icount_budget);
cpu_neg(cpu)->icount_decr.u16.low = insns_left;
cpu->icount_extra = cpu->icount_budget - insns_left;
@@ -106,11 +106,11 @@ void prepare_icount_for_run(CPUState *cpu)
replay_mutex_lock();
if (cpu->icount_budget == 0 && replay_has_checkpoint()) {
- notify_aio_contexts();
+ icount_notify_aio_contexts();
}
}
-void process_icount_data(CPUState *cpu)
+void icount_process_data(CPUState *cpu)
{
/* Account for executed instructions */
icount_update(cpu);
@@ -129,7 +129,7 @@ static void icount_handle_interrupt(CPUState *cpu, int mask)
{
int old_mask = cpu->interrupt_request;
- tcg_handle_interrupt(cpu, mask);
+ tcg_cpus_handle_interrupt(cpu, mask);
if (qemu_cpu_is_self(cpu) &&
!cpu->can_do_io
&& (mask & ~old_mask) != 0) {
@@ -139,7 +139,7 @@ static void icount_handle_interrupt(CPUState *cpu, int mask)
const CpusAccel tcg_cpus_icount = {
.create_vcpu_thread = rr_start_vcpu_thread,
- .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
+ .kick_vcpu_thread = rr_kick_vcpu_thread,
.handle_interrupt = icount_handle_interrupt,
.get_virtual_clock = icount_get,
diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c
index f2b892a380..9c3767d260 100644
--- a/accel/tcg/tcg-cpus-mttcg.c
+++ b/accel/tcg/tcg-cpus-mttcg.c
@@ -40,7 +40,7 @@
* current CPUState for a given thread.
*/
-static void *tcg_cpu_thread_fn(void *arg)
+static void *mttcg_cpu_thread_fn(void *arg)
{
CPUState *cpu = arg;
@@ -66,7 +66,7 @@ static void *tcg_cpu_thread_fn(void *arg)
if (cpu_can_run(cpu)) {
int r;
qemu_mutex_unlock_iothread();
- r = tcg_cpu_exec(cpu);
+ r = tcg_cpus_exec(cpu);
qemu_mutex_lock_iothread();
switch (r) {
case EXCP_DEBUG:
@@ -97,7 +97,7 @@ static void *tcg_cpu_thread_fn(void *arg)
qemu_wait_io_event(cpu);
} while (!cpu->unplug || cpu_can_run(cpu));
- qemu_tcg_destroy_vcpu(cpu);
+ tcg_cpus_destroy(cpu);
qemu_mutex_unlock_iothread();
rcu_unregister_thread();
return NULL;
@@ -124,7 +124,7 @@ static void mttcg_start_vcpu_thread(CPUState *cpu)
snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/TCG",
cpu->cpu_index);
- qemu_thread_create(cpu->thread, thread_name, tcg_cpu_thread_fn,
+ qemu_thread_create(cpu->thread, thread_name, mttcg_cpu_thread_fn,
cpu, QEMU_THREAD_JOINABLE);
#ifdef _WIN32
@@ -136,5 +136,5 @@ const CpusAccel tcg_cpus_mttcg = {
.create_vcpu_thread = mttcg_start_vcpu_thread,
.kick_vcpu_thread = mttcg_kick_vcpu_thread,
- .handle_interrupt = tcg_handle_interrupt,
+ .handle_interrupt = tcg_cpus_handle_interrupt,
};
diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c
index f3b262bec7..0181d2e4eb 100644
--- a/accel/tcg/tcg-cpus-rr.c
+++ b/accel/tcg/tcg-cpus-rr.c
@@ -37,7 +37,7 @@
#include "tcg-cpus-icount.h"
/* Kick all RR vCPUs */
-void qemu_cpu_kick_rr_cpus(CPUState *unused)
+void rr_kick_vcpu_thread(CPUState *unused)
{
CPUState *cpu;
@@ -58,62 +58,62 @@ void qemu_cpu_kick_rr_cpus(CPUState *unused)
* idleness is complete.
*/
-static QEMUTimer *tcg_kick_vcpu_timer;
-static CPUState *tcg_current_rr_cpu;
+static QEMUTimer *rr_kick_vcpu_timer;
+static CPUState *rr_current_cpu;
#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
-static inline int64_t qemu_tcg_next_kick(void)
+static inline int64_t rr_next_kick_time(void)
{
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
}
/* Kick the currently round-robin scheduled vCPU to next */
-static void qemu_cpu_kick_rr_next_cpu(void)
+static void rr_kick_next_cpu(void)
{
CPUState *cpu;
do {
- cpu = qatomic_mb_read(&tcg_current_rr_cpu);
+ cpu = qatomic_mb_read(&rr_current_cpu);
if (cpu) {
cpu_exit(cpu);
}
- } while (cpu != qatomic_mb_read(&tcg_current_rr_cpu));
+ } while (cpu != qatomic_mb_read(&rr_current_cpu));
}
-static void kick_tcg_thread(void *opaque)
+static void rr_kick_thread(void *opaque)
{
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
- qemu_cpu_kick_rr_next_cpu();
+ timer_mod(rr_kick_vcpu_timer, rr_next_kick_time());
+ rr_kick_next_cpu();
}
-static void start_tcg_kick_timer(void)
+static void rr_start_kick_timer(void)
{
- if (!tcg_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
- tcg_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
- kick_tcg_thread, NULL);
+ if (!rr_kick_vcpu_timer && CPU_NEXT(first_cpu)) {
+ rr_kick_vcpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ rr_kick_thread, NULL);
}
- if (tcg_kick_vcpu_timer && !timer_pending(tcg_kick_vcpu_timer)) {
- timer_mod(tcg_kick_vcpu_timer, qemu_tcg_next_kick());
+ if (rr_kick_vcpu_timer && !timer_pending(rr_kick_vcpu_timer)) {
+ timer_mod(rr_kick_vcpu_timer, rr_next_kick_time());
}
}
-static void stop_tcg_kick_timer(void)
+static void rr_stop_kick_timer(void)
{
- if (tcg_kick_vcpu_timer && timer_pending(tcg_kick_vcpu_timer)) {
- timer_del(tcg_kick_vcpu_timer);
+ if (rr_kick_vcpu_timer && timer_pending(rr_kick_vcpu_timer)) {
+ timer_del(rr_kick_vcpu_timer);
}
}
-static void qemu_tcg_rr_wait_io_event(void)
+static void rr_wait_io_event(void)
{
CPUState *cpu;
while (all_cpu_threads_idle()) {
- stop_tcg_kick_timer();
+ rr_stop_kick_timer();
qemu_cond_wait_iothread(first_cpu->halt_cond);
}
- start_tcg_kick_timer();
+ rr_start_kick_timer();
CPU_FOREACH(cpu) {
qemu_wait_io_event_common(cpu);
@@ -124,13 +124,13 @@ static void qemu_tcg_rr_wait_io_event(void)
* Destroy any remaining vCPUs which have been unplugged and have
* finished running
*/
-static void deal_with_unplugged_cpus(void)
+static void rr_deal_with_unplugged_cpus(void)
{
CPUState *cpu;
CPU_FOREACH(cpu) {
if (cpu->unplug && !cpu_can_run(cpu)) {
- qemu_tcg_destroy_vcpu(cpu);
+ tcg_cpus_destroy(cpu);
break;
}
}
@@ -144,7 +144,7 @@ static void deal_with_unplugged_cpus(void)
* elsewhere.
*/
-static void *tcg_rr_cpu_thread_fn(void *arg)
+static void *rr_cpu_thread_fn(void *arg)
{
CPUState *cpu = arg;
@@ -171,7 +171,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg)
}
}
- start_tcg_kick_timer();
+ rr_start_kick_timer();
cpu = first_cpu;
@@ -190,7 +190,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg)
* Run the timers here. This is much more efficient than
* waking up the I/O thread and waiting for completion.
*/
- handle_icount_deadline();
+ icount_handle_deadline();
}
replay_mutex_unlock();
@@ -201,7 +201,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg)
while (cpu && cpu_work_list_empty(cpu) && !cpu->exit_request) {
- qatomic_mb_set(&tcg_current_rr_cpu, cpu);
+ qatomic_mb_set(&rr_current_cpu, cpu);
current_cpu = cpu;
qemu_clock_enable(QEMU_CLOCK_VIRTUAL,
@@ -212,11 +212,11 @@ static void *tcg_rr_cpu_thread_fn(void *arg)
qemu_mutex_unlock_iothread();
if (icount_enabled()) {
- prepare_icount_for_run(cpu);
+ icount_prepare_for_run(cpu);
}
- r = tcg_cpu_exec(cpu);
+ r = tcg_cpus_exec(cpu);
if (icount_enabled()) {
- process_icount_data(cpu);
+ icount_process_data(cpu);
}
qemu_mutex_lock_iothread();
@@ -240,7 +240,7 @@ static void *tcg_rr_cpu_thread_fn(void *arg)
} /* while (cpu && !cpu->exit_request).. */
/* Does not need qatomic_mb_set because a spurious wakeup is okay. */
- qatomic_set(&tcg_current_rr_cpu, NULL);
+ qatomic_set(&rr_current_cpu, NULL);
if (cpu && cpu->exit_request) {
qatomic_mb_set(&cpu->exit_request, 0);
@@ -254,8 +254,8 @@ static void *tcg_rr_cpu_thread_fn(void *arg)
qemu_notify_event();
}
- qemu_tcg_rr_wait_io_event();
- deal_with_unplugged_cpus();
+ rr_wait_io_event();
+ rr_deal_with_unplugged_cpus();
}
rcu_unregister_thread();
@@ -279,7 +279,7 @@ void rr_start_vcpu_thread(CPUState *cpu)
/* share a single thread for all cpus with TCG */
snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "ALL CPUs/TCG");
qemu_thread_create(cpu->thread, thread_name,
- tcg_rr_cpu_thread_fn,
+ rr_cpu_thread_fn,
cpu, QEMU_THREAD_JOINABLE);
single_tcg_halt_cond = cpu->halt_cond;
@@ -299,7 +299,7 @@ void rr_start_vcpu_thread(CPUState *cpu)
const CpusAccel tcg_cpus_rr = {
.create_vcpu_thread = rr_start_vcpu_thread,
- .kick_vcpu_thread = qemu_cpu_kick_rr_cpus,
+ .kick_vcpu_thread = rr_kick_vcpu_thread,
- .handle_interrupt = tcg_handle_interrupt,
+ .handle_interrupt = tcg_cpus_handle_interrupt,
};
diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c
index 86fd09545a..e335f9f155 100644
--- a/accel/tcg/tcg-cpus.c
+++ b/accel/tcg/tcg-cpus.c
@@ -38,12 +38,12 @@
/* common functionality among all TCG variants */
-void qemu_tcg_destroy_vcpu(CPUState *cpu)
+void tcg_cpus_destroy(CPUState *cpu)
{
cpu_thread_signal_destroyed(cpu);
}
-int tcg_cpu_exec(CPUState *cpu)
+int tcg_cpus_exec(CPUState *cpu)
{
int ret;
#ifdef CONFIG_PROFILER
@@ -64,7 +64,7 @@ int tcg_cpu_exec(CPUState *cpu)
}
/* mask must never be zero, except for A20 change call */
-void tcg_handle_interrupt(CPUState *cpu, int mask)
+void tcg_cpus_handle_interrupt(CPUState *cpu, int mask)
{
g_assert(qemu_mutex_iothread_locked());
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 04/25] i386: move kvm accel files into kvm/
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (2 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 03/25] accel/tcg: rename tcg-cpus functions to match module name Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 16:08 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 05/25] i386: move whpx accel files into whpx/ Claudio Fontana
` (22 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team,
Claudio Fontana, Anthony Perard, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
meson.build | 1 +
target/i386/cpu.h | 2 +-
target/i386/{ => kvm}/hyperv-proto.h | 0
target/i386/{ => kvm}/hyperv.h | 0
target/i386/{ => kvm}/kvm_i386.h | 0
target/i386/kvm/trace.h | 1 +
hw/i386/fw_cfg.c | 2 +-
hw/i386/intel_iommu.c | 2 +-
hw/i386/kvm/apic.c | 2 +-
hw/i386/kvm/clock.c | 2 +-
hw/i386/microvm.c | 2 +-
hw/i386/pc.c | 2 +-
hw/i386/x86.c | 2 +-
target/i386/cpu.c | 2 +-
target/i386/helper.c | 2 +-
target/i386/{ => kvm}/hyperv-stub.c | 0
target/i386/{ => kvm}/hyperv.c | 0
target/i386/{ => kvm}/kvm-stub.c | 0
target/i386/{ => kvm}/kvm.c | 0
target/i386/machine.c | 4 ++--
MAINTAINERS | 2 +-
target/i386/kvm/meson.build | 3 +++
target/i386/kvm/trace-events | 7 +++++++
target/i386/meson.build | 4 +---
target/i386/trace-events | 6 ------
25 files changed, 26 insertions(+), 22 deletions(-)
rename target/i386/{ => kvm}/hyperv-proto.h (100%)
rename target/i386/{ => kvm}/hyperv.h (100%)
rename target/i386/{ => kvm}/kvm_i386.h (100%)
create mode 100644 target/i386/kvm/trace.h
rename target/i386/{ => kvm}/hyperv-stub.c (100%)
rename target/i386/{ => kvm}/hyperv.c (100%)
rename target/i386/{ => kvm}/kvm-stub.c (100%)
rename target/i386/{ => kvm}/kvm.c (100%)
create mode 100644 target/i386/kvm/meson.build
create mode 100644 target/i386/kvm/trace-events
diff --git a/meson.build b/meson.build
index 732b29a1f3..d3f4aeeb32 100644
--- a/meson.build
+++ b/meson.build
@@ -1467,6 +1467,7 @@ trace_events_subdirs += [
'target/arm',
'target/hppa',
'target/i386',
+ 'target/i386/kvm',
'target/mips',
'target/ppc',
'target/riscv',
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 88e8586f8f..9ecda75aec 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -22,7 +22,7 @@
#include "sysemu/tcg.h"
#include "cpu-qom.h"
-#include "hyperv-proto.h"
+#include "kvm/hyperv-proto.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
diff --git a/target/i386/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h
similarity index 100%
rename from target/i386/hyperv-proto.h
rename to target/i386/kvm/hyperv-proto.h
diff --git a/target/i386/hyperv.h b/target/i386/kvm/hyperv.h
similarity index 100%
rename from target/i386/hyperv.h
rename to target/i386/kvm/hyperv.h
diff --git a/target/i386/kvm_i386.h b/target/i386/kvm/kvm_i386.h
similarity index 100%
rename from target/i386/kvm_i386.h
rename to target/i386/kvm/kvm_i386.h
diff --git a/target/i386/kvm/trace.h b/target/i386/kvm/trace.h
new file mode 100644
index 0000000000..46b75c6942
--- /dev/null
+++ b/target/i386/kvm/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-target_i386_kvm.h"
diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c
index e06579490c..fae1bb380f 100644
--- a/hw/i386/fw_cfg.c
+++ b/hw/i386/fw_cfg.c
@@ -21,7 +21,7 @@
#include "hw/timer/hpet.h"
#include "hw/nvram/fw_cfg.h"
#include "e820_memory_layout.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include CONFIG_DEVICES
struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 0cc71e4057..b4f5094259 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -37,7 +37,7 @@
#include "sysemu/kvm.h"
#include "sysemu/sysemu.h"
#include "hw/i386/apic_internal.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "migration/vmstate.h"
#include "trace.h"
diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c
index dd29906061..07bebc1282 100644
--- a/hw/i386/kvm/apic.c
+++ b/hw/i386/kvm/apic.c
@@ -17,7 +17,7 @@
#include "hw/pci/msi.h"
#include "sysemu/hw_accel.h"
#include "sysemu/kvm.h"
-#include "target/i386/kvm_i386.h"
+#include "kvm/kvm_i386.h"
static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,
int reg_id, uint32_t val)
diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c
index 24fe5091b6..2d8a366369 100644
--- a/hw/i386/kvm/clock.c
+++ b/hw/i386/kvm/clock.c
@@ -20,7 +20,7 @@
#include "sysemu/kvm.h"
#include "sysemu/runstate.h"
#include "sysemu/hw_accel.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "migration/vmstate.h"
#include "hw/sysbus.h"
#include "hw/kvm/clock.h"
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index 5428448b70..3ed6adff83 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -51,7 +51,7 @@
#include "cpu.h"
#include "elf.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "hw/xen/start_info.h"
#define MICROVM_QBOOT_FILENAME "qboot.rom"
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 9e29f3792b..e562f5e190 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -61,7 +61,7 @@
#include "sysemu/qtest.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "hw/xen/xen.h"
#include "hw/xen/start_info.h"
#include "ui/qemu-spice.h"
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 5944fc44ed..88d0c70e12 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -52,7 +52,7 @@
#include "elf.h"
#include "standard-headers/asm-x86/bootparam.h"
#include CONFIG_DEVICES
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#define BIOS_FILENAME "bios.bin"
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5a8c96072e..b9bd249c8f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -30,7 +30,7 @@
#include "sysemu/hvf.h"
#include "sysemu/cpus.h"
#include "sysemu/xen.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "sev_i386.h"
#include "qemu/error-report.h"
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 034f46bcc2..a1b3367ab2 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -24,7 +24,7 @@
#include "qemu/qemu-print.h"
#include "sysemu/kvm.h"
#include "sysemu/runstate.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#ifndef CONFIG_USER_ONLY
#include "sysemu/tcg.h"
#include "sysemu/hw_accel.h"
diff --git a/target/i386/hyperv-stub.c b/target/i386/kvm/hyperv-stub.c
similarity index 100%
rename from target/i386/hyperv-stub.c
rename to target/i386/kvm/hyperv-stub.c
diff --git a/target/i386/hyperv.c b/target/i386/kvm/hyperv.c
similarity index 100%
rename from target/i386/hyperv.c
rename to target/i386/kvm/hyperv.c
diff --git a/target/i386/kvm-stub.c b/target/i386/kvm/kvm-stub.c
similarity index 100%
rename from target/i386/kvm-stub.c
rename to target/i386/kvm/kvm-stub.c
diff --git a/target/i386/kvm.c b/target/i386/kvm/kvm.c
similarity index 100%
rename from target/i386/kvm.c
rename to target/i386/kvm/kvm.c
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 233e46bb70..1614e8c2f8 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -3,9 +3,9 @@
#include "exec/exec-all.h"
#include "hw/isa/isa.h"
#include "migration/cpu.h"
-#include "hyperv.h"
+#include "kvm/hyperv.h"
#include "hw/i386/x86.h"
-#include "kvm_i386.h"
+#include "kvm/kvm_i386.h"
#include "sysemu/kvm.h"
#include "sysemu/tcg.h"
diff --git a/MAINTAINERS b/MAINTAINERS
index 68bc160f41..5b3eced829 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -425,7 +425,7 @@ M: Paolo Bonzini <pbonzini@redhat.com>
M: Marcelo Tosatti <mtosatti@redhat.com>
L: kvm@vger.kernel.org
S: Supported
-F: target/i386/kvm.c
+F: target/i386/kvm/
F: scripts/kvm/vmxcap
Guest CPU Cores (other accelerators)
diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build
new file mode 100644
index 0000000000..1d66559187
--- /dev/null
+++ b/target/i386/kvm/meson.build
@@ -0,0 +1,3 @@
+i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
+i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
+i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c'))
diff --git a/target/i386/kvm/trace-events b/target/i386/kvm/trace-events
new file mode 100644
index 0000000000..b4e2d9e4ea
--- /dev/null
+++ b/target/i386/kvm/trace-events
@@ -0,0 +1,7 @@
+# See docs/devel/tracing.txt for syntax documentation.
+
+# kvm.c
+kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI %" PRIu32
+kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d"
+kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d"
+kvm_x86_update_msi_routes(int num) "Updated %d MSI routes"
diff --git a/target/i386/meson.build b/target/i386/meson.build
index a1a02f3e99..0209542a8a 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -18,7 +18,6 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files(
'smm_helper.c',
'svm_helper.c',
'translate.c'), if_false: files('tcg-stub.c'))
-i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c'))
i386_softmmu_ss = ss.source_set()
@@ -28,8 +27,6 @@ i386_softmmu_ss.add(files(
'machine.c',
'monitor.c',
))
-i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_false: files('hyperv-stub.c'))
-i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files(
'whpx-all.c',
'whpx-cpus.c',
@@ -42,6 +39,7 @@ i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c'))
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))
+subdir('kvm')
subdir('hvf')
target_arch += {'i386': i386_ss}
diff --git a/target/i386/trace-events b/target/i386/trace-events
index 789c700d4a..d166f9d5e0 100644
--- a/target/i386/trace-events
+++ b/target/i386/trace-events
@@ -1,11 +1,5 @@
# See docs/devel/tracing.txt for syntax documentation.
-# kvm.c
-kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI %" PRIu32
-kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d"
-kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d"
-kvm_x86_update_msi_routes(int num) "Updated %d MSI routes"
-
# sev.c
kvm_sev_init(void) ""
kvm_memcrypt_register_region(void *addr, size_t len) "addr %p len 0x%zu"
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 05/25] i386: move whpx accel files into whpx/
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (3 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 04/25] i386: move kvm accel files into kvm/ Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 16:09 ` Richard Henderson
2020-12-11 20:41 ` Eduardo Habkost
2020-12-11 8:31 ` [PATCH v11 06/25] i386: move hax accel files into hax/ Claudio Fontana
` (21 subsequent siblings)
26 siblings, 2 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team,
Claudio Fontana, Anthony Perard, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
target/i386/{ => whpx}/whp-dispatch.h | 0
target/i386/{ => whpx}/whpx-cpus.h | 0
target/i386/{ => whpx}/whpx-all.c | 0
target/i386/{ => whpx}/whpx-cpus.c | 0
MAINTAINERS | 5 +----
target/i386/meson.build | 5 +----
target/i386/whpx/meson.build | 4 ++++
7 files changed, 6 insertions(+), 8 deletions(-)
rename target/i386/{ => whpx}/whp-dispatch.h (100%)
rename target/i386/{ => whpx}/whpx-cpus.h (100%)
rename target/i386/{ => whpx}/whpx-all.c (100%)
rename target/i386/{ => whpx}/whpx-cpus.c (100%)
create mode 100644 target/i386/whpx/meson.build
diff --git a/target/i386/whp-dispatch.h b/target/i386/whpx/whp-dispatch.h
similarity index 100%
rename from target/i386/whp-dispatch.h
rename to target/i386/whpx/whp-dispatch.h
diff --git a/target/i386/whpx-cpus.h b/target/i386/whpx/whpx-cpus.h
similarity index 100%
rename from target/i386/whpx-cpus.h
rename to target/i386/whpx/whpx-cpus.h
diff --git a/target/i386/whpx-all.c b/target/i386/whpx/whpx-all.c
similarity index 100%
rename from target/i386/whpx-all.c
rename to target/i386/whpx/whpx-all.c
diff --git a/target/i386/whpx-cpus.c b/target/i386/whpx/whpx-cpus.c
similarity index 100%
rename from target/i386/whpx-cpus.c
rename to target/i386/whpx/whpx-cpus.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b3eced829..20e079f40c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -451,10 +451,7 @@ F: include/sysemu/hvf.h
WHPX CPUs
M: Sunil Muthuswamy <sunilmut@microsoft.com>
S: Supported
-F: target/i386/whpx-all.c
-F: target/i386/whpx-cpus.c
-F: target/i386/whp-dispatch.h
-F: accel/stubs/whpx-stub.c
+F: target/i386/whpx/
F: include/sysemu/whpx.h
Guest CPU Cores (Xen)
diff --git a/target/i386/meson.build b/target/i386/meson.build
index 0209542a8a..62cd042915 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -27,10 +27,6 @@ i386_softmmu_ss.add(files(
'machine.c',
'monitor.c',
))
-i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files(
- 'whpx-all.c',
- 'whpx-cpus.c',
-))
i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
'hax-all.c',
'hax-mem.c',
@@ -40,6 +36,7 @@ i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-po
i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))
subdir('kvm')
+subdir('whpx')
subdir('hvf')
target_arch += {'i386': i386_ss}
diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build
new file mode 100644
index 0000000000..94a72c8efc
--- /dev/null
+++ b/target/i386/whpx/meson.build
@@ -0,0 +1,4 @@
+i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files(
+ 'whpx-all.c',
+ 'whpx-cpus.c',
+))
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 06/25] i386: move hax accel files into hax/
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (4 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 05/25] i386: move whpx accel files into whpx/ Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 16:10 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 07/25] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Claudio Fontana
` (20 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team,
Claudio Fontana, Anthony Perard, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
target/i386/{ => hax}/hax-cpus.h | 0
target/i386/{ => hax}/hax-i386.h | 6 +++---
target/i386/{ => hax}/hax-interface.h | 0
target/i386/{ => hax}/hax-posix.h | 0
target/i386/{ => hax}/hax-windows.h | 0
target/i386/{ => hax}/hax-all.c | 0
target/i386/{ => hax}/hax-cpus.c | 0
target/i386/{ => hax}/hax-mem.c | 0
target/i386/{ => hax}/hax-posix.c | 0
target/i386/{ => hax}/hax-windows.c | 0
MAINTAINERS | 2 +-
target/i386/hax/meson.build | 7 +++++++
target/i386/meson.build | 8 +-------
13 files changed, 12 insertions(+), 11 deletions(-)
rename target/i386/{ => hax}/hax-cpus.h (100%)
rename target/i386/{ => hax}/hax-i386.h (95%)
rename target/i386/{ => hax}/hax-interface.h (100%)
rename target/i386/{ => hax}/hax-posix.h (100%)
rename target/i386/{ => hax}/hax-windows.h (100%)
rename target/i386/{ => hax}/hax-all.c (100%)
rename target/i386/{ => hax}/hax-cpus.c (100%)
rename target/i386/{ => hax}/hax-mem.c (100%)
rename target/i386/{ => hax}/hax-posix.c (100%)
rename target/i386/{ => hax}/hax-windows.c (100%)
create mode 100644 target/i386/hax/meson.build
diff --git a/target/i386/hax-cpus.h b/target/i386/hax/hax-cpus.h
similarity index 100%
rename from target/i386/hax-cpus.h
rename to target/i386/hax/hax-cpus.h
diff --git a/target/i386/hax-i386.h b/target/i386/hax/hax-i386.h
similarity index 95%
rename from target/i386/hax-i386.h
rename to target/i386/hax/hax-i386.h
index 48c4abe14e..efbb346238 100644
--- a/target/i386/hax-i386.h
+++ b/target/i386/hax/hax-i386.h
@@ -84,13 +84,13 @@ void hax_memory_init(void);
#ifdef CONFIG_POSIX
-#include "target/i386/hax-posix.h"
+#include "hax-posix.h"
#endif
#ifdef CONFIG_WIN32
-#include "target/i386/hax-windows.h"
+#include "hax-windows.h"
#endif
-#include "target/i386/hax-interface.h"
+#include "hax-interface.h"
#endif
diff --git a/target/i386/hax-interface.h b/target/i386/hax/hax-interface.h
similarity index 100%
rename from target/i386/hax-interface.h
rename to target/i386/hax/hax-interface.h
diff --git a/target/i386/hax-posix.h b/target/i386/hax/hax-posix.h
similarity index 100%
rename from target/i386/hax-posix.h
rename to target/i386/hax/hax-posix.h
diff --git a/target/i386/hax-windows.h b/target/i386/hax/hax-windows.h
similarity index 100%
rename from target/i386/hax-windows.h
rename to target/i386/hax/hax-windows.h
diff --git a/target/i386/hax-all.c b/target/i386/hax/hax-all.c
similarity index 100%
rename from target/i386/hax-all.c
rename to target/i386/hax/hax-all.c
diff --git a/target/i386/hax-cpus.c b/target/i386/hax/hax-cpus.c
similarity index 100%
rename from target/i386/hax-cpus.c
rename to target/i386/hax/hax-cpus.c
diff --git a/target/i386/hax-mem.c b/target/i386/hax/hax-mem.c
similarity index 100%
rename from target/i386/hax-mem.c
rename to target/i386/hax/hax-mem.c
diff --git a/target/i386/hax-posix.c b/target/i386/hax/hax-posix.c
similarity index 100%
rename from target/i386/hax-posix.c
rename to target/i386/hax/hax-posix.c
diff --git a/target/i386/hax-windows.c b/target/i386/hax/hax-windows.c
similarity index 100%
rename from target/i386/hax-windows.c
rename to target/i386/hax/hax-windows.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 20e079f40c..448593c904 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -491,7 +491,7 @@ W: https://github.com/intel/haxm/issues
S: Maintained
F: accel/stubs/hax-stub.c
F: include/sysemu/hax.h
-F: target/i386/hax-*
+F: target/i386/hax/
Hosts
-----
diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build
new file mode 100644
index 0000000000..77ea431b30
--- /dev/null
+++ b/target/i386/hax/meson.build
@@ -0,0 +1,7 @@
+i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
+ 'hax-all.c',
+ 'hax-mem.c',
+ 'hax-cpus.c',
+))
+i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c'))
+i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))
diff --git a/target/i386/meson.build b/target/i386/meson.build
index 62cd042915..284d52ab81 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -27,15 +27,9 @@ i386_softmmu_ss.add(files(
'machine.c',
'monitor.c',
))
-i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files(
- 'hax-all.c',
- 'hax-mem.c',
- 'hax-cpus.c',
-))
-i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c'))
-i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c'))
subdir('kvm')
+subdir('hax')
subdir('whpx')
subdir('hvf')
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 07/25] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (5 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 06/25] i386: move hax accel files into hax/ Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 08/25] i386: move TCG accel files into tcg/ Claudio Fontana
` (19 subsequent siblings)
26 siblings, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team,
Claudio Fontana, Anthony Perard, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 448593c904..f53f2678d8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -444,7 +444,6 @@ M: Cameron Esfahani <dirty@apple.com>
M: Roman Bolshakov <r.bolshakov@yadro.com>
W: https://wiki.qemu.org/Features/HVF
S: Maintained
-F: accel/stubs/hvf-stub.c
F: target/i386/hvf/
F: include/sysemu/hvf.h
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 08/25] i386: move TCG accel files into tcg/
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (6 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 07/25] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 16:10 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 09/25] i386: move cpu dump out of helper.c into cpu-dump.c Claudio Fontana
` (18 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team,
Claudio Fontana, Anthony Perard, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
target/i386/{ => tcg}/bpt_helper.c | 0
target/i386/{ => tcg}/cc_helper.c | 0
target/i386/{ => tcg}/excp_helper.c | 0
target/i386/{ => tcg}/fpu_helper.c | 0
target/i386/{ => tcg}/int_helper.c | 0
target/i386/{ => tcg}/mem_helper.c | 0
target/i386/{ => tcg}/misc_helper.c | 0
target/i386/{ => tcg}/mpx_helper.c | 0
target/i386/{ => tcg}/seg_helper.c | 0
target/i386/{ => tcg}/smm_helper.c | 0
target/i386/{ => tcg}/svm_helper.c | 0
target/i386/{ => tcg}/tcg-stub.c | 0
target/i386/{ => tcg}/translate.c | 0
target/i386/meson.build | 14 +-------------
target/i386/tcg/meson.build | 13 +++++++++++++
15 files changed, 14 insertions(+), 13 deletions(-)
rename target/i386/{ => tcg}/bpt_helper.c (100%)
rename target/i386/{ => tcg}/cc_helper.c (100%)
rename target/i386/{ => tcg}/excp_helper.c (100%)
rename target/i386/{ => tcg}/fpu_helper.c (100%)
rename target/i386/{ => tcg}/int_helper.c (100%)
rename target/i386/{ => tcg}/mem_helper.c (100%)
rename target/i386/{ => tcg}/misc_helper.c (100%)
rename target/i386/{ => tcg}/mpx_helper.c (100%)
rename target/i386/{ => tcg}/seg_helper.c (100%)
rename target/i386/{ => tcg}/smm_helper.c (100%)
rename target/i386/{ => tcg}/svm_helper.c (100%)
rename target/i386/{ => tcg}/tcg-stub.c (100%)
rename target/i386/{ => tcg}/translate.c (100%)
create mode 100644 target/i386/tcg/meson.build
diff --git a/target/i386/bpt_helper.c b/target/i386/tcg/bpt_helper.c
similarity index 100%
rename from target/i386/bpt_helper.c
rename to target/i386/tcg/bpt_helper.c
diff --git a/target/i386/cc_helper.c b/target/i386/tcg/cc_helper.c
similarity index 100%
rename from target/i386/cc_helper.c
rename to target/i386/tcg/cc_helper.c
diff --git a/target/i386/excp_helper.c b/target/i386/tcg/excp_helper.c
similarity index 100%
rename from target/i386/excp_helper.c
rename to target/i386/tcg/excp_helper.c
diff --git a/target/i386/fpu_helper.c b/target/i386/tcg/fpu_helper.c
similarity index 100%
rename from target/i386/fpu_helper.c
rename to target/i386/tcg/fpu_helper.c
diff --git a/target/i386/int_helper.c b/target/i386/tcg/int_helper.c
similarity index 100%
rename from target/i386/int_helper.c
rename to target/i386/tcg/int_helper.c
diff --git a/target/i386/mem_helper.c b/target/i386/tcg/mem_helper.c
similarity index 100%
rename from target/i386/mem_helper.c
rename to target/i386/tcg/mem_helper.c
diff --git a/target/i386/misc_helper.c b/target/i386/tcg/misc_helper.c
similarity index 100%
rename from target/i386/misc_helper.c
rename to target/i386/tcg/misc_helper.c
diff --git a/target/i386/mpx_helper.c b/target/i386/tcg/mpx_helper.c
similarity index 100%
rename from target/i386/mpx_helper.c
rename to target/i386/tcg/mpx_helper.c
diff --git a/target/i386/seg_helper.c b/target/i386/tcg/seg_helper.c
similarity index 100%
rename from target/i386/seg_helper.c
rename to target/i386/tcg/seg_helper.c
diff --git a/target/i386/smm_helper.c b/target/i386/tcg/smm_helper.c
similarity index 100%
rename from target/i386/smm_helper.c
rename to target/i386/tcg/smm_helper.c
diff --git a/target/i386/svm_helper.c b/target/i386/tcg/svm_helper.c
similarity index 100%
rename from target/i386/svm_helper.c
rename to target/i386/tcg/svm_helper.c
diff --git a/target/i386/tcg-stub.c b/target/i386/tcg/tcg-stub.c
similarity index 100%
rename from target/i386/tcg-stub.c
rename to target/i386/tcg/tcg-stub.c
diff --git a/target/i386/translate.c b/target/i386/tcg/translate.c
similarity index 100%
rename from target/i386/translate.c
rename to target/i386/tcg/translate.c
diff --git a/target/i386/meson.build b/target/i386/meson.build
index 284d52ab81..750471c9f3 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -5,19 +5,6 @@ i386_ss.add(files(
'helper.c',
'xsave_helper.c',
))
-i386_ss.add(when: 'CONFIG_TCG', if_true: files(
- 'bpt_helper.c',
- 'cc_helper.c',
- 'excp_helper.c',
- 'fpu_helper.c',
- 'int_helper.c',
- 'mem_helper.c',
- 'misc_helper.c',
- 'mpx_helper.c',
- 'seg_helper.c',
- 'smm_helper.c',
- 'svm_helper.c',
- 'translate.c'), if_false: files('tcg-stub.c'))
i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c'))
i386_softmmu_ss = ss.source_set()
@@ -32,6 +19,7 @@ subdir('kvm')
subdir('hax')
subdir('whpx')
subdir('hvf')
+subdir('tcg')
target_arch += {'i386': i386_ss}
target_softmmu_arch += {'i386': i386_softmmu_ss}
diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build
new file mode 100644
index 0000000000..02794226c2
--- /dev/null
+++ b/target/i386/tcg/meson.build
@@ -0,0 +1,13 @@
+i386_ss.add(when: 'CONFIG_TCG', if_true: files(
+ 'bpt_helper.c',
+ 'cc_helper.c',
+ 'excp_helper.c',
+ 'fpu_helper.c',
+ 'int_helper.c',
+ 'mem_helper.c',
+ 'misc_helper.c',
+ 'mpx_helper.c',
+ 'seg_helper.c',
+ 'smm_helper.c',
+ 'svm_helper.c',
+ 'translate.c'), if_false: files('tcg-stub.c'))
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 09/25] i386: move cpu dump out of helper.c into cpu-dump.c
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (7 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 08/25] i386: move TCG accel files into tcg/ Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 16:13 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 10/25] i386: move TCG cpu class initialization out of helper.c Claudio Fontana
` (17 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team,
Claudio Fontana, Anthony Perard, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
target/i386/cpu.h | 1 +
target/i386/cpu-dump.c | 537 ++++++++++++++++++++++++++++++++++++++++
target/i386/helper.c | 514 --------------------------------------
target/i386/meson.build | 1 +
4 files changed, 539 insertions(+), 514 deletions(-)
create mode 100644 target/i386/cpu-dump.c
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 9ecda75aec..d6ed45c5d7 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2232,6 +2232,7 @@ void enable_compat_apic_id_mode(void);
#define APIC_DEFAULT_ADDRESS 0xfee00000
#define APIC_SPACE_SIZE 0x100000
+/* cpu-dump.c */
void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
/* cpu.c */
diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c
new file mode 100644
index 0000000000..aac21f1f60
--- /dev/null
+++ b/target/i386/cpu-dump.c
@@ -0,0 +1,537 @@
+/*
+ * i386 CPU dump to FILE
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/qemu-print.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/i386/apic_internal.h"
+#endif
+
+/***********************************************************/
+/* x86 debug */
+
+static const char *cc_op_str[CC_OP_NB] = {
+ "DYNAMIC",
+ "EFLAGS",
+
+ "MULB",
+ "MULW",
+ "MULL",
+ "MULQ",
+
+ "ADDB",
+ "ADDW",
+ "ADDL",
+ "ADDQ",
+
+ "ADCB",
+ "ADCW",
+ "ADCL",
+ "ADCQ",
+
+ "SUBB",
+ "SUBW",
+ "SUBL",
+ "SUBQ",
+
+ "SBBB",
+ "SBBW",
+ "SBBL",
+ "SBBQ",
+
+ "LOGICB",
+ "LOGICW",
+ "LOGICL",
+ "LOGICQ",
+
+ "INCB",
+ "INCW",
+ "INCL",
+ "INCQ",
+
+ "DECB",
+ "DECW",
+ "DECL",
+ "DECQ",
+
+ "SHLB",
+ "SHLW",
+ "SHLL",
+ "SHLQ",
+
+ "SARB",
+ "SARW",
+ "SARL",
+ "SARQ",
+
+ "BMILGB",
+ "BMILGW",
+ "BMILGL",
+ "BMILGQ",
+
+ "ADCX",
+ "ADOX",
+ "ADCOX",
+
+ "CLR",
+};
+
+static void
+cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f,
+ const char *name, struct SegmentCache *sc)
+{
+#ifdef TARGET_X86_64
+ if (env->hflags & HF_CS64_MASK) {
+ qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name,
+ sc->selector, sc->base, sc->limit,
+ sc->flags & 0x00ffff00);
+ } else
+#endif
+ {
+ qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector,
+ (uint32_t)sc->base, sc->limit,
+ sc->flags & 0x00ffff00);
+ }
+
+ if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
+ goto done;
+
+ qemu_fprintf(f, " DPL=%d ",
+ (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
+ if (sc->flags & DESC_S_MASK) {
+ if (sc->flags & DESC_CS_MASK) {
+ qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" :
+ ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16"));
+ qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
+ (sc->flags & DESC_R_MASK) ? 'R' : '-');
+ } else {
+ qemu_fprintf(f, (sc->flags & DESC_B_MASK
+ || env->hflags & HF_LMA_MASK)
+ ? "DS " : "DS16");
+ qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
+ (sc->flags & DESC_W_MASK) ? 'W' : '-');
+ }
+ qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-');
+ } else {
+ static const char *sys_type_name[2][16] = {
+ { /* 32 bit mode */
+ "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
+ "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
+ "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
+ "CallGate32", "Reserved", "IntGate32", "TrapGate32"
+ },
+ { /* 64 bit mode */
+ "<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
+ "Reserved", "Reserved", "Reserved", "Reserved",
+ "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
+ "Reserved", "IntGate64", "TrapGate64"
+ }
+ };
+ qemu_fprintf(f, "%s",
+ sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
+ [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]);
+ }
+done:
+ qemu_fprintf(f, "\n");
+}
+
+#ifndef CONFIG_USER_ONLY
+
+/* ARRAY_SIZE check is not required because
+ * DeliveryMode(dm) has a size of 3 bit.
+ */
+static inline const char *dm2str(uint32_t dm)
+{
+ static const char *str[] = {
+ "Fixed",
+ "...",
+ "SMI",
+ "...",
+ "NMI",
+ "INIT",
+ "...",
+ "ExtINT"
+ };
+ return str[dm];
+}
+
+static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer)
+{
+ uint32_t dm = (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT;
+ qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s",
+ name, lvt,
+ lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi",
+ lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge",
+ lvt & APIC_LVT_MASKED ? "masked" : "",
+ lvt & APIC_LVT_DELIV_STS ? "pending" : "",
+ !is_timer ?
+ "" : lvt & APIC_LVT_TIMER_PERIODIC ?
+ "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ?
+ "tsc-deadline" : "one-shot",
+ dm2str(dm));
+ if (dm != APIC_DM_NMI) {
+ qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK);
+ } else {
+ qemu_printf("\n");
+ }
+}
+
+/* ARRAY_SIZE check is not required because
+ * destination shorthand has a size of 2 bit.
+ */
+static inline const char *shorthand2str(uint32_t shorthand)
+{
+ const char *str[] = {
+ "no-shorthand", "self", "all-self", "all"
+ };
+ return str[shorthand];
+}
+
+static inline uint8_t divider_conf(uint32_t divide_conf)
+{
+ uint8_t divide_val = ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3);
+
+ return divide_val == 7 ? 1 : 2 << divide_val;
+}
+
+static inline void mask2str(char *str, uint32_t val, uint8_t size)
+{
+ while (size--) {
+ *str++ = (val >> size) & 1 ? '1' : '0';
+ }
+ *str = 0;
+}
+
+#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16
+
+static void dump_apic_icr(APICCommonState *s, CPUX86State *env)
+{
+ uint32_t icr = s->icr[0], icr2 = s->icr[1];
+ uint8_t dest_shorthand = \
+ (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT;
+ bool logical_mod = icr & APIC_ICR_DEST_MOD;
+ char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1];
+ uint32_t dest_field;
+ bool x2apic;
+
+ qemu_printf("ICR\t 0x%08x %s %s %s %s\n",
+ icr,
+ logical_mod ? "logical" : "physical",
+ icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge",
+ icr & APIC_ICR_LEVEL ? "assert" : "de-assert",
+ shorthand2str(dest_shorthand));
+
+ qemu_printf("ICR2\t 0x%08x", icr2);
+ if (dest_shorthand != 0) {
+ qemu_printf("\n");
+ return;
+ }
+ x2apic = env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC;
+ dest_field = x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT;
+
+ if (!logical_mod) {
+ if (x2apic) {
+ qemu_printf(" cpu %u (X2APIC ID)\n", dest_field);
+ } else {
+ qemu_printf(" cpu %u (APIC ID)\n",
+ dest_field & APIC_LOGDEST_XAPIC_ID);
+ }
+ return;
+ }
+
+ if (s->dest_mode == 0xf) { /* flat mode */
+ mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8);
+ qemu_printf(" mask %s (APIC ID)\n", apic_id_str);
+ } else if (s->dest_mode == 0) { /* cluster mode */
+ if (x2apic) {
+ mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16);
+ qemu_printf(" cluster %u mask %s (X2APIC ID)\n",
+ dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_str);
+ } else {
+ mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4);
+ qemu_printf(" cluster %u mask %s (APIC ID)\n",
+ dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_str);
+ }
+ }
+}
+
+static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab,
+ uint32_t *tmr_tab)
+{
+ int i, empty = true;
+
+ qemu_printf("%s\t ", name);
+ for (i = 0; i < 256; i++) {
+ if (apic_get_bit(ireg_tab, i)) {
+ qemu_printf("%u%s ", i,
+ apic_get_bit(tmr_tab, i) ? "(level)" : "");
+ empty = false;
+ }
+ }
+ qemu_printf("%s\n", empty ? "(none)" : "");
+}
+
+void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ APICCommonState *s = APIC_COMMON(cpu->apic_state);
+ if (!s) {
+ qemu_printf("local apic state not available\n");
+ return;
+ }
+ uint32_t *lvt = s->lvt;
+
+ qemu_printf("dumping local APIC state for CPU %-2u\n\n",
+ CPU(cpu)->cpu_index);
+ dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false);
+ dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false);
+ dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false);
+ dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false);
+ dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false);
+ dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true);
+
+ qemu_printf("Timer\t DCR=0x%x (divide by %u) initial_count = %u"
+ " current_count = %u\n",
+ s->divide_conf & APIC_DCR_MASK,
+ divider_conf(s->divide_conf),
+ s->initial_count, apic_get_current_count(s));
+
+ qemu_printf("SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n",
+ s->spurious_vec,
+ s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disabled",
+ s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off",
+ s->spurious_vec & APIC_VECTOR_MASK);
+
+ dump_apic_icr(s, &cpu->env);
+
+ qemu_printf("ESR\t 0x%08x\n", s->esr);
+
+ dump_apic_interrupt("ISR", s->isr, s->tmr);
+ dump_apic_interrupt("IRR", s->irr, s->tmr);
+
+ qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x",
+ s->arb_id, s->tpr, s->dest_mode, s->log_dest);
+ if (s->dest_mode == 0) {
+ qemu_printf("(cluster %u: id %u)",
+ s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT,
+ s->log_dest & APIC_LOGDEST_XAPIC_ID);
+ }
+ qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s));
+}
+#else
+void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
+{
+}
+#endif /* !CONFIG_USER_ONLY */
+
+#define DUMP_CODE_BYTES_TOTAL 50
+#define DUMP_CODE_BYTES_BACKWARD 20
+
+void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+ int eflags, i, nb;
+ char cc_op_name[32];
+ static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
+
+ eflags = cpu_compute_eflags(env);
+#ifdef TARGET_X86_64
+ if (env->hflags & HF_CS64_MASK) {
+ qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
+ "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
+ "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
+ "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
+ "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
+ env->regs[R_EAX],
+ env->regs[R_EBX],
+ env->regs[R_ECX],
+ env->regs[R_EDX],
+ env->regs[R_ESI],
+ env->regs[R_EDI],
+ env->regs[R_EBP],
+ env->regs[R_ESP],
+ env->regs[8],
+ env->regs[9],
+ env->regs[10],
+ env->regs[11],
+ env->regs[12],
+ env->regs[13],
+ env->regs[14],
+ env->regs[15],
+ env->eip, eflags,
+ eflags & DF_MASK ? 'D' : '-',
+ eflags & CC_O ? 'O' : '-',
+ eflags & CC_S ? 'S' : '-',
+ eflags & CC_Z ? 'Z' : '-',
+ eflags & CC_A ? 'A' : '-',
+ eflags & CC_P ? 'P' : '-',
+ eflags & CC_C ? 'C' : '-',
+ env->hflags & HF_CPL_MASK,
+ (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
+ (env->a20_mask >> 20) & 1,
+ (env->hflags >> HF_SMM_SHIFT) & 1,
+ cs->halted);
+ } else
+#endif
+ {
+ qemu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
+ "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
+ "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
+ (uint32_t)env->regs[R_EAX],
+ (uint32_t)env->regs[R_EBX],
+ (uint32_t)env->regs[R_ECX],
+ (uint32_t)env->regs[R_EDX],
+ (uint32_t)env->regs[R_ESI],
+ (uint32_t)env->regs[R_EDI],
+ (uint32_t)env->regs[R_EBP],
+ (uint32_t)env->regs[R_ESP],
+ (uint32_t)env->eip, eflags,
+ eflags & DF_MASK ? 'D' : '-',
+ eflags & CC_O ? 'O' : '-',
+ eflags & CC_S ? 'S' : '-',
+ eflags & CC_Z ? 'Z' : '-',
+ eflags & CC_A ? 'A' : '-',
+ eflags & CC_P ? 'P' : '-',
+ eflags & CC_C ? 'C' : '-',
+ env->hflags & HF_CPL_MASK,
+ (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
+ (env->a20_mask >> 20) & 1,
+ (env->hflags >> HF_SMM_SHIFT) & 1,
+ cs->halted);
+ }
+
+ for(i = 0; i < 6; i++) {
+ cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]);
+ }
+ cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt);
+ cpu_x86_dump_seg_cache(env, f, "TR", &env->tr);
+
+#ifdef TARGET_X86_64
+ if (env->hflags & HF_LMA_MASK) {
+ qemu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
+ env->gdt.base, env->gdt.limit);
+ qemu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
+ env->idt.base, env->idt.limit);
+ qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
+ (uint32_t)env->cr[0],
+ env->cr[2],
+ env->cr[3],
+ (uint32_t)env->cr[4]);
+ for(i = 0; i < 4; i++)
+ qemu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
+ qemu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
+ env->dr[6], env->dr[7]);
+ } else
+#endif
+ {
+ qemu_fprintf(f, "GDT= %08x %08x\n",
+ (uint32_t)env->gdt.base, env->gdt.limit);
+ qemu_fprintf(f, "IDT= %08x %08x\n",
+ (uint32_t)env->idt.base, env->idt.limit);
+ qemu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
+ (uint32_t)env->cr[0],
+ (uint32_t)env->cr[2],
+ (uint32_t)env->cr[3],
+ (uint32_t)env->cr[4]);
+ for(i = 0; i < 4; i++) {
+ qemu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]);
+ }
+ qemu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n",
+ env->dr[6], env->dr[7]);
+ }
+ if (flags & CPU_DUMP_CCOP) {
+ if ((unsigned)env->cc_op < CC_OP_NB)
+ snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
+ else
+ snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
+#ifdef TARGET_X86_64
+ if (env->hflags & HF_CS64_MASK) {
+ qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
+ env->cc_src, env->cc_dst,
+ cc_op_name);
+ } else
+#endif
+ {
+ qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
+ (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
+ cc_op_name);
+ }
+ }
+ qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
+ if (flags & CPU_DUMP_FPU) {
+ int fptag;
+ fptag = 0;
+ for(i = 0; i < 8; i++) {
+ fptag |= ((!env->fptags[i]) << i);
+ }
+ update_mxcsr_from_sse_status(env);
+ qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
+ env->fpuc,
+ (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
+ env->fpstt,
+ fptag,
+ env->mxcsr);
+ for(i=0;i<8;i++) {
+ CPU_LDoubleU u;
+ u.d = env->fpregs[i].d;
+ qemu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
+ i, u.l.lower, u.l.upper);
+ if ((i & 1) == 1)
+ qemu_fprintf(f, "\n");
+ else
+ qemu_fprintf(f, " ");
+ }
+ if (env->hflags & HF_CS64_MASK)
+ nb = 16;
+ else
+ nb = 8;
+ for(i=0;i<nb;i++) {
+ qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
+ i,
+ env->xmm_regs[i].ZMM_L(3),
+ env->xmm_regs[i].ZMM_L(2),
+ env->xmm_regs[i].ZMM_L(1),
+ env->xmm_regs[i].ZMM_L(0));
+ if ((i & 1) == 1)
+ qemu_fprintf(f, "\n");
+ else
+ qemu_fprintf(f, " ");
+ }
+ }
+ if (flags & CPU_DUMP_CODE) {
+ target_ulong base = env->segs[R_CS].base + env->eip;
+ target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD);
+ uint8_t code;
+ char codestr[3];
+
+ qemu_fprintf(f, "Code=");
+ for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
+ if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
+ snprintf(codestr, sizeof(codestr), "%02x", code);
+ } else {
+ snprintf(codestr, sizeof(codestr), "??");
+ }
+ qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "",
+ i == offs ? "<" : "", codestr, i == offs ? ">" : "");
+ }
+ qemu_fprintf(f, "\n");
+ }
+}
diff --git a/target/i386/helper.c b/target/i386/helper.c
index a1b3367ab2..6e7e0f507c 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -21,8 +21,6 @@
#include "qapi/qapi-events-run-state.h"
#include "cpu.h"
#include "exec/exec-all.h"
-#include "qemu/qemu-print.h"
-#include "sysemu/kvm.h"
#include "sysemu/runstate.h"
#include "kvm/kvm_i386.h"
#ifndef CONFIG_USER_ONLY
@@ -88,518 +86,6 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env)
return 0;
}
-/***********************************************************/
-/* x86 debug */
-
-static const char *cc_op_str[CC_OP_NB] = {
- "DYNAMIC",
- "EFLAGS",
-
- "MULB",
- "MULW",
- "MULL",
- "MULQ",
-
- "ADDB",
- "ADDW",
- "ADDL",
- "ADDQ",
-
- "ADCB",
- "ADCW",
- "ADCL",
- "ADCQ",
-
- "SUBB",
- "SUBW",
- "SUBL",
- "SUBQ",
-
- "SBBB",
- "SBBW",
- "SBBL",
- "SBBQ",
-
- "LOGICB",
- "LOGICW",
- "LOGICL",
- "LOGICQ",
-
- "INCB",
- "INCW",
- "INCL",
- "INCQ",
-
- "DECB",
- "DECW",
- "DECL",
- "DECQ",
-
- "SHLB",
- "SHLW",
- "SHLL",
- "SHLQ",
-
- "SARB",
- "SARW",
- "SARL",
- "SARQ",
-
- "BMILGB",
- "BMILGW",
- "BMILGL",
- "BMILGQ",
-
- "ADCX",
- "ADOX",
- "ADCOX",
-
- "CLR",
-};
-
-static void
-cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f,
- const char *name, struct SegmentCache *sc)
-{
-#ifdef TARGET_X86_64
- if (env->hflags & HF_CS64_MASK) {
- qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name,
- sc->selector, sc->base, sc->limit,
- sc->flags & 0x00ffff00);
- } else
-#endif
- {
- qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector,
- (uint32_t)sc->base, sc->limit,
- sc->flags & 0x00ffff00);
- }
-
- if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
- goto done;
-
- qemu_fprintf(f, " DPL=%d ",
- (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
- if (sc->flags & DESC_S_MASK) {
- if (sc->flags & DESC_CS_MASK) {
- qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" :
- ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16"));
- qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
- (sc->flags & DESC_R_MASK) ? 'R' : '-');
- } else {
- qemu_fprintf(f, (sc->flags & DESC_B_MASK
- || env->hflags & HF_LMA_MASK)
- ? "DS " : "DS16");
- qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
- (sc->flags & DESC_W_MASK) ? 'W' : '-');
- }
- qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-');
- } else {
- static const char *sys_type_name[2][16] = {
- { /* 32 bit mode */
- "Reserved", "TSS16-avl", "LDT", "TSS16-busy",
- "CallGate16", "TaskGate", "IntGate16", "TrapGate16",
- "Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
- "CallGate32", "Reserved", "IntGate32", "TrapGate32"
- },
- { /* 64 bit mode */
- "<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
- "Reserved", "Reserved", "Reserved", "Reserved",
- "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
- "Reserved", "IntGate64", "TrapGate64"
- }
- };
- qemu_fprintf(f, "%s",
- sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
- [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]);
- }
-done:
- qemu_fprintf(f, "\n");
-}
-
-#ifndef CONFIG_USER_ONLY
-
-/* ARRAY_SIZE check is not required because
- * DeliveryMode(dm) has a size of 3 bit.
- */
-static inline const char *dm2str(uint32_t dm)
-{
- static const char *str[] = {
- "Fixed",
- "...",
- "SMI",
- "...",
- "NMI",
- "INIT",
- "...",
- "ExtINT"
- };
- return str[dm];
-}
-
-static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer)
-{
- uint32_t dm = (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT;
- qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s",
- name, lvt,
- lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi",
- lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge",
- lvt & APIC_LVT_MASKED ? "masked" : "",
- lvt & APIC_LVT_DELIV_STS ? "pending" : "",
- !is_timer ?
- "" : lvt & APIC_LVT_TIMER_PERIODIC ?
- "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ?
- "tsc-deadline" : "one-shot",
- dm2str(dm));
- if (dm != APIC_DM_NMI) {
- qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK);
- } else {
- qemu_printf("\n");
- }
-}
-
-/* ARRAY_SIZE check is not required because
- * destination shorthand has a size of 2 bit.
- */
-static inline const char *shorthand2str(uint32_t shorthand)
-{
- const char *str[] = {
- "no-shorthand", "self", "all-self", "all"
- };
- return str[shorthand];
-}
-
-static inline uint8_t divider_conf(uint32_t divide_conf)
-{
- uint8_t divide_val = ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3);
-
- return divide_val == 7 ? 1 : 2 << divide_val;
-}
-
-static inline void mask2str(char *str, uint32_t val, uint8_t size)
-{
- while (size--) {
- *str++ = (val >> size) & 1 ? '1' : '0';
- }
- *str = 0;
-}
-
-#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16
-
-static void dump_apic_icr(APICCommonState *s, CPUX86State *env)
-{
- uint32_t icr = s->icr[0], icr2 = s->icr[1];
- uint8_t dest_shorthand = \
- (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT;
- bool logical_mod = icr & APIC_ICR_DEST_MOD;
- char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1];
- uint32_t dest_field;
- bool x2apic;
-
- qemu_printf("ICR\t 0x%08x %s %s %s %s\n",
- icr,
- logical_mod ? "logical" : "physical",
- icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge",
- icr & APIC_ICR_LEVEL ? "assert" : "de-assert",
- shorthand2str(dest_shorthand));
-
- qemu_printf("ICR2\t 0x%08x", icr2);
- if (dest_shorthand != 0) {
- qemu_printf("\n");
- return;
- }
- x2apic = env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC;
- dest_field = x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT;
-
- if (!logical_mod) {
- if (x2apic) {
- qemu_printf(" cpu %u (X2APIC ID)\n", dest_field);
- } else {
- qemu_printf(" cpu %u (APIC ID)\n",
- dest_field & APIC_LOGDEST_XAPIC_ID);
- }
- return;
- }
-
- if (s->dest_mode == 0xf) { /* flat mode */
- mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8);
- qemu_printf(" mask %s (APIC ID)\n", apic_id_str);
- } else if (s->dest_mode == 0) { /* cluster mode */
- if (x2apic) {
- mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16);
- qemu_printf(" cluster %u mask %s (X2APIC ID)\n",
- dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_str);
- } else {
- mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4);
- qemu_printf(" cluster %u mask %s (APIC ID)\n",
- dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_str);
- }
- }
-}
-
-static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab,
- uint32_t *tmr_tab)
-{
- int i, empty = true;
-
- qemu_printf("%s\t ", name);
- for (i = 0; i < 256; i++) {
- if (apic_get_bit(ireg_tab, i)) {
- qemu_printf("%u%s ", i,
- apic_get_bit(tmr_tab, i) ? "(level)" : "");
- empty = false;
- }
- }
- qemu_printf("%s\n", empty ? "(none)" : "");
-}
-
-void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
-{
- X86CPU *cpu = X86_CPU(cs);
- APICCommonState *s = APIC_COMMON(cpu->apic_state);
- if (!s) {
- qemu_printf("local apic state not available\n");
- return;
- }
- uint32_t *lvt = s->lvt;
-
- qemu_printf("dumping local APIC state for CPU %-2u\n\n",
- CPU(cpu)->cpu_index);
- dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false);
- dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false);
- dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false);
- dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false);
- dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false);
- dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true);
-
- qemu_printf("Timer\t DCR=0x%x (divide by %u) initial_count = %u"
- " current_count = %u\n",
- s->divide_conf & APIC_DCR_MASK,
- divider_conf(s->divide_conf),
- s->initial_count, apic_get_current_count(s));
-
- qemu_printf("SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n",
- s->spurious_vec,
- s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disabled",
- s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off",
- s->spurious_vec & APIC_VECTOR_MASK);
-
- dump_apic_icr(s, &cpu->env);
-
- qemu_printf("ESR\t 0x%08x\n", s->esr);
-
- dump_apic_interrupt("ISR", s->isr, s->tmr);
- dump_apic_interrupt("IRR", s->irr, s->tmr);
-
- qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x",
- s->arb_id, s->tpr, s->dest_mode, s->log_dest);
- if (s->dest_mode == 0) {
- qemu_printf("(cluster %u: id %u)",
- s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT,
- s->log_dest & APIC_LOGDEST_XAPIC_ID);
- }
- qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s));
-}
-#else
-void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
-{
-}
-#endif /* !CONFIG_USER_ONLY */
-
-#define DUMP_CODE_BYTES_TOTAL 50
-#define DUMP_CODE_BYTES_BACKWARD 20
-
-void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
- int eflags, i, nb;
- char cc_op_name[32];
- static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
-
- eflags = cpu_compute_eflags(env);
-#ifdef TARGET_X86_64
- if (env->hflags & HF_CS64_MASK) {
- qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
- "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
- "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
- "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
- "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
- env->regs[R_EAX],
- env->regs[R_EBX],
- env->regs[R_ECX],
- env->regs[R_EDX],
- env->regs[R_ESI],
- env->regs[R_EDI],
- env->regs[R_EBP],
- env->regs[R_ESP],
- env->regs[8],
- env->regs[9],
- env->regs[10],
- env->regs[11],
- env->regs[12],
- env->regs[13],
- env->regs[14],
- env->regs[15],
- env->eip, eflags,
- eflags & DF_MASK ? 'D' : '-',
- eflags & CC_O ? 'O' : '-',
- eflags & CC_S ? 'S' : '-',
- eflags & CC_Z ? 'Z' : '-',
- eflags & CC_A ? 'A' : '-',
- eflags & CC_P ? 'P' : '-',
- eflags & CC_C ? 'C' : '-',
- env->hflags & HF_CPL_MASK,
- (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
- (env->a20_mask >> 20) & 1,
- (env->hflags >> HF_SMM_SHIFT) & 1,
- cs->halted);
- } else
-#endif
- {
- qemu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
- "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
- "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
- (uint32_t)env->regs[R_EAX],
- (uint32_t)env->regs[R_EBX],
- (uint32_t)env->regs[R_ECX],
- (uint32_t)env->regs[R_EDX],
- (uint32_t)env->regs[R_ESI],
- (uint32_t)env->regs[R_EDI],
- (uint32_t)env->regs[R_EBP],
- (uint32_t)env->regs[R_ESP],
- (uint32_t)env->eip, eflags,
- eflags & DF_MASK ? 'D' : '-',
- eflags & CC_O ? 'O' : '-',
- eflags & CC_S ? 'S' : '-',
- eflags & CC_Z ? 'Z' : '-',
- eflags & CC_A ? 'A' : '-',
- eflags & CC_P ? 'P' : '-',
- eflags & CC_C ? 'C' : '-',
- env->hflags & HF_CPL_MASK,
- (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
- (env->a20_mask >> 20) & 1,
- (env->hflags >> HF_SMM_SHIFT) & 1,
- cs->halted);
- }
-
- for(i = 0; i < 6; i++) {
- cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]);
- }
- cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt);
- cpu_x86_dump_seg_cache(env, f, "TR", &env->tr);
-
-#ifdef TARGET_X86_64
- if (env->hflags & HF_LMA_MASK) {
- qemu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
- env->gdt.base, env->gdt.limit);
- qemu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
- env->idt.base, env->idt.limit);
- qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
- (uint32_t)env->cr[0],
- env->cr[2],
- env->cr[3],
- (uint32_t)env->cr[4]);
- for(i = 0; i < 4; i++)
- qemu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
- qemu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
- env->dr[6], env->dr[7]);
- } else
-#endif
- {
- qemu_fprintf(f, "GDT= %08x %08x\n",
- (uint32_t)env->gdt.base, env->gdt.limit);
- qemu_fprintf(f, "IDT= %08x %08x\n",
- (uint32_t)env->idt.base, env->idt.limit);
- qemu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
- (uint32_t)env->cr[0],
- (uint32_t)env->cr[2],
- (uint32_t)env->cr[3],
- (uint32_t)env->cr[4]);
- for(i = 0; i < 4; i++) {
- qemu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]);
- }
- qemu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n",
- env->dr[6], env->dr[7]);
- }
- if (flags & CPU_DUMP_CCOP) {
- if ((unsigned)env->cc_op < CC_OP_NB)
- snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
- else
- snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
-#ifdef TARGET_X86_64
- if (env->hflags & HF_CS64_MASK) {
- qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
- env->cc_src, env->cc_dst,
- cc_op_name);
- } else
-#endif
- {
- qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
- (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
- cc_op_name);
- }
- }
- qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
- if (flags & CPU_DUMP_FPU) {
- int fptag;
- fptag = 0;
- for(i = 0; i < 8; i++) {
- fptag |= ((!env->fptags[i]) << i);
- }
- update_mxcsr_from_sse_status(env);
- qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
- env->fpuc,
- (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
- env->fpstt,
- fptag,
- env->mxcsr);
- for(i=0;i<8;i++) {
- CPU_LDoubleU u;
- u.d = env->fpregs[i].d;
- qemu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
- i, u.l.lower, u.l.upper);
- if ((i & 1) == 1)
- qemu_fprintf(f, "\n");
- else
- qemu_fprintf(f, " ");
- }
- if (env->hflags & HF_CS64_MASK)
- nb = 16;
- else
- nb = 8;
- for(i=0;i<nb;i++) {
- qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
- i,
- env->xmm_regs[i].ZMM_L(3),
- env->xmm_regs[i].ZMM_L(2),
- env->xmm_regs[i].ZMM_L(1),
- env->xmm_regs[i].ZMM_L(0));
- if ((i & 1) == 1)
- qemu_fprintf(f, "\n");
- else
- qemu_fprintf(f, " ");
- }
- }
- if (flags & CPU_DUMP_CODE) {
- target_ulong base = env->segs[R_CS].base + env->eip;
- target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD);
- uint8_t code;
- char codestr[3];
-
- qemu_fprintf(f, "Code=");
- for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
- if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
- snprintf(codestr, sizeof(codestr), "%02x", code);
- } else {
- snprintf(codestr, sizeof(codestr), "??");
- }
- qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "",
- i == offs ? "<" : "", codestr, i == offs ? ">" : "");
- }
- qemu_fprintf(f, "\n");
- }
-}
-
/***********************************************************/
/* x86 mmu */
/* XXX: add PGE support */
diff --git a/target/i386/meson.build b/target/i386/meson.build
index 750471c9f3..c4bf20b319 100644
--- a/target/i386/meson.build
+++ b/target/i386/meson.build
@@ -4,6 +4,7 @@ i386_ss.add(files(
'gdbstub.c',
'helper.c',
'xsave_helper.c',
+ 'cpu-dump.c',
))
i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('sev-stub.c'))
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 10/25] i386: move TCG cpu class initialization out of helper.c
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (8 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 09/25] i386: move cpu dump out of helper.c into cpu-dump.c Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 16:44 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 11/25] tcg: cpu_exec_{enter,exit} helpers Claudio Fontana
` (16 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Jason Wang, Marcelo Tosatti, qemu-devel, Peter Xu,
Dario Faggioli, Cameron Esfahani, haxm-team, Claudio Fontana,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/i386/cpu.h | 97 ++---------------------------
target/i386/tcg/helper-tcg.h | 112 ++++++++++++++++++++++++++++++++++
target/i386/tcg/tcg-cpu.h | 15 +++++
target/i386/cpu.c | 33 ++++------
target/i386/helper.c | 23 -------
target/i386/tcg/bpt_helper.c | 1 +
target/i386/tcg/cc_helper.c | 1 +
target/i386/tcg/excp_helper.c | 1 +
target/i386/tcg/fpu_helper.c | 33 +++++-----
target/i386/tcg/int_helper.c | 1 +
target/i386/tcg/mem_helper.c | 1 +
target/i386/tcg/misc_helper.c | 1 +
target/i386/tcg/mpx_helper.c | 1 +
target/i386/tcg/seg_helper.c | 1 +
target/i386/tcg/smm_helper.c | 2 +
target/i386/tcg/svm_helper.c | 1 +
target/i386/tcg/tcg-cpu.c | 71 +++++++++++++++++++++
target/i386/tcg/translate.c | 1 +
target/i386/tcg/meson.build | 1 +
19 files changed, 244 insertions(+), 153 deletions(-)
create mode 100644 target/i386/tcg/helper-tcg.h
create mode 100644 target/i386/tcg/tcg-cpu.h
create mode 100644 target/i386/tcg/tcg-cpu.c
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d6ed45c5d7..a0d64613dc 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -31,9 +31,6 @@
#define KVM_HAVE_MCE_INJECTION 1
-/* Maximum instruction code size */
-#define TARGET_MAX_INSN_SIZE 16
-
/* support for self modifying code even if the modified instruction is
close to the modifying instruction */
#define TARGET_HAS_PRECISE_SMC
@@ -1037,6 +1034,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
* using this information. Condition codes are not generated if they
* are only needed for conditional branches.
*/
+
+#define CC_DST (env->cc_dst)
+#define CC_SRC (env->cc_src)
+#define CC_SRC2 (env->cc_src2)
+#define CC_OP (env->cc_op)
+
typedef enum {
CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
@@ -1765,12 +1768,6 @@ struct X86CPU {
extern VMStateDescription vmstate_x86_cpu;
#endif
-/**
- * x86_cpu_do_interrupt:
- * @cpu: vCPU the interrupt is to be handled by.
- */
-void x86_cpu_do_interrupt(CPUState *cpu);
-bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -1793,9 +1790,6 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void x86_cpu_exec_enter(CPUState *cpu);
-void x86_cpu_exec_exit(CPUState *cpu);
-
void x86_cpu_list(void);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
@@ -1920,9 +1914,6 @@ void host_cpuid(uint32_t function, uint32_t count,
void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
/* helper.c */
-bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
#ifndef CONFIG_USER_ONLY
@@ -1947,8 +1938,6 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
#endif
-void breakpoint_handler(CPUState *cs);
-
/* will be suppressed */
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
@@ -1958,16 +1947,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
/* hw/pc.c */
uint64_t cpu_get_tsc(CPUX86State *env);
-/* XXX: This value should match the one returned by CPUID
- * and in exec.c */
-# if defined(TARGET_X86_64)
-# define TCG_PHYS_ADDR_BITS 40
-# else
-# define TCG_PHYS_ADDR_BITS 36
-# endif
-
-#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
-
#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_X86_CPU
@@ -1999,30 +1978,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
}
-#define CC_DST (env->cc_dst)
-#define CC_SRC (env->cc_src)
-#define CC_SRC2 (env->cc_src2)
-#define CC_OP (env->cc_op)
-
-/* n must be a constant to be efficient */
-static inline target_long lshift(target_long x, int n)
-{
- if (n >= 0) {
- return x << n;
- } else {
- return x >> (-n);
- }
-}
-
-/* float macros */
-#define FT0 (env->ft0)
-#define ST0 (env->fpregs[env->fpstt].d)
-#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
-#define ST1 ST(1)
-
-/* translate.c */
-void tcg_x86_init(void);
-
typedef CPUX86State CPUArchState;
typedef X86CPU ArchCPU;
@@ -2052,19 +2007,6 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
uint64_t status, uint64_t mcg_status, uint64_t addr,
uint64_t misc, int flags);
-/* excp_helper.c */
-void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
-void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
- uintptr_t retaddr);
-void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
- int error_code);
-void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
- int error_code, uintptr_t retaddr);
-void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
- int error_code, int next_eip_addend);
-
-/* cc_helper.c */
-extern const uint8_t parity_table[256];
uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
static inline uint32_t cpu_compute_eflags(CPUX86State *env)
@@ -2076,18 +2018,6 @@ static inline uint32_t cpu_compute_eflags(CPUX86State *env)
return eflags;
}
-/* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
- * after generating a call to a helper that uses this.
- */
-static inline void cpu_load_eflags(CPUX86State *env, int eflags,
- int update_mask)
-{
- CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
- CC_OP = CC_OP_EFLAGS;
- env->df = 1 - (2 * ((eflags >> 10) & 1));
- env->eflags = (env->eflags & ~update_mask) |
- (eflags & update_mask) | 0x2;
-}
/* load efer and update the corresponding hflags. XXX: do consistency
checks with cpuid bits? */
@@ -2176,16 +2106,6 @@ void helper_lock_init(void);
/* svm_helper.c */
void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
uint64_t param, uintptr_t retaddr);
-void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
- uint64_t exit_info_1, uintptr_t retaddr);
-void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
-
-/* seg_helper.c */
-void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
-
-/* smm_helper.c */
-void do_smm_enter(X86CPU *cpu);
-
/* apic.c */
void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
@@ -2224,11 +2144,6 @@ typedef int X86CPUVersion;
*/
void x86_cpu_set_default_version(X86CPUVersion version);
-/* Return name of 32-bit register, from a R_* constant */
-const char *get_register_name_32(unsigned int reg);
-
-void enable_compat_apic_id_mode(void);
-
#define APIC_DEFAULT_ADDRESS 0xfee00000
#define APIC_SPACE_SIZE 0x100000
diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h
new file mode 100644
index 0000000000..57b4391a7d
--- /dev/null
+++ b/target/i386/tcg/helper-tcg.h
@@ -0,0 +1,112 @@
+/*
+ * TCG specific prototypes for helpers
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef I386_HELPER_TCG_H
+#define I386_HELPER_TCG_H
+
+#include "exec/exec-all.h"
+
+/* Maximum instruction code size */
+#define TARGET_MAX_INSN_SIZE 16
+
+/*
+ * XXX: This value should match the one returned by CPUID
+ * and in exec.c
+ */
+# if defined(TARGET_X86_64)
+# define TCG_PHYS_ADDR_BITS 40
+# else
+# define TCG_PHYS_ADDR_BITS 36
+# endif
+
+#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
+
+/**
+ * x86_cpu_do_interrupt:
+ * @cpu: vCPU the interrupt is to be handled by.
+ */
+void x86_cpu_do_interrupt(CPUState *cpu);
+bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
+
+/* helper.c */
+bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
+
+void breakpoint_handler(CPUState *cs);
+
+/* n must be a constant to be efficient */
+static inline target_long lshift(target_long x, int n)
+{
+ if (n >= 0) {
+ return x << n;
+ } else {
+ return x >> (-n);
+ }
+}
+
+/* float macros */
+#define FT0 (env->ft0)
+#define ST0 (env->fpregs[env->fpstt].d)
+#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
+#define ST1 ST(1)
+
+/* translate.c */
+void tcg_x86_init(void);
+
+/* excp_helper.c */
+void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
+void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
+ uintptr_t retaddr);
+void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
+ int error_code);
+void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
+ int error_code, uintptr_t retaddr);
+void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
+ int error_code, int next_eip_addend);
+
+/* cc_helper.c */
+extern const uint8_t parity_table[256];
+
+/*
+ * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
+ * after generating a call to a helper that uses this.
+ */
+static inline void cpu_load_eflags(CPUX86State *env, int eflags,
+ int update_mask)
+{
+ CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
+ CC_OP = CC_OP_EFLAGS;
+ env->df = 1 - (2 * ((eflags >> 10) & 1));
+ env->eflags = (env->eflags & ~update_mask) |
+ (eflags & update_mask) | 0x2;
+}
+
+/* svm_helper.c */
+void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
+ uint64_t exit_info_1, uintptr_t retaddr);
+void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
+
+/* seg_helper.c */
+void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
+
+/* smm_helper.c */
+void do_smm_enter(X86CPU *cpu);
+
+#endif /* I386_HELPER_TCG_H */
diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h
new file mode 100644
index 0000000000..81f02e562e
--- /dev/null
+++ b/target/i386/tcg/tcg-cpu.h
@@ -0,0 +1,15 @@
+/*
+ * i386 TCG CPU class initialization
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TCG_CPU_H
+#define TCG_CPU_H
+
+void tcg_cpu_common_class_init(CPUClass *cc);
+
+#endif /* TCG_CPU_H */
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b9bd249c8f..f0aa6d1841 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -24,6 +24,8 @@
#include "qemu/qemu-print.h"
#include "cpu.h"
+#include "tcg/tcg-cpu.h"
+#include "tcg/helper-tcg.h"
#include "exec/exec-all.h"
#include "sysemu/kvm.h"
#include "sysemu/reset.h"
@@ -1495,7 +1497,8 @@ static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
cpu->env.features[FEAT_XSAVE_COMP_LO];
}
-const char *get_register_name_32(unsigned int reg)
+/* Return name of 32-bit register, from a R_* constant */
+static const char *get_register_name_32(unsigned int reg)
{
if (reg >= CPU_NB_REGS32) {
return NULL;
@@ -7012,13 +7015,6 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.eip = value;
}
-static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
-{
- X86CPU *cpu = X86_CPU(cs);
-
- cpu->env.eip = tb->pc - tb->cs_base;
-}
-
int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
{
X86CPU *cpu = X86_CPU(cs);
@@ -7252,17 +7248,18 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->class_by_name = x86_cpu_class_by_name;
cc->parse_features = x86_cpu_parse_featurestr;
cc->has_work = x86_cpu_has_work;
+
#ifdef CONFIG_TCG
- cc->do_interrupt = x86_cpu_do_interrupt;
- cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
-#endif
+ tcg_cpu_common_class_init(cc);
+#endif /* CONFIG_TCG */
+
cc->dump_state = x86_cpu_dump_state;
cc->set_pc = x86_cpu_set_pc;
- cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
+
#ifndef CONFIG_USER_ONLY
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
@@ -7273,7 +7270,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->vmsd = &vmstate_x86_cpu;
-#endif
+#endif /* !CONFIG_USER_ONLY */
+
cc->gdb_arch_name = x86_gdb_arch_name;
#ifdef TARGET_X86_64
cc->gdb_core_xml_file = "i386-64bit.xml";
@@ -7281,15 +7279,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#else
cc->gdb_core_xml_file = "i386-32bit.xml";
cc->gdb_num_core_regs = 50;
-#endif
-#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
- cc->debug_excp_handler = breakpoint_handler;
-#endif
- cc->cpu_exec_enter = x86_cpu_exec_enter;
- cc->cpu_exec_exit = x86_cpu_exec_exit;
-#ifdef CONFIG_TCG
- cc->tcg_initialize = tcg_x86_init;
- cc->tlb_fill = x86_cpu_tlb_fill;
#endif
cc->disas_set_info = x86_disas_set_info;
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 6e7e0f507c..6bb0c53182 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -24,10 +24,8 @@
#include "sysemu/runstate.h"
#include "kvm/kvm_i386.h"
#ifndef CONFIG_USER_ONLY
-#include "sysemu/tcg.h"
#include "sysemu/hw_accel.h"
#include "monitor/monitor.h"
-#include "hw/i386/apic_internal.h"
#endif
void cpu_sync_bndcs_hflags(CPUX86State *env)
@@ -572,27 +570,6 @@ void do_cpu_sipi(X86CPU *cpu)
}
#endif
-/* Frob eflags into and out of the CPU temporary format. */
-
-void x86_cpu_exec_enter(CPUState *cs)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
-
- CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
- env->df = 1 - (2 * ((env->eflags >> 10) & 1));
- CC_OP = CC_OP_EFLAGS;
- env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
-}
-
-void x86_cpu_exec_exit(CPUState *cs)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
-
- env->eflags = cpu_compute_eflags(env);
-}
-
#ifndef CONFIG_USER_ONLY
uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
{
diff --git a/target/i386/tcg/bpt_helper.c b/target/i386/tcg/bpt_helper.c
index e6cc2921e2..979230ac12 100644
--- a/target/i386/tcg/bpt_helper.c
+++ b/target/i386/tcg/bpt_helper.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
+#include "helper-tcg.h"
#ifndef CONFIG_USER_ONLY
diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c
index 924dd3cd57..cc7ea9e8b9 100644
--- a/target/i386/tcg/cc_helper.c
+++ b/target/i386/tcg/cc_helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
+#include "helper-tcg.h"
const uint8_t parity_table[256] = {
CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c
index 191471749f..a0f44431fe 100644
--- a/target/i386/tcg/excp_helper.c
+++ b/target/i386/tcg/excp_helper.c
@@ -23,6 +23,7 @@
#include "qemu/log.h"
#include "sysemu/runstate.h"
#include "exec/helper-proto.h"
+#include "helper-tcg.h"
void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_addend)
{
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 03b35443a6..13f31b6ac7 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -26,6 +26,7 @@
#include "exec/cpu_ldst.h"
#include "fpu/softfloat.h"
#include "fpu/softfloat-macros.h"
+#include "helper-tcg.h"
#ifdef CONFIG_SOFTMMU
#include "hw/irq.h"
@@ -2986,23 +2987,21 @@ void update_mxcsr_status(CPUX86State *env)
void update_mxcsr_from_sse_status(CPUX86State *env)
{
- if (tcg_enabled()) {
- uint8_t flags = get_float_exception_flags(&env->sse_status);
- /*
- * The MXCSR denormal flag has opposite semantics to
- * float_flag_input_denormal (the softfloat code sets that flag
- * only when flushing input denormals to zero, but SSE sets it
- * only when not flushing them to zero), so is not converted
- * here.
- */
- env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) |
- (flags & float_flag_divbyzero ? FPUS_ZE : 0) |
- (flags & float_flag_overflow ? FPUS_OE : 0) |
- (flags & float_flag_underflow ? FPUS_UE : 0) |
- (flags & float_flag_inexact ? FPUS_PE : 0) |
- (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE :
- 0));
- }
+ uint8_t flags = get_float_exception_flags(&env->sse_status);
+ /*
+ * The MXCSR denormal flag has opposite semantics to
+ * float_flag_input_denormal (the softfloat code sets that flag
+ * only when flushing input denormals to zero, but SSE sets it
+ * only when not flushing them to zero), so is not converted
+ * here.
+ */
+ env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) |
+ (flags & float_flag_divbyzero ? FPUS_ZE : 0) |
+ (flags & float_flag_overflow ? FPUS_OE : 0) |
+ (flags & float_flag_underflow ? FPUS_UE : 0) |
+ (flags & float_flag_inexact ? FPUS_PE : 0) |
+ (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE :
+ 0));
}
void helper_update_mxcsr(CPUX86State *env)
diff --git a/target/i386/tcg/int_helper.c b/target/i386/tcg/int_helper.c
index 4f89436b53..87fa7280ee 100644
--- a/target/i386/tcg/int_helper.c
+++ b/target/i386/tcg/int_helper.c
@@ -24,6 +24,7 @@
#include "exec/helper-proto.h"
#include "qapi/error.h"
#include "qemu/guest-random.h"
+#include "helper-tcg.h"
//#define DEBUG_MULDIV
diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c
index 21ca3e3e88..e5cd2de1bf 100644
--- a/target/i386/tcg/mem_helper.c
+++ b/target/i386/tcg/mem_helper.c
@@ -25,6 +25,7 @@
#include "qemu/int128.h"
#include "qemu/atomic128.h"
#include "tcg/tcg.h"
+#include "helper-tcg.h"
void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0)
{
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
index ae259d9145..c99370e5e3 100644
--- a/target/i386/tcg/misc_helper.c
+++ b/target/i386/tcg/misc_helper.c
@@ -24,6 +24,7 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/address-spaces.h"
+#include "helper-tcg.h"
void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
{
diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c
index fd966174b4..22423eedcd 100644
--- a/target/i386/tcg/mpx_helper.c
+++ b/target/i386/tcg/mpx_helper.c
@@ -22,6 +22,7 @@
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
+#include "helper-tcg.h"
void helper_bndck(CPUX86State *env, uint32_t fail)
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index 09b6554660..ed3e04a187 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -25,6 +25,7 @@
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/log.h"
+#include "helper-tcg.h"
//#define DEBUG_PCALL
diff --git a/target/i386/tcg/smm_helper.c b/target/i386/tcg/smm_helper.c
index d20e8edfdf..62d027abd3 100644
--- a/target/i386/tcg/smm_helper.c
+++ b/target/i386/tcg/smm_helper.c
@@ -22,6 +22,8 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/log.h"
+#include "helper-tcg.h"
+
/* SMM support */
diff --git a/target/i386/tcg/svm_helper.c b/target/i386/tcg/svm_helper.c
index 38931586e5..097bb9b83d 100644
--- a/target/i386/tcg/svm_helper.c
+++ b/target/i386/tcg/svm_helper.c
@@ -22,6 +22,7 @@
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
+#include "helper-tcg.h"
/* Secure Virtual Machine helpers */
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
new file mode 100644
index 0000000000..628dd29fe7
--- /dev/null
+++ b/target/i386/tcg/tcg-cpu.c
@@ -0,0 +1,71 @@
+/*
+ * i386 TCG cpu class initialization
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "tcg-cpu.h"
+#include "exec/exec-all.h"
+#include "sysemu/runstate.h"
+#include "helper-tcg.h"
+
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/i386/apic.h"
+#endif
+
+/* Frob eflags into and out of the CPU temporary format. */
+
+static void x86_cpu_exec_enter(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
+ env->df = 1 - (2 * ((env->eflags >> 10) & 1));
+ CC_OP = CC_OP_EFLAGS;
+ env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
+}
+
+static void x86_cpu_exec_exit(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ env->eflags = cpu_compute_eflags(env);
+}
+
+static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+{
+ X86CPU *cpu = X86_CPU(cs);
+
+ cpu->env.eip = tb->pc - tb->cs_base;
+}
+
+void tcg_cpu_common_class_init(CPUClass *cc)
+{
+ cc->do_interrupt = x86_cpu_do_interrupt;
+ cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
+ cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
+ cc->cpu_exec_enter = x86_cpu_exec_enter;
+ cc->cpu_exec_exit = x86_cpu_exec_exit;
+ cc->tcg_initialize = tcg_x86_init;
+ cc->tlb_fill = x86_cpu_tlb_fill;
+#ifndef CONFIG_USER_ONLY
+ cc->debug_excp_handler = breakpoint_handler;
+#endif
+}
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 4c57307e42..5988ea0289 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -28,6 +28,7 @@
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
+#include "helper-tcg.h"
#include "trace-tcg.h"
#include "exec/log.h"
diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build
index 02794226c2..6a1a73cdbf 100644
--- a/target/i386/tcg/meson.build
+++ b/target/i386/tcg/meson.build
@@ -10,4 +10,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files(
'seg_helper.c',
'smm_helper.c',
'svm_helper.c',
+ 'tcg-cpu.c',
'translate.c'), if_false: files('tcg-stub.c'))
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 11/25] tcg: cpu_exec_{enter,exit} helpers
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (9 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 10/25] i386: move TCG cpu class initialization out of helper.c Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 16:45 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 12/25] tcg: make CPUClass.cpu_exec_* optional Claudio Fontana
` (15 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Move invocation of CPUClass.cpu_exec_*() to separate helpers,
to make it easier to refactor that code later.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
accel/tcg/cpu-exec.c | 23 ++++++++++++++++++-----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 58aea605d8..8d31145ad2 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -236,9 +236,22 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
}
#endif
+static void cpu_exec_enter(CPUState *cpu)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ cc->cpu_exec_enter(cpu);
+}
+
+static void cpu_exec_exit(CPUState *cpu)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ cc->cpu_exec_exit(cpu);
+}
+
void cpu_exec_step_atomic(CPUState *cpu)
{
- CPUClass *cc = CPU_GET_CLASS(cpu);
TranslationBlock *tb;
target_ulong cs_base, pc;
uint32_t flags;
@@ -257,11 +270,11 @@ void cpu_exec_step_atomic(CPUState *cpu)
/* Since we got here, we know that parallel_cpus must be true. */
parallel_cpus = false;
- cc->cpu_exec_enter(cpu);
+ cpu_exec_enter(cpu);
/* execute the generated code */
trace_exec_tb(tb, pc);
cpu_tb_exec(cpu, tb);
- cc->cpu_exec_exit(cpu);
+ cpu_exec_exit(cpu);
} else {
/*
* The mmap_lock is dropped by tb_gen_code if it runs out of
@@ -713,7 +726,7 @@ int cpu_exec(CPUState *cpu)
rcu_read_lock();
- cc->cpu_exec_enter(cpu);
+ cpu_exec_enter(cpu);
/* Calculate difference between guest clock and host clock.
* This delay includes the delay of the last cycle, so
@@ -775,7 +788,7 @@ int cpu_exec(CPUState *cpu)
}
}
- cc->cpu_exec_exit(cpu);
+ cpu_exec_exit(cpu);
rcu_read_unlock();
return ret;
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 12/25] tcg: make CPUClass.cpu_exec_* optional
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (10 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 11/25] tcg: cpu_exec_{enter,exit} helpers Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 13/25] tcg: Make CPUClass.debug_excp_handler optional Claudio Fontana
` (14 subsequent siblings)
26 siblings, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
This will let us simplify the code that initializes CPU class
methods, when we move cpu_exec_*() to a separate struct.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
accel/tcg/cpu-exec.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 8d31145ad2..890b88861a 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -240,14 +240,18 @@ static void cpu_exec_enter(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->cpu_exec_enter(cpu);
+ if (cc->cpu_exec_enter) {
+ cc->cpu_exec_enter(cpu);
+ }
}
static void cpu_exec_exit(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->cpu_exec_exit(cpu);
+ if (cc->cpu_exec_exit) {
+ cc->cpu_exec_exit(cpu);
+ }
}
void cpu_exec_step_atomic(CPUState *cpu)
@@ -619,7 +623,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
True when it is, and we should restart on a new TB,
and via longjmp via cpu_loop_exit. */
else {
- if (cc->cpu_exec_interrupt(cpu, interrupt_request)) {
+ if (cc->cpu_exec_interrupt &&
+ cc->cpu_exec_interrupt(cpu, interrupt_request)) {
if (need_replay_interrupt(interrupt_request)) {
replay_interrupt();
}
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 13/25] tcg: Make CPUClass.debug_excp_handler optional
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (11 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 12/25] tcg: make CPUClass.cpu_exec_* optional Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 14/25] cpu: Remove unnecessary noop methods Claudio Fontana
` (13 subsequent siblings)
26 siblings, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
accel/tcg/cpu-exec.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 890b88861a..64cba89356 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -482,7 +482,9 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
}
}
- cc->debug_excp_handler(cpu);
+ if (cc->debug_excp_handler) {
+ cc->debug_excp_handler(cpu);
+ }
}
static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 14/25] cpu: Remove unnecessary noop methods
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (12 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 13/25] tcg: Make CPUClass.debug_excp_handler optional Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 11:05 ` Philippe Mathieu-Daudé
2020-12-11 8:31 ` [PATCH v11 15/25] cpu: Introduce TCGCpuOperations struct Claudio Fontana
` (12 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/core/cpu.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 576fa1d7ba..994a12cb35 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -199,15 +199,6 @@ static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
return target_words_bigendian();
}
-static void cpu_common_noop(CPUState *cpu)
-{
-}
-
-static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req)
-{
- return false;
-}
-
#if !defined(CONFIG_USER_ONLY)
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
{
@@ -410,11 +401,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
- k->debug_excp_handler = cpu_common_noop;
k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
- k->cpu_exec_enter = cpu_common_noop;
- k->cpu_exec_exit = cpu_common_noop;
- k->cpu_exec_interrupt = cpu_common_exec_interrupt;
k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 15/25] cpu: Introduce TCGCpuOperations struct
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (13 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 14/25] cpu: Remove unnecessary noop methods Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 16:55 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 16/25] target/riscv: remove CONFIG_TCG, as it is always TCG Claudio Fontana
` (11 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded struct for now, to make code conversion
easier.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: make the tcg code build for CONFIG_TCG only]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
include/hw/core/cpu.h | 9 ++++++++-
include/hw/core/tcg-cpu-ops.h | 25 +++++++++++++++++++++++++
cpu.c | 6 +++++-
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 12 ++++++------
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
MAINTAINERS | 1 +
target/ppc/translate_init.c.inc | 2 +-
27 files changed, 67 insertions(+), 30 deletions(-)
create mode 100644 include/hw/core/tcg-cpu-ops.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 3d92c967ff..c93b08a0fb 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -76,6 +76,10 @@ typedef struct CPUWatchpoint CPUWatchpoint;
struct TranslationBlock;
+#ifdef CONFIG_TCG
+#include "tcg-cpu-ops.h"
+#endif /* CONFIG_TCG */
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -221,12 +225,15 @@ struct CPUClass {
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
- void (*tcg_initialize)(void);
const char *deprecation_note;
/* Keep non-pointer data at the end to minimize holes. */
int gdb_num_core_regs;
bool gdb_stop_before_watchpoint;
+
+#ifdef CONFIG_TCG
+ TcgCpuOperations tcg_ops;
+#endif /* CONFIG_TCG */
};
/*
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
new file mode 100644
index 0000000000..4475ef0996
--- /dev/null
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -0,0 +1,25 @@
+/*
+ * TCG-Specific operations that are not meaningful for hardware accelerators
+ *
+ * Copyright 2020 SUSE LLC
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TCG_CPU_OPS_H
+#define TCG_CPU_OPS_H
+
+/**
+ * struct TcgCpuOperations: TCG operations specific to a CPU class
+ */
+typedef struct TcgCpuOperations {
+ /**
+ * @initialize: Initalize TCG state
+ *
+ * Called when the first CPU is realized.
+ */
+ void (*initialize)(void);
+} TcgCpuOperations;
+
+#endif /* TCG_CPU_OPS_H */
diff --git a/cpu.c b/cpu.c
index 0be5dcb6f3..27ad096cc4 100644
--- a/cpu.c
+++ b/cpu.c
@@ -174,14 +174,18 @@ void cpu_exec_initfn(CPUState *cpu)
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+#ifdef CONFIG_TCG
static bool tcg_target_initialized;
+#endif /* CONFIG_TCG */
cpu_list_add(cpu);
+#ifdef CONFIG_TCG
if (tcg_enabled() && !tcg_target_initialized) {
tcg_target_initialized = true;
- cc->tcg_initialize();
+ cc->tcg_ops.initialize();
}
+#endif /* CONFIG_TCG */
tlb_init(cpu);
qemu_plugin_vcpu_init_hook(cpu);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index b3fd6643e8..d66f0351a9 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -231,7 +231,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
dc->vmsd = &vmstate_alpha_cpu;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
- cc->tcg_initialize = alpha_translate_init;
+ cc->tcg_ops.initialize = alpha_translate_init;
cc->gdb_num_core_regs = 67;
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 07492e9f9a..1fa9382a7c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2261,7 +2261,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = arm_disas_set_info;
#ifdef CONFIG_TCG
- cc->tcg_initialize = arm_translate_init;
+ cc->tcg_ops.initialize = arm_translate_init;
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 5d9c4ad5bf..94306a2aa0 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -206,7 +206,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->tlb_fill = avr_cpu_tlb_fill;
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
- cc->tcg_initialize = avr_cpu_tcg_init;
+ cc->tcg_ops.initialize = avr_cpu_tcg_init;
cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index cff6b9eabf..4328f8e6c9 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -201,7 +201,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 8;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
@@ -212,7 +212,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 9;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
@@ -223,7 +223,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 10;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
@@ -234,7 +234,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 11;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
@@ -245,7 +245,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
ccc->vr = 17;
cc->do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
- cc->tcg_initialize = cris_initialize_crisv10_tcg;
+ cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
@@ -284,7 +284,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = cris_disas_set_info;
- cc->tcg_initialize = cris_initialize_tcg;
+ cc->tcg_ops.initialize = cris_initialize_tcg;
}
#define DEFINE_CRIS_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 71b6aca45d..4c778966c2 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -153,7 +153,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->do_unaligned_access = hppa_cpu_do_unaligned_access;
cc->disas_set_info = hppa_cpu_disas_set_info;
- cc->tcg_initialize = hppa_translate_init;
+ cc->tcg_ops.initialize = hppa_translate_init;
cc->gdb_num_core_regs = 128;
}
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 628dd29fe7..1f2a3e881a 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -63,7 +63,7 @@ void tcg_cpu_common_class_init(CPUClass *cc)
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
- cc->tcg_initialize = tcg_x86_init;
+ cc->tcg_ops.initialize = tcg_x86_init;
cc->tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->debug_excp_handler = breakpoint_handler;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c50ad5fa15..ef795b81a4 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -237,7 +237,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->debug_excp_handler = lm32_debug_excp_handler;
cc->disas_set_info = lm32_cpu_disas_set_info;
- cc->tcg_initialize = lm32_translate_init;
+ cc->tcg_ops.initialize = lm32_translate_init;
}
#define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 72c545149e..b66d86c353 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -289,7 +289,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
- cc->tcg_initialize = m68k_tcg_init;
+ cc->tcg_ops.initialize = m68k_tcg_init;
cc->gdb_num_core_regs = 18;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 9b2482159d..bc10518fa3 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -335,7 +335,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 32 + 27;
cc->disas_set_info = mb_disas_set_info;
- cc->tcg_initialize = mb_tcg_init;
+ cc->tcg_ops.initialize = mb_tcg_init;
}
static const TypeInfo mb_cpu_type_info = {
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 76d50b00b4..bc48573763 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -249,7 +249,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
- cc->tcg_initialize = mips_tcg_init;
+ cc->tcg_ops.initialize = mips_tcg_init;
cc->tlb_fill = mips_cpu_tlb_fill;
#endif
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 6e0443ccb7..224cfc8361 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -116,7 +116,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
- cc->tcg_initialize = moxie_translate_init;
+ cc->tcg_ops.initialize = moxie_translate_init;
}
static void moxielite_initfn(Object *obj)
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 8f7011fcb9..29c9c6f634 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -205,7 +205,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
cc->gdb_num_core_regs = 49;
- cc->tcg_initialize = nios2_tcg_init;
+ cc->tcg_ops.initialize = nios2_tcg_init;
}
static const TypeInfo nios2_cpu_type_info = {
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 5528c0918f..e442f4f97c 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -166,7 +166,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
dc->vmsd = &vmstate_openrisc_cpu;
#endif
cc->gdb_num_core_regs = 32 + 3;
- cc->tcg_initialize = openrisc_translate_init;
+ cc->tcg_ops.initialize = openrisc_translate_init;
cc->disas_set_info = openrisc_disas_set_info;
}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6a0264fc6b..a52e0ce466 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -562,7 +562,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->vmsd = &vmstate_riscv_cpu;
#endif
#ifdef CONFIG_TCG
- cc->tcg_initialize = riscv_translate_init;
+ cc->tcg_ops.initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
#endif
device_class_set_props(dc, riscv_cpu_properties);
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 23ee17a701..a701a09b11 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -194,7 +194,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
- cc->tcg_initialize = rx_translate_init;
+ cc->tcg_ops.initialize = rx_translate_init;
cc->tlb_fill = rx_cpu_tlb_fill;
cc->gdb_num_core_regs = 26;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 7b66718c44..697b94ff7b 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -512,7 +512,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
#ifdef CONFIG_TCG
- cc->tcg_initialize = s390x_translate_init;
+ cc->tcg_ops.initialize = s390x_translate_init;
cc->tlb_fill = s390_cpu_tlb_fill;
#endif
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 3c68021c56..bdc5c9d90b 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -231,7 +231,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
- cc->tcg_initialize = sh4_translate_init;
+ cc->tcg_ops.initialize = sh4_translate_init;
cc->gdb_num_core_regs = 59;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 701e794eac..07e48b86d1 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -879,7 +879,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_sparc_cpu;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
- cc->tcg_initialize = sparc_tcg_init;
+ cc->tcg_ops.initialize = sparc_tcg_init;
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
cc->gdb_num_core_regs = 86;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 1fee87c094..cd24d0eb9d 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -153,7 +153,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = tilegx_cpu_set_pc;
cc->tlb_fill = tilegx_cpu_tlb_fill;
cc->gdb_num_core_regs = 0;
- cc->tcg_initialize = tilegx_tcg_init;
+ cc->tcg_ops.initialize = tilegx_tcg_init;
}
static const TypeInfo tilegx_cpu_type_info = {
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 2f2e5b029f..78b2925955 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -164,7 +164,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->set_pc = tricore_cpu_set_pc;
cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
- cc->tcg_initialize = tricore_tcg_init;
+ cc->tcg_ops.initialize = tricore_tcg_init;
cc->tlb_fill = tricore_cpu_tlb_fill;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index b27fb9689f..226bf4226e 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -137,7 +137,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = uc32_cpu_set_pc;
cc->tlb_fill = uc32_cpu_tlb_fill;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- cc->tcg_initialize = uc32_translate_init;
+ cc->tcg_ops.initialize = uc32_translate_init;
dc->vmsd = &vmstate_uc32_cpu;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 88a32268a1..5a6f5bf88b 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -209,7 +209,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
- cc->tcg_initialize = xtensa_translate_init;
+ cc->tcg_ops.initialize = xtensa_translate_init;
dc->vmsd = &vmstate_xtensa_cpu;
}
diff --git a/MAINTAINERS b/MAINTAINERS
index f53f2678d8..d876f504a6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1535,6 +1535,7 @@ F: qapi/machine.json
F: qapi/machine-target.json
F: include/hw/boards.h
F: include/hw/core/cpu.h
+F: include/hw/core/tcg-cpu-ops.h
F: include/hw/cpu/cluster.h
F: include/sysemu/numa.h
T: git https://github.com/ehabkost/qemu.git machine-next
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 78cc8f043b..9a6932b774 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10945,7 +10945,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
#ifdef CONFIG_TCG
- cc->tcg_initialize = ppc_translate_init;
+ cc->tcg_ops.initialize = ppc_translate_init;
cc->tlb_fill = ppc_cpu_tlb_fill;
#endif
#ifndef CONFIG_USER_ONLY
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 16/25] target/riscv: remove CONFIG_TCG, as it is always TCG
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (14 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 15/25] cpu: Introduce TCGCpuOperations struct Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 16:56 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 17/25] accel/tcg: split TCG-only code from cpu_exec_realizefn Claudio Fontana
` (10 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Jason Wang, Marcelo Tosatti, qemu-devel, Peter Xu,
Dario Faggioli, Cameron Esfahani, haxm-team, Claudio Fontana,
Anthony Perard, Alistair Francis, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a52e0ce466..27dd1645c9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -561,10 +561,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
#endif
-#ifdef CONFIG_TCG
cc->tcg_ops.initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
-#endif
+
device_class_set_props(dc, riscv_cpu_properties);
}
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 17/25] accel/tcg: split TCG-only code from cpu_exec_realizefn
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (15 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 16/25] target/riscv: remove CONFIG_TCG, as it is always TCG Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 16:58 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops Claudio Fontana
` (9 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team,
Claudio Fontana, Anthony Perard, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
move away TCG-only code, make it compile only on TCG.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
include/hw/core/cpu.h | 8 +++++
accel/tcg/cpu-exec.c | 28 +++++++++++++++++
cpu.c | 70 ++++++++++++++++++++-----------------------
hw/core/cpu.c | 6 +++-
4 files changed, 74 insertions(+), 38 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c93b08a0fb..ea648d52ad 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -1119,10 +1119,18 @@ AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
extern Property cpu_common_props[];
+
+/* $(top_srcdir)/cpu.c */
void cpu_exec_initfn(CPUState *cpu);
void cpu_exec_realizefn(CPUState *cpu, Error **errp);
void cpu_exec_unrealizefn(CPUState *cpu);
+#ifdef CONFIG_TCG
+/* accel/tcg/cpu-exec.c */
+void tcg_exec_realizefn(CPUState *cpu, Error **errp);
+void tcg_exec_unrealizefn(CPUState *cpu);
+#endif /* CONFIG_TCG */
+
/**
* target_words_bigendian:
* Returns true if the (default) endianness of the target is big endian,
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 64cba89356..50eb92d217 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -801,6 +801,34 @@ int cpu_exec(CPUState *cpu)
return ret;
}
+void tcg_exec_realizefn(CPUState *cpu, Error **errp)
+{
+ static bool tcg_target_initialized;
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (!tcg_target_initialized) {
+ cc->tcg_ops.initialize();
+ tcg_target_initialized = true;
+ }
+ tlb_init(cpu);
+ qemu_plugin_vcpu_init_hook(cpu);
+
+#ifndef CONFIG_USER_ONLY
+ tcg_iommu_init_notifier_list(cpu);
+#endif /* !CONFIG_USER_ONLY */
+}
+
+/* undo the initializations in reverse order */
+void tcg_exec_unrealizefn(CPUState *cpu)
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_iommu_free_notifier_list(cpu);
+#endif /* !CONFIG_USER_ONLY */
+
+ qemu_plugin_vcpu_exit_hook(cpu);
+ tlb_destroy(cpu);
+}
+
#ifndef CONFIG_USER_ONLY
void dump_drift_info(void)
diff --git a/cpu.c b/cpu.c
index 27ad096cc4..5cc8f181be 100644
--- a/cpu.c
+++ b/cpu.c
@@ -124,13 +124,35 @@ const VMStateDescription vmstate_cpu_common = {
};
#endif
+void cpu_exec_realizefn(CPUState *cpu, Error **errp)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ cpu_list_add(cpu);
+
+#ifdef CONFIG_TCG
+ /* NB: errp parameter is unused currently */
+ if (tcg_enabled()) {
+ tcg_exec_realizefn(cpu, errp);
+ }
+#endif /* CONFIG_TCG */
+
+#ifdef CONFIG_USER_ONLY
+ assert(cc->vmsd == NULL);
+#else
+ if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
+ vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
+ }
+ if (cc->vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+ }
+#endif /* CONFIG_USER_ONLY */
+}
+
void cpu_exec_unrealizefn(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- tlb_destroy(cpu);
- cpu_list_remove(cpu);
-
#ifdef CONFIG_USER_ONLY
assert(cc->vmsd == NULL);
#else
@@ -140,8 +162,15 @@ void cpu_exec_unrealizefn(CPUState *cpu)
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
}
- tcg_iommu_free_notifier_list(cpu);
#endif
+#ifdef CONFIG_TCG
+ /* NB: errp parameter is unused currently */
+ if (tcg_enabled()) {
+ tcg_exec_unrealizefn(cpu);
+ }
+#endif /* CONFIG_TCG */
+
+ cpu_list_remove(cpu);
}
Property cpu_common_props[] = {
@@ -171,39 +200,6 @@ void cpu_exec_initfn(CPUState *cpu)
#endif
}
-void cpu_exec_realizefn(CPUState *cpu, Error **errp)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-#ifdef CONFIG_TCG
- static bool tcg_target_initialized;
-#endif /* CONFIG_TCG */
-
- cpu_list_add(cpu);
-
-#ifdef CONFIG_TCG
- if (tcg_enabled() && !tcg_target_initialized) {
- tcg_target_initialized = true;
- cc->tcg_ops.initialize();
- }
-#endif /* CONFIG_TCG */
- tlb_init(cpu);
-
- qemu_plugin_vcpu_init_hook(cpu);
-
-#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
-#else /* !CONFIG_USER_ONLY */
- if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
- vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
- }
- if (cc->vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
- }
-
- tcg_iommu_init_notifier_list(cpu);
-#endif
-}
-
const char *parse_cpu_option(const char *cpu_option)
{
ObjectClass *oc;
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 994a12cb35..1f04aab16b 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -199,6 +199,10 @@ static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
return target_words_bigendian();
}
+/*
+ * XXX the following #if is always true because this is a common_ss
+ * module, so target CONFIG_* is never defined.
+ */
#if !defined(CONFIG_USER_ONLY)
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
{
@@ -340,9 +344,9 @@ static void cpu_common_realizefn(DeviceState *dev, Error **errp)
static void cpu_common_unrealizefn(DeviceState *dev)
{
CPUState *cpu = CPU(dev);
+
/* NOTE: latest generic point before the cpu is fully unrealized */
trace_fini_vcpu(cpu);
- qemu_plugin_vcpu_exit_hook(cpu);
cpu_exec_unrealizefn(cpu);
}
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (16 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 17/25] accel/tcg: split TCG-only code from cpu_exec_realizefn Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 17:05 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 19/25] cpu: Move cpu_exec_* " Claudio Fontana
` (8 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
include/hw/core/cpu.h | 8 --------
include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 4 +++-
target/avr/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 +++-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
14 files changed, 29 insertions(+), 21 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index ea648d52ad..83007d262c 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -110,13 +110,6 @@ struct TranslationBlock;
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @synchronize_from_tb: Callback for synchronizing state from a TCG
- * #TranslationBlock. This is called when we abandon execution
- * of a TB before starting it, and must set all parts of the CPU
- * state which the previous TB in the chain may not have updated.
- * This always includes at least the program counter; some targets
- * will need to do more. If this hook is not implemented then the
- * default is to call @set_pc(tb->pc).
* @tlb_fill: Callback for handling a softmmu tlb miss or user-only
* address fault. For system mode, if the access is valid, call
* tlb_set_page and return true; if the access is invalid, and
@@ -193,7 +186,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 4475ef0996..e1d50b3c8b 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -10,6 +10,8 @@
#ifndef TCG_CPU_OPS_H
#define TCG_CPU_OPS_H
+#include "hw/core/cpu.h"
+
/**
* struct TcgCpuOperations: TCG operations specific to a CPU class
*/
@@ -20,6 +22,16 @@ typedef struct TcgCpuOperations {
* Called when the first CPU is realized.
*/
void (*initialize)(void);
+ /**
+ * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
+ *
+ * This is called when we abandon execution of a TB before
+ * starting it, and must set all parts of the CPU state which
+ * the previous TB in the chain may not have updated. This
+ * will need to do more. If this hook is not implemented then
+ * the default is to call @set_pc(tb->pc).
+ */
+ void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
} TcgCpuOperations;
#endif /* TCG_CPU_OPS_H */
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 50eb92d217..05dba7f2cc 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -192,8 +192,8 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
TARGET_FMT_lx "] %s\n",
last_tb->tc.ptr, last_tb->pc,
lookup_symbol(last_tb->pc));
- if (cc->synchronize_from_tb) {
- cc->synchronize_from_tb(cpu, last_tb);
+ if (cc->tcg_ops.synchronize_from_tb) {
+ cc->tcg_ops.synchronize_from_tb(cpu, last_tb);
} else {
assert(cc->set_pc);
cc->set_pc(cpu, last_tb->pc);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1fa9382a7c..ac1757d49f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -54,6 +54,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
}
}
+#ifdef CONFIG_TCG
static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -69,6 +70,7 @@ static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
env->regs[15] = tb->pc;
}
}
+#endif /* CONFIG_TCG */
static bool arm_cpu_has_work(CPUState *cs)
{
@@ -2242,7 +2244,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
- cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
@@ -2262,6 +2263,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = arm_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = arm_translate_init;
+ cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 94306a2aa0..f753c15768 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -207,7 +207,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->tcg_ops.initialize = avr_cpu_tcg_init;
- cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = avr_cpu_synchronize_from_tb;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
cc->gdb_num_core_regs = 35;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 4c778966c2..12a09e93ae 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -143,7 +143,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
- cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
cc->tlb_fill = hppa_cpu_tlb_fill;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 1f2a3e881a..d1414e2970 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -60,7 +60,7 @@ void tcg_cpu_common_class_init(CPUClass *cc)
{
cc->do_interrupt = x86_cpu_do_interrupt;
cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
- cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
cc->tcg_ops.initialize = tcg_x86_init;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index bc10518fa3..97d94d9c27 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -322,7 +322,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
- cc->synchronize_from_tb = mb_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
cc->gdb_read_register = mb_cpu_gdb_read_register;
cc->gdb_write_register = mb_cpu_gdb_write_register;
cc->tlb_fill = mb_cpu_tlb_fill;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index bc48573763..4a539349a9 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -44,6 +44,7 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value)
}
}
+#ifdef CONFIG_TCG
static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -53,6 +54,7 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
env->hflags &= ~MIPS_HFLAG_BMASK;
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
}
+#endif /* CONFIG_TCG */
static bool mips_cpu_has_work(CPUState *cs)
{
@@ -238,7 +240,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
- cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
@@ -250,6 +251,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = mips_tcg_init;
+ cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tlb_fill = mips_cpu_tlb_fill;
#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 27dd1645c9..a9c30879d3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -543,7 +543,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
- cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = riscv_cpu_synchronize_from_tb;
cc->gdb_read_register = riscv_cpu_gdb_read_register;
cc->gdb_write_register = riscv_cpu_gdb_write_register;
cc->gdb_num_core_regs = 33;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index a701a09b11..d03c4e0b05 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -189,7 +189,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
- cc->synchronize_from_tb = rx_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = rx_cpu_synchronize_from_tb;
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index bdc5c9d90b..a33025b5c8 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -222,7 +222,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
- cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
cc->tlb_fill = superh_cpu_tlb_fill;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 07e48b86d1..baf6c5b587 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -868,7 +868,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
#endif
cc->set_pc = sparc_cpu_set_pc;
- cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb;
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
cc->tlb_fill = sparc_cpu_tlb_fill;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 78b2925955..5edf96c600 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -162,7 +162,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb;
+ cc->tcg_ops.synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->tcg_ops.initialize = tricore_tcg_init;
cc->tlb_fill = tricore_cpu_tlb_fill;
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 19/25] cpu: Move cpu_exec_* to tcg_ops
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (17 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 17:30 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 20/25] cpu: Move tlb_fill " Claudio Fontana
` (7 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
include/hw/core/cpu.h | 6 ------
include/hw/core/tcg-cpu-ops.h | 6 ++++++
accel/tcg/cpu-exec.c | 12 ++++++------
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/arm/cpu64.c | 5 ++++-
target/arm/cpu_tcg.c | 7 ++++++-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 6 +++---
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 16 ++++++++++------
26 files changed, 54 insertions(+), 42 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 83007d262c..52142e9094 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -146,9 +146,6 @@ struct TranslationBlock;
* @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
* gdb stub. Returns a pointer to the XML contents for the specified XML file
* or NULL if the CPU doesn't have a dynamically generated content for it.
- * @cpu_exec_enter: Callback for cpu_exec preparation.
- * @cpu_exec_exit: Callback for cpu_exec cleanup.
- * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
* @disas_set_info: Setup architecture specific components of disassembly info
* @adjust_watchpoint_address: Perform a target-specific adjustment to an
* address before attempting to match it against watchpoints.
@@ -211,9 +208,6 @@ struct CPUClass {
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
- void (*cpu_exec_enter)(CPUState *cpu);
- void (*cpu_exec_exit)(CPUState *cpu);
- bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index e1d50b3c8b..fbd579c2a6 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -32,6 +32,12 @@ typedef struct TcgCpuOperations {
* the default is to call @set_pc(tb->pc).
*/
void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
+ /** @cpu_exec_enter: Callback for cpu_exec preparation */
+ void (*cpu_exec_enter)(CPUState *cpu);
+ /** @cpu_exec_exit: Callback for cpu_exec cleanup */
+ void (*cpu_exec_exit)(CPUState *cpu);
+ /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
+ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
} TcgCpuOperations;
#endif /* TCG_CPU_OPS_H */
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 05dba7f2cc..502f6a53ae 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -240,8 +240,8 @@ static void cpu_exec_enter(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->cpu_exec_enter) {
- cc->cpu_exec_enter(cpu);
+ if (cc->tcg_ops.cpu_exec_enter) {
+ cc->tcg_ops.cpu_exec_enter(cpu);
}
}
@@ -249,8 +249,8 @@ static void cpu_exec_exit(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->cpu_exec_exit) {
- cc->cpu_exec_exit(cpu);
+ if (cc->tcg_ops.cpu_exec_exit) {
+ cc->tcg_ops.cpu_exec_exit(cpu);
}
}
@@ -625,8 +625,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
True when it is, and we should restart on a new TB,
and via longjmp via cpu_loop_exit. */
else {
- if (cc->cpu_exec_interrupt &&
- cc->cpu_exec_interrupt(cpu, interrupt_request)) {
+ if (cc->tcg_ops.cpu_exec_interrupt &&
+ cc->tcg_ops.cpu_exec_interrupt(cpu, interrupt_request)) {
if (need_replay_interrupt(interrupt_request)) {
replay_interrupt();
}
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index d66f0351a9..d9ced1635a 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -218,7 +218,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;
cc->do_interrupt = alpha_cpu_do_interrupt;
- cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = alpha_cpu_exec_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ac1757d49f..897db4335a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2241,7 +2241,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = arm_cpu_class_by_name;
cc->has_work = arm_cpu_has_work;
- cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
cc->gdb_read_register = arm_cpu_gdb_read_register;
@@ -2263,6 +2262,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = arm_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = arm_translate_init;
+ cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 649213082f..ebc53c8bdc 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -784,7 +784,10 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
- cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
+#ifdef CONFIG_TCG
+ cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
+#endif /* CONFIG_TCG */
+
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
cc->gdb_num_core_regs = 34;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 0013e25412..e261839d08 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -15,6 +15,7 @@
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
+#ifdef CONFIG_TCG
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -38,6 +39,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return ret;
}
+#endif /* CONFIG_TCG */
static void arm926_initfn(Object *obj)
{
@@ -628,7 +630,10 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
#endif
- cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
+#ifdef CONFIG_TCG
+ cc->tcg_ops.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
+#endif /* CONFIG_TCG */
+
cc->gdb_core_xml_file = "arm-m-profile.xml";
}
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index f753c15768..277b00dbfc 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -198,7 +198,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = avr_cpu_has_work;
cc->do_interrupt = avr_cpu_do_interrupt;
- cc->cpu_exec_interrupt = avr_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = avr_cpu_exec_interrupt;
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 4328f8e6c9..7489fc20c8 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -269,7 +269,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work;
cc->do_interrupt = cris_cpu_do_interrupt;
- cc->cpu_exec_interrupt = cris_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = cris_cpu_exec_interrupt;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 12a09e93ae..61444753f2 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -140,7 +140,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = hppa_cpu_class_by_name;
cc->has_work = hppa_cpu_has_work;
cc->do_interrupt = hppa_cpu_do_interrupt;
- cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index d1414e2970..5e0f2a2fae 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -59,10 +59,10 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
void tcg_cpu_common_class_init(CPUClass *cc)
{
cc->do_interrupt = x86_cpu_do_interrupt;
- cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = x86_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
- cc->cpu_exec_enter = x86_cpu_exec_enter;
- cc->cpu_exec_exit = x86_cpu_exec_exit;
+ cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
+ cc->tcg_ops.cpu_exec_exit = x86_cpu_exec_exit;
cc->tcg_ops.initialize = tcg_x86_init;
cc->tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index ef795b81a4..eea2d3e515 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -223,7 +223,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = lm32_cpu_class_by_name;
cc->has_work = lm32_cpu_has_work;
cc->do_interrupt = lm32_cpu_do_interrupt;
- cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = lm32_cpu_exec_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
cc->gdb_read_register = lm32_cpu_gdb_read_register;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index b66d86c353..c0fa517fc3 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -278,7 +278,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;
cc->do_interrupt = m68k_cpu_do_interrupt;
- cc->cpu_exec_interrupt = m68k_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = m68k_cpu_exec_interrupt;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 97d94d9c27..833d7f2d59 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -319,7 +319,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = mb_cpu_has_work;
cc->do_interrupt = mb_cpu_do_interrupt;
cc->do_unaligned_access = mb_cpu_do_unaligned_access;
- cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 4a539349a9..6c525a6af1 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -237,7 +237,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
cc->do_interrupt = mips_cpu_do_interrupt;
- cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
cc->gdb_read_register = mips_cpu_gdb_read_register;
@@ -251,6 +250,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = mips_tcg_init;
+ cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tlb_fill = mips_cpu_tlb_fill;
#endif
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 29c9c6f634..9eeb01fb5b 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -193,7 +193,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;
cc->do_interrupt = nios2_cpu_do_interrupt;
- cc->cpu_exec_interrupt = nios2_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = nios2_cpu_exec_interrupt;
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index e442f4f97c..df8a41f956 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -155,7 +155,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work;
cc->do_interrupt = openrisc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a9c30879d3..15d58698a6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -540,7 +540,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
cc->do_interrupt = riscv_cpu_do_interrupt;
- cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = riscv_cpu_synchronize_from_tb;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index d03c4e0b05..3ba93590d2 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -186,7 +186,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->class_by_name = rx_cpu_class_by_name;
cc->has_work = rx_cpu_has_work;
cc->do_interrupt = rx_cpu_do_interrupt;
- cc->cpu_exec_interrupt = rx_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = rx_cpu_exec_interrupt;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = rx_cpu_synchronize_from_tb;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 697b94ff7b..add2f4b21f 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -505,7 +505,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
#ifdef CONFIG_TCG
- cc->cpu_exec_interrupt = s390_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
cc->debug_excp_handler = s390x_cpu_debug_excp_handler;
cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
#endif
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index a33025b5c8..0574194cd0 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -219,7 +219,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;
cc->do_interrupt = superh_cpu_do_interrupt;
- cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = superh_cpu_exec_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index baf6c5b587..c559f15e14 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -862,7 +862,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
cc->do_interrupt = sparc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = sparc_cpu_exec_interrupt;
cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index cd24d0eb9d..4c6176d26e 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -148,7 +148,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = tilegx_cpu_class_by_name;
cc->has_work = tilegx_cpu_has_work;
cc->do_interrupt = tilegx_cpu_do_interrupt;
- cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
cc->tlb_fill = tilegx_cpu_tlb_fill;
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 226bf4226e..84c3419989 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -132,7 +132,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = uc32_cpu_class_by_name;
cc->has_work = uc32_cpu_has_work;
cc->do_interrupt = uc32_cpu_do_interrupt;
- cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->tlb_fill = uc32_cpu_tlb_fill;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 5a6f5bf88b..42a5e4ebe8 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -195,7 +195,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;
cc->do_interrupt = xtensa_cpu_do_interrupt;
- cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
+ cc->tcg_ops.cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 9a6932b774..e82c92bcf8 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10765,6 +10765,7 @@ static void ppc_cpu_reset(DeviceState *dev)
}
#ifndef CONFIG_USER_ONLY
+
static bool ppc_cpu_is_big_endian(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -10775,6 +10776,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
return !msr_le;
}
+#ifdef CONFIG_TCG
static void ppc_cpu_exec_enter(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -10796,7 +10798,9 @@ static void ppc_cpu_exec_exit(CPUState *cs)
vhc->cpu_exec_exit(cpu->vhyp, cpu);
}
}
-#endif
+#endif /* CONFIG_TCG */
+
+#endif /* !CONFIG_USER_ONLY */
static void ppc_cpu_instance_init(Object *obj)
{
@@ -10909,7 +10913,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->parse_features = ppc_cpu_parse_featurestr;
cc->has_work = ppc_cpu_has_work;
cc->do_interrupt = ppc_cpu_do_interrupt;
- cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
cc->set_pc = ppc_cpu_set_pc;
@@ -10946,12 +10949,13 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#endif
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = ppc_translate_init;
+ cc->tcg_ops.cpu_exec_interrupt = ppc_cpu_exec_interrupt;
cc->tlb_fill = ppc_cpu_tlb_fill;
-#endif
#ifndef CONFIG_USER_ONLY
- cc->cpu_exec_enter = ppc_cpu_exec_enter;
- cc->cpu_exec_exit = ppc_cpu_exec_exit;
-#endif
+ cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
+ cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
+#endif /* !CONFIG_USER_ONLY */
+#endif /* CONFIG_TCG */
cc->disas_set_info = ppc_disas_set_info;
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 20/25] cpu: Move tlb_fill to tcg_ops
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (18 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 19/25] cpu: Move cpu_exec_* " Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 17:42 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 21/25] cpu: Move debug_excp_handler " Claudio Fontana
` (6 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: wrapped in CONFIG_TCG]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
include/hw/core/cpu.h | 9 ---------
include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++
accel/tcg/cputlb.c | 6 +++---
accel/tcg/user-exec.c | 6 +++---
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
27 files changed, 41 insertions(+), 38 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 52142e9094..c82ef261c6 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -110,12 +110,6 @@ struct TranslationBlock;
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
- * address fault. For system mode, if the access is valid, call
- * tlb_set_page and return true; if the access is invalid, and
- * probe is true, return false; otherwise raise an exception and
- * do not return. For user-only mode, always raise an exception
- * and do not return.
* @get_phys_page_debug: Callback for obtaining a physical address.
* @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
* associated memory transaction attributes to use for the access.
@@ -183,9 +177,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
- MMUAccessType access_type, int mmu_idx,
- bool probe, uintptr_t retaddr);
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index fbd579c2a6..deeabbcf33 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -38,6 +38,18 @@ typedef struct TcgCpuOperations {
void (*cpu_exec_exit)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /**
+ * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
+ *
+ * For system mode, if the access is valid, call tlb_set_page
+ * and return true; if the access is invalid, and probe is
+ * true, return false; otherwise raise an exception and do
+ * not return. For user-only mode, always raise an exception
+ * and do not return.
+ */
+ bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
} TcgCpuOperations;
#endif /* TCG_CPU_OPS_H */
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 42ab79c1a5..2dc71b5528 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1286,7 +1286,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
* This is not a probe, so only valid return is success; failure
* should result in exception + longjmp to the cpu loop.
*/
- ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
+ ok = cc->tcg_ops.tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
assert(ok);
}
@@ -1557,8 +1557,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
CPUState *cs = env_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cs);
- if (!cc->tlb_fill(cs, addr, fault_size, access_type,
- mmu_idx, nonfault, retaddr)) {
+ if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type,
+ mmu_idx, nonfault, retaddr)) {
/* Non-faulting page table read failed. */
*phost = NULL;
return TLB_INVALID_MASK;
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 4ebe25461a..7f53992251 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -186,7 +186,7 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
clear_helper_retaddr();
cc = CPU_GET_CLASS(cpu);
- cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
+ cc->tcg_ops.tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
g_assert_not_reached();
}
@@ -216,8 +216,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
} else {
CPUState *cpu = env_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->tlb_fill(cpu, addr, fault_size, access_type,
- MMU_USER_IDX, false, ra);
+ cc->tcg_ops.tlb_fill(cpu, addr, fault_size, access_type,
+ MMU_USER_IDX, false, ra);
g_assert_not_reached();
}
}
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index d9ced1635a..9f36f824fd 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -223,7 +223,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = alpha_cpu_set_pc;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
- cc->tlb_fill = alpha_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 897db4335a..c9aee4d566 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2264,7 +2264,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.initialize = arm_translate_init;
cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
- cc->tlb_fill = arm_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 277b00dbfc..699055de7c 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -203,7 +203,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->tlb_fill = avr_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = avr_cpu_tlb_fill;
cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->tcg_ops.initialize = avr_cpu_tcg_init;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 7489fc20c8..9222717f3e 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -274,7 +274,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = cris_cpu_set_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
- cc->tlb_fill = cris_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = cris_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 61444753f2..e2d79f954e 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -146,7 +146,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb;
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
- cc->tlb_fill = hppa_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_hppa_cpu;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 5e0f2a2fae..8606dd6a3e 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -64,7 +64,7 @@ void tcg_cpu_common_class_init(CPUClass *cc)
cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
cc->tcg_ops.cpu_exec_exit = x86_cpu_exec_exit;
cc->tcg_ops.initialize = tcg_x86_init;
- cc->tlb_fill = x86_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->debug_excp_handler = breakpoint_handler;
#endif
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index eea2d3e515..76dc728858 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -228,7 +228,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = lm32_cpu_set_pc;
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
- cc->tlb_fill = lm32_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = lm32_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index c0fa517fc3..bc109faa21 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -283,7 +283,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->set_pc = m68k_cpu_set_pc;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
- cc->tlb_fill = m68k_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill;
#if defined(CONFIG_SOFTMMU)
cc->do_transaction_failed = m68k_cpu_transaction_failed;
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 833d7f2d59..6e660a27b8 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -325,7 +325,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = mb_cpu_synchronize_from_tb;
cc->gdb_read_register = mb_cpu_gdb_read_register;
cc->gdb_write_register = mb_cpu_gdb_write_register;
- cc->tlb_fill = mb_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = mb_cpu_transaction_failed;
cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 6c525a6af1..b258560da9 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -252,7 +252,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.initialize = mips_tcg_init;
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
- cc->tlb_fill = mips_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
#endif
cc->gdb_num_core_regs = 73;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 224cfc8361..1177d092c1 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -110,7 +110,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
- cc->tlb_fill = moxie_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = moxie_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_moxie_cpu;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 9eeb01fb5b..a96b74b00c 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -197,7 +197,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
- cc->tlb_fill = nios2_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = nios2_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = nios2_cpu_do_unaligned_access;
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index df8a41f956..e6d1c9764b 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -160,7 +160,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = openrisc_cpu_set_pc;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
- cc->tlb_fill = openrisc_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = openrisc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 15d58698a6..31a43f7bfb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -562,7 +562,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->vmsd = &vmstate_riscv_cpu;
#endif
cc->tcg_ops.initialize = riscv_translate_init;
- cc->tlb_fill = riscv_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = riscv_cpu_tlb_fill;
device_class_set_props(dc, riscv_cpu_properties);
}
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 3ba93590d2..c815533223 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -195,7 +195,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
cc->tcg_ops.initialize = rx_translate_init;
- cc->tlb_fill = rx_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = rx_cpu_tlb_fill;
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "rx-core.xml";
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index add2f4b21f..6cd2b30192 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -513,7 +513,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = s390_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = s390x_translate_init;
- cc->tlb_fill = s390_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = s390_cpu_tlb_fill;
#endif
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 0574194cd0..7a9019edec 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -225,7 +225,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = superh_cpu_synchronize_from_tb;
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
- cc->tlb_fill = superh_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = superh_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = superh_cpu_do_unaligned_access;
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index c559f15e14..760e0ea92c 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -871,7 +871,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb;
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
- cc->tlb_fill = sparc_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_transaction_failed = sparc_cpu_do_transaction_failed;
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 4c6176d26e..75b3a4bae3 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -151,7 +151,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
- cc->tlb_fill = tilegx_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = tilegx_cpu_tlb_fill;
cc->gdb_num_core_regs = 0;
cc->tcg_ops.initialize = tilegx_tcg_init;
}
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 5edf96c600..89a14f81d7 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -165,7 +165,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.synchronize_from_tb = tricore_cpu_synchronize_from_tb;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->tcg_ops.initialize = tricore_tcg_init;
- cc->tlb_fill = tricore_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = tricore_cpu_tlb_fill;
}
#define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 84c3419989..a57d315d2f 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -135,7 +135,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
- cc->tlb_fill = uc32_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = uc32_cpu_tlb_fill;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
cc->tcg_ops.initialize = uc32_translate_init;
dc->vmsd = &vmstate_uc32_cpu;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 42a5e4ebe8..e764dbeb73 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -201,7 +201,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
- cc->tlb_fill = xtensa_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = xtensa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index e82c92bcf8..16d92f0a49 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10950,7 +10950,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = ppc_translate_init;
cc->tcg_ops.cpu_exec_interrupt = ppc_cpu_exec_interrupt;
- cc->tlb_fill = ppc_cpu_tlb_fill;
+ cc->tcg_ops.tlb_fill = ppc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 21/25] cpu: Move debug_excp_handler to tcg_ops
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (19 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 20/25] cpu: Move tlb_fill " Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 17:44 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 22/25] target/arm: do not use cc->do_interrupt for KVM directly Claudio Fontana
` (5 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota,
Claudio Fontana
From: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/tcg-cpu-ops.h | 2 ++
accel/tcg/cpu-exec.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
8 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c82ef261c6..f438abb785 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -121,7 +121,6 @@ struct TranslationBlock;
* @gdb_write_register: Callback for letting GDB write a register.
* @debug_check_watchpoint: Callback: return true if the architectural
* watchpoint whose address has matched should really fire.
- * @debug_excp_handler: Callback for handling debug exceptions.
* @write_elf64_note: Callback for writing a CPU-specific ELF note to a
* 64-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
@@ -184,7 +183,6 @@ struct CPUClass {
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
- void (*debug_excp_handler)(CPUState *cpu);
int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque);
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index deeabbcf33..322204c441 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -50,6 +50,8 @@ typedef struct TcgCpuOperations {
bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+ /** @debug_excp_handler: Callback for handling debug exceptions */
+ void (*debug_excp_handler)(CPUState *cpu);
} TcgCpuOperations;
#endif /* TCG_CPU_OPS_H */
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 502f6a53ae..17dc86af50 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -482,8 +482,8 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
}
}
- if (cc->debug_excp_handler) {
- cc->debug_excp_handler(cpu);
+ if (cc->tcg_ops.debug_excp_handler) {
+ cc->tcg_ops.debug_excp_handler(cpu);
}
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c9aee4d566..d27bc5ef0a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2265,7 +2265,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
- cc->debug_excp_handler = arm_debug_excp_handler;
+ cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 8606dd6a3e..38ed8bf6d3 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -66,6 +66,6 @@ void tcg_cpu_common_class_init(CPUClass *cc)
cc->tcg_ops.initialize = tcg_x86_init;
cc->tcg_ops.tlb_fill = x86_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->debug_excp_handler = breakpoint_handler;
+ cc->tcg_ops.debug_excp_handler = breakpoint_handler;
#endif
}
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 76dc728858..bbe1405e32 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -235,7 +235,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
- cc->debug_excp_handler = lm32_debug_excp_handler;
+ cc->tcg_ops.debug_excp_handler = lm32_debug_excp_handler;
cc->disas_set_info = lm32_cpu_disas_set_info;
cc->tcg_ops.initialize = lm32_translate_init;
}
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 6cd2b30192..04856076b3 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -506,7 +506,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->write_elf64_note = s390_cpu_write_elf64_note;
#ifdef CONFIG_TCG
cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
- cc->debug_excp_handler = s390x_cpu_debug_excp_handler;
+ cc->tcg_ops.debug_excp_handler = s390x_cpu_debug_excp_handler;
cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
#endif
#endif
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e764dbeb73..b6f13ceb32 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -207,7 +207,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
- cc->debug_excp_handler = xtensa_breakpoint_handler;
+ cc->tcg_ops.debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
cc->tcg_ops.initialize = xtensa_translate_init;
dc->vmsd = &vmstate_xtensa_cpu;
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 22/25] target/arm: do not use cc->do_interrupt for KVM directly
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (20 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 21/25] cpu: Move debug_excp_handler " Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 17:44 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 23/25] cpu: move cc->do_interrupt to tcg_ops Claudio Fontana
` (4 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team,
Claudio Fontana, Anthony Perard, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
cc->do_interrupt is in theory a TCG callback used in accel/tcg only,
to prepare the emulated architecture to take an interrupt as defined
in the hardware specifications,
but in reality the _do_interrupt style of functions in targets are
also occasionally reused by KVM to prepare the architecture state in a
similar way where userspace code has identified that it needs to
deliver an exception to the guest.
In the case of ARM, that includes:
1) the vcpu thread got a SIGBUS indicating a memory error,
and we need to deliver a Synchronous External Abort to the guest to
let it know about the error.
2) the kernel told us about a debug exception (breakpoint, watchpoint)
but it is not for one of QEMU's own gdbstub breakpoints/watchpoints
so it must be a breakpoint the guest itself has set up, therefore
we need to deliver it to the guest.
So in order to reuse code, the same arm_do_interrupt function is used.
This is all fine, but we need to avoid calling it using the callback
registered in CPUClass, since that one is now TCG-only.
Fortunately this is easily solved by replacing calls to
CPUClass::do_interrupt() with explicit calls to arm_do_interrupt().
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/arm/helper.c | 4 ++++
target/arm/kvm64.c | 6 ++----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 38cd35c049..bebaabf525 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9895,6 +9895,10 @@ static void handle_semihosting(CPUState *cs)
* Do any appropriate logging, handle PSCI calls, and then hand off
* to the AArch64-entry or AArch32-entry function depending on the
* target exception level's register width.
+ *
+ * Note: this is used for both TCG (as the do_interrupt tcg op),
+ * and KVM to re-inject guest debug exceptions, and to
+ * inject a Synchronous-External-Abort.
*/
void arm_cpu_do_interrupt(CPUState *cs)
{
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index f74bac2457..3728b3a336 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -944,7 +944,6 @@ static void kvm_inject_arm_sea(CPUState *c)
{
ARMCPU *cpu = ARM_CPU(c);
CPUARMState *env = &cpu->env;
- CPUClass *cc = CPU_GET_CLASS(c);
uint32_t esr;
bool same_el;
@@ -960,7 +959,7 @@ static void kvm_inject_arm_sea(CPUState *c)
env->exception.syndrome = esr;
- cc->do_interrupt(c);
+ arm_cpu_do_interrupt(c);
}
#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
@@ -1491,7 +1490,6 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
{
int hsr_ec = syn_get_ec(debug_exit->hsr);
ARMCPU *cpu = ARM_CPU(cs);
- CPUClass *cc = CPU_GET_CLASS(cs);
CPUARMState *env = &cpu->env;
/* Ensure PC is synchronised */
@@ -1545,7 +1543,7 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
env->exception.vaddress = debug_exit->far;
env->exception.target_el = 1;
qemu_mutex_lock_iothread();
- cc->do_interrupt(cs);
+ arm_cpu_do_interrupt(cs);
qemu_mutex_unlock_iothread();
return false;
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 23/25] cpu: move cc->do_interrupt to tcg_ops
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (21 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 22/25] target/arm: do not use cc->do_interrupt for KVM directly Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 17:46 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 24/25] cpu: move cc->transaction_failed " Claudio Fontana
` (3 subsequent siblings)
26 siblings, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team,
Claudio Fontana, Anthony Perard, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/tcg-cpu-ops.h | 3 +++
accel/tcg/cpu-exec.c | 4 ++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 4 ++--
target/arm/cpu_tcg.c | 9 ++++-----
target/avr/cpu.c | 2 +-
target/avr/helper.c | 4 ++--
target/cris/cpu.c | 12 ++++++------
target/cris/helper.c | 4 ++--
target/hppa/cpu.c | 2 +-
target/i386/tcg/tcg-cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 ++--
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tilegx/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
28 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index f438abb785..b178549d48 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -87,7 +87,6 @@ struct TranslationBlock;
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @do_interrupt: Callback for interrupt handling.
* @do_unaligned_access: Callback for unaligned access handling, if
* the target defines #TARGET_ALIGNED_ONLY.
* @do_transaction_failed: Callback for handling failed memory transactions
@@ -157,7 +156,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- void (*do_interrupt)(CPUState *cpu);
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 322204c441..a7387b5c39 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -38,6 +38,9 @@ typedef struct TcgCpuOperations {
void (*cpu_exec_exit)(CPUState *cpu);
/** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
+ /** @do_interrupt: Callback for interrupt handling. */
+ void (*do_interrupt)(CPUState *cpu);
+
/**
* @tlb_fill: Handle a softmmu tlb miss or user-only address fault
*
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 17dc86af50..eafd600085 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -517,7 +517,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
loop */
#if defined(TARGET_I386)
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->do_interrupt(cpu);
+ cc->tcg_ops.do_interrupt(cpu);
#endif
*ret = cpu->exception_index;
cpu->exception_index = -1;
@@ -526,7 +526,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
if (replay_exception()) {
CPUClass *cc = CPU_GET_CLASS(cpu);
qemu_mutex_lock_iothread();
- cc->do_interrupt(cpu);
+ cc->tcg_ops.do_interrupt(cpu);
qemu_mutex_unlock_iothread();
cpu->exception_index = -1;
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 9f36f824fd..66f1166672 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -217,7 +217,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = alpha_cpu_class_by_name;
cc->has_work = alpha_cpu_has_work;
- cc->do_interrupt = alpha_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = alpha_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = alpha_cpu_exec_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d27bc5ef0a..1d0fe58771 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -586,7 +586,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
found:
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
return true;
}
@@ -2246,7 +2246,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_interrupt = arm_cpu_do_interrupt;
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->vmsd = &vmstate_arm_cpu;
@@ -2271,6 +2270,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#if !defined(CONFIG_USER_ONLY)
cc->do_transaction_failed = arm_cpu_do_transaction_failed;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
+ cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
#endif
}
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index e261839d08..451a6a5a40 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -34,7 +34,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_HARD
&& (armv7m_nvic_can_take_pending_exception(env->nvic))) {
cs->exception_index = EXCP_IRQ;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
ret = true;
}
return ret;
@@ -626,12 +626,11 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
acc->info = data;
+#ifdef CONFIG_TCG
+ cc->tcg_ops.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
#ifndef CONFIG_USER_ONLY
- cc->do_interrupt = arm_v7m_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = arm_v7m_cpu_do_interrupt;
#endif
-
-#ifdef CONFIG_TCG
- cc->tcg_ops.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
#endif /* CONFIG_TCG */
cc->gdb_core_xml_file = "arm-m-profile.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 699055de7c..5a5ae68444 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -197,7 +197,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = avr_cpu_class_by_name;
cc->has_work = avr_cpu_has_work;
- cc->do_interrupt = avr_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = avr_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = avr_cpu_exec_interrupt;
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
diff --git a/target/avr/helper.c b/target/avr/helper.c
index d96d14372b..69d3b6181f 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -34,7 +34,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_RESET) {
if (cpu_interrupts_enabled(env)) {
cs->exception_index = EXCP_RESET;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
@@ -45,7 +45,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
int index = ctz32(env->intsrc);
cs->exception_index = EXCP_INT(index);
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
env->intsrc &= env->intsrc - 1; /* clear the interrupt */
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 9222717f3e..b65743e8ca 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -199,7 +199,7 @@ static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 8;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -210,7 +210,7 @@ static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 9;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -221,7 +221,7 @@ static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 10;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -232,7 +232,7 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 11;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -243,7 +243,7 @@ static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ccc->vr = 17;
- cc->do_interrupt = crisv10_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = crisv10_cpu_do_interrupt;
cc->gdb_read_register = crisv10_cpu_gdb_read_register;
cc->tcg_ops.initialize = cris_initialize_crisv10_tcg;
}
@@ -268,7 +268,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work;
- cc->do_interrupt = cris_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = cris_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = cris_cpu_exec_interrupt;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
diff --git a/target/cris/helper.c b/target/cris/helper.c
index ed45c3d9b7..1f4d6f7d45 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -299,7 +299,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
&& (env->pregs[PR_CCS] & I_FLAG)
&& !env->locked_irq) {
cs->exception_index = EXCP_IRQ;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
ret = true;
}
if (interrupt_request & CPU_INTERRUPT_NMI) {
@@ -311,7 +311,7 @@ bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
if ((env->pregs[PR_CCS] & m_flag_archval)) {
cs->exception_index = EXCP_NMI;
- cc->do_interrupt(cs);
+ cc->tcg_ops.do_interrupt(cs);
ret = true;
}
}
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index e2d79f954e..cce6ae6213 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -139,7 +139,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = hppa_cpu_class_by_name;
cc->has_work = hppa_cpu_has_work;
- cc->do_interrupt = hppa_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = hppa_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = hppa_cpu_exec_interrupt;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 38ed8bf6d3..d2dd521612 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -58,7 +58,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
void tcg_cpu_common_class_init(CPUClass *cc)
{
- cc->do_interrupt = x86_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = x86_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = x86_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index bbe1405e32..fb3761b749 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -222,7 +222,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = lm32_cpu_class_by_name;
cc->has_work = lm32_cpu_has_work;
- cc->do_interrupt = lm32_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = lm32_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = lm32_cpu_exec_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index bc109faa21..3e84de772c 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -277,7 +277,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;
- cc->do_interrupt = m68k_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = m68k_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = m68k_cpu_exec_interrupt;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 6e660a27b8..4f95248b2e 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -317,7 +317,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;
- cc->do_interrupt = mb_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = mb_cpu_do_interrupt;
cc->do_unaligned_access = mb_cpu_do_unaligned_access;
cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index b258560da9..25c4a55a6a 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -236,7 +236,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
- cc->do_interrupt = mips_cpu_do_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
cc->gdb_read_register = mips_cpu_gdb_read_register;
@@ -250,10 +249,11 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = mips_cpu_disas_set_info;
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = mips_tcg_init;
+ cc->tcg_ops.do_interrupt = mips_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
-#endif
+#endif /* CONFIG_TCG */
cc->gdb_num_core_regs = 73;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 1177d092c1..36bef4d357 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -107,7 +107,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = moxie_cpu_class_by_name;
cc->has_work = moxie_cpu_has_work;
- cc->do_interrupt = moxie_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
cc->tcg_ops.tlb_fill = moxie_cpu_tlb_fill;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index a96b74b00c..2b959f0e49 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -192,7 +192,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;
- cc->do_interrupt = nios2_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = nios2_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = nios2_cpu_exec_interrupt;
cc->dump_state = nios2_cpu_dump_state;
cc->set_pc = nios2_cpu_set_pc;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index e6d1c9764b..27105c5c09 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -154,7 +154,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work;
- cc->do_interrupt = openrisc_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = openrisc_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 31a43f7bfb..6a815569cc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -539,7 +539,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
- cc->do_interrupt = riscv_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = riscv_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = riscv_cpu_exec_interrupt;
cc->dump_state = riscv_cpu_dump_state;
cc->set_pc = riscv_cpu_set_pc;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index c815533223..dc7d1c3c57 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -185,7 +185,7 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->class_by_name = rx_cpu_class_by_name;
cc->has_work = rx_cpu_has_work;
- cc->do_interrupt = rx_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = rx_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = rx_cpu_exec_interrupt;
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 04856076b3..b838bd61a4 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -493,7 +493,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = s390_cpu_class_by_name,
cc->has_work = s390_cpu_has_work;
#ifdef CONFIG_TCG
- cc->do_interrupt = s390_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = s390_cpu_do_interrupt;
#endif
cc->dump_state = s390_cpu_dump_state;
cc->set_pc = s390_cpu_set_pc;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 7a9019edec..ff835d4bc1 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -218,7 +218,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;
- cc->do_interrupt = superh_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = superh_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = superh_cpu_exec_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 760e0ea92c..3f23aa5962 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -861,7 +861,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = sparc_cpu_class_by_name;
cc->parse_features = sparc_cpu_parse_features;
cc->has_work = sparc_cpu_has_work;
- cc->do_interrupt = sparc_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = sparc_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = sparc_cpu_exec_interrupt;
cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 75b3a4bae3..7d4ead4ef1 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -147,7 +147,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = tilegx_cpu_class_by_name;
cc->has_work = tilegx_cpu_has_work;
- cc->do_interrupt = tilegx_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = tilegx_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index a57d315d2f..e27ffc571a 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -131,7 +131,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = uc32_cpu_class_by_name;
cc->has_work = uc32_cpu_has_work;
- cc->do_interrupt = uc32_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = uc32_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = uc32_cpu_exec_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index b6f13ceb32..3ff025f0fe 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -194,7 +194,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;
- cc->do_interrupt = xtensa_cpu_do_interrupt;
+ cc->tcg_ops.do_interrupt = xtensa_cpu_do_interrupt;
cc->tcg_ops.cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 16d92f0a49..dc13ff2cf8 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10912,7 +10912,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
pcc->parent_parse_features = cc->parse_features;
cc->parse_features = ppc_cpu_parse_featurestr;
cc->has_work = ppc_cpu_has_work;
- cc->do_interrupt = ppc_cpu_do_interrupt;
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
cc->set_pc = ppc_cpu_set_pc;
@@ -10950,6 +10949,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops.initialize = ppc_translate_init;
cc->tcg_ops.cpu_exec_interrupt = ppc_cpu_exec_interrupt;
+ cc->tcg_ops.do_interrupt = ppc_cpu_do_interrupt;
cc->tcg_ops.tlb_fill = ppc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 24/25] cpu: move cc->transaction_failed to tcg_ops
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (22 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 23/25] cpu: move cc->do_interrupt to tcg_ops Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 11:00 ` Philippe Mathieu-Daudé
2020-12-11 17:50 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 25/25] cpu: move do_unaligned_access " Claudio Fontana
` (2 subsequent siblings)
26 siblings, 2 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team,
Claudio Fontana, Anthony Perard, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
include/hw/core/cpu.h | 18 +++++++-----------
include/hw/core/tcg-cpu-ops.h | 14 ++++++++++++++
hw/mips/jazz.c | 9 +++++++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 4 ++--
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 +++-
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 2 +-
target/sparc/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/xtensa/helper.c | 4 ++--
13 files changed, 42 insertions(+), 25 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b178549d48..0c6c17fb48 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -89,8 +89,6 @@ struct TranslationBlock;
* @has_work: Callback for checking if there is work to do.
* @do_unaligned_access: Callback for unaligned access handling, if
* the target defines #TARGET_ALIGNED_ONLY.
- * @do_transaction_failed: Callback for handling failed memory transactions
- * (ie bus faults or external aborts; not MMU faults)
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian. Non-configurable
* CPUs can use the default implementation of this method. This method should
@@ -159,10 +157,6 @@ struct CPUClass {
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
- void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
- unsigned size, MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
@@ -848,7 +842,7 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
}
-
+#ifdef CONFIG_TCG
static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -858,12 +852,14 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) {
- cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
- mmu_idx, attrs, response, retaddr);
+ if (!cpu->ignore_memory_transaction_failures &&
+ cc->tcg_ops.do_transaction_failed) {
+ cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size, access_type,
+ mmu_idx, attrs, response, retaddr);
}
}
-#endif
+#endif /* CONFIG_TCG */
+#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index a7387b5c39..dbf17c4f96 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -11,6 +11,7 @@
#define TCG_CPU_OPS_H
#include "hw/core/cpu.h"
+#include "exec/memattrs.h"
/**
* struct TcgCpuOperations: TCG operations specific to a CPU class
@@ -55,6 +56,19 @@ typedef struct TcgCpuOperations {
bool probe, uintptr_t retaddr);
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
+
+#ifndef CONFIG_USER_ONLY
+ /**
+ * @do_transaction_failed: Callback for handling failed memory transactions
+ * (ie bus faults or external aborts; not MMU faults)
+ */
+ void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
+ unsigned size, MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
+
+#endif /* !CONFIG_USER_ONLY */
+
} TcgCpuOperations;
#endif /* TCG_CPU_OPS_H */
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 71448f72ac..753256d377 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -115,6 +115,8 @@ static const MemoryRegionOps dma_dummy_ops = {
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE \
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
+
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -136,6 +138,7 @@ static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
(*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
mmu_idx, attrs, response, retaddr);
}
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
@@ -204,8 +207,10 @@ static void mips_jazz_init(MachineState *machine,
* memory region that catches all memory accesses, as we do on Malta.
*/
cc = CPU_GET_CLASS(cpu);
- real_do_transaction_failed = cc->do_transaction_failed;
- cc->do_transaction_failed = mips_jazz_do_transaction_failed;
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
+ real_do_transaction_failed = cc->tcg_ops.do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = mips_jazz_do_transaction_failed;
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
/* allocate RAM */
memory_region_add_subregion(address_space, 0, machine->ram);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 66f1166672..a1696bebeb 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -225,7 +225,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 1d0fe58771..39663d2861 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2268,11 +2268,11 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
- cc->do_transaction_failed = arm_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
-#endif
+#endif /* CONFIG_TCG */
}
#ifdef CONFIG_KVM
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 3e84de772c..3f60c99865 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -285,7 +285,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill;
#if defined(CONFIG_SOFTMMU)
- cc->do_transaction_failed = m68k_cpu_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = m68k_cpu_transaction_failed;
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 4f95248b2e..fa57a324dc 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -327,7 +327,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = mb_cpu_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = mb_cpu_transaction_failed;
cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_mb_cpu;
#endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 25c4a55a6a..fe8bca41b7 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -241,7 +241,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = mips_cpu_do_transaction_failed;
cc->do_unaligned_access = mips_cpu_do_unaligned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
@@ -253,6 +252,9 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
+#ifndef CONFIG_USER_ONLY
+ cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
+#endif /* CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
cc->gdb_num_core_regs = 73;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6a815569cc..7dfd8d7339 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -555,7 +555,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = riscv_cpu_do_transaction_failed;
cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a2787b1d48..4c3e0382ce 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -667,7 +667,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
env->badaddr = addr;
riscv_raise_exception(env, cs->exception_index, retaddr);
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 3f23aa5962..009d0f07c3 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -873,7 +873,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = sparc_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 3ff025f0fe..fc52fde696 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -205,7 +205,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
- cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
cc->tcg_ops.debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index 05e2b7f70a..eeffee297d 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -261,7 +261,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
cpu_loop_exit_restore(cs, retaddr);
}
-#else
+#else /* !CONFIG_USER_ONLY */
void xtensa_cpu_do_unaligned_access(CPUState *cs,
vaddr addr, MMUAccessType access_type,
@@ -337,4 +337,4 @@ void xtensa_runstall(CPUXtensaState *env, bool runstall)
qemu_cpu_kick(cpu);
}
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* [PATCH v11 25/25] cpu: move do_unaligned_access to tcg_ops
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (23 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 24/25] cpu: move cc->transaction_failed " Claudio Fontana
@ 2020-12-11 8:31 ` Claudio Fontana
2020-12-11 11:01 ` Philippe Mathieu-Daudé
2020-12-11 17:58 ` Richard Henderson
2020-12-11 8:57 ` [PATCH v11 00/25] i386 cleanup PART 1 no-reply
2020-12-11 11:07 ` Philippe Mathieu-Daudé
26 siblings, 2 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 8:31 UTC (permalink / raw)
To: Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team,
Claudio Fontana, Anthony Perard, Bruce Rogers, Olaf Hering,
Emilio G . Cota, Colin Xu
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
include/hw/core/cpu.h | 17 +++--------------
include/hw/core/tcg-cpu-ops.h | 7 +++++++
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/hppa/cpu.c | 4 +++-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 3 ++-
target/nios2/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/s390x/excp_helper.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
15 files changed, 26 insertions(+), 27 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 0c6c17fb48..db54223983 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -87,8 +87,6 @@ struct TranslationBlock;
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @do_unaligned_access: Callback for unaligned access handling, if
- * the target defines #TARGET_ALIGNED_ONLY.
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian. Non-configurable
* CPUs can use the default implementation of this method. This method should
@@ -154,9 +152,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr);
bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
@@ -831,18 +826,15 @@ CPUState *cpu_by_arch_id(int64_t id);
void cpu_interrupt(CPUState *cpu, int mask);
-#ifdef NEED_CPU_H
-
-#ifdef CONFIG_SOFTMMU
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
+ cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
}
-#ifdef CONFIG_TCG
static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -858,10 +850,7 @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
mmu_idx, attrs, response, retaddr);
}
}
-#endif /* CONFIG_TCG */
-#endif /* CONFIG_SOFTMMU */
-
-#endif /* NEED_CPU_H */
+#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
/**
* cpu_set_pc:
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index dbf17c4f96..e92e0ea536 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -66,6 +66,13 @@ typedef struct TcgCpuOperations {
unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
+ /**
+ * @do_unaligned_access: Callback for unaligned access handling, if
+ * the target defines #TARGET_ALIGNED_ONLY.
+ */
+ void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr);
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index a1696bebeb..0710298e5a 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -226,7 +226,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
- cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = alpha_cpu_do_unaligned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
#endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 39663d2861..1ba11698eb 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2266,9 +2266,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
- cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
+ cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index cce6ae6213..0985b3661f 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -70,6 +70,7 @@ static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
info->print_insn = print_insn_hppa;
}
+#ifndef CONFIG_USER_ONLY
static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
@@ -86,6 +87,7 @@ static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
cpu_loop_exit_restore(cs, retaddr);
}
+#endif /* CONFIG_USER_ONLY */
static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
{
@@ -149,9 +151,9 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
+ cc->tcg_ops.do_unaligned_access = hppa_cpu_do_unaligned_access;
dc->vmsd = &vmstate_hppa_cpu;
#endif
- cc->do_unaligned_access = hppa_cpu_do_unaligned_access;
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->tcg_ops.initialize = hppa_translate_init;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index fa57a324dc..395f4a300f 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -318,7 +318,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;
cc->tcg_ops.do_interrupt = mb_cpu_do_interrupt;
- cc->do_unaligned_access = mb_cpu_do_unaligned_access;
cc->tcg_ops.cpu_exec_interrupt = mb_cpu_exec_interrupt;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
@@ -328,6 +327,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = mb_cpu_transaction_failed;
+ cc->tcg_ops.do_unaligned_access = mb_cpu_do_unaligned_access;
cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_mb_cpu;
#endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index fe8bca41b7..e99c692e2d 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -241,7 +241,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = mips_cpu_do_unaligned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
#endif
@@ -254,6 +253,8 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
+ cc->tcg_ops.do_unaligned_access = mips_cpu_do_unaligned_access;
+
#endif /* CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 2b959f0e49..059eea8c94 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -199,7 +199,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = nios2_cpu_disas_set_info;
cc->tcg_ops.tlb_fill = nios2_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = nios2_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = nios2_cpu_do_unaligned_access;
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7dfd8d7339..e5626862c2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -556,7 +556,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = riscv_cpu_do_transaction_failed;
- cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index b838bd61a4..86f654fd6b 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -507,7 +507,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
#ifdef CONFIG_TCG
cc->tcg_ops.cpu_exec_interrupt = s390_cpu_exec_interrupt;
cc->tcg_ops.debug_excp_handler = s390x_cpu_debug_excp_handler;
- cc->do_unaligned_access = s390x_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = s390x_cpu_do_unaligned_access;
#endif
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index 0adfbbda27..abe5e3c62a 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -633,4 +633,4 @@ void HELPER(monitor_call)(CPUS390XState *env, uint64_t monitor_code,
}
}
-#endif /* CONFIG_USER_ONLY */
+#endif /* !CONFIG_USER_ONLY */
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ff835d4bc1..fbd5f42675 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -227,7 +227,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = superh_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = superh_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = superh_cpu_do_unaligned_access;
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 009d0f07c3..3b53ef2390 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -874,7 +874,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
- cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
#endif
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index fc52fde696..4b6381569f 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -203,7 +203,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->tcg_ops.tlb_fill = xtensa_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
+ cc->tcg_ops.do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
cc->tcg_ops.do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index dc13ff2cf8..3fbec30a65 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10917,7 +10917,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = ppc_cpu_set_pc;
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
- cc->do_unaligned_access = ppc_cpu_do_unaligned_access;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_ppc_cpu;
@@ -10954,6 +10953,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->tcg_ops.cpu_exec_enter = ppc_cpu_exec_enter;
cc->tcg_ops.cpu_exec_exit = ppc_cpu_exec_exit;
+ cc->tcg_ops.do_unaligned_access = ppc_cpu_do_unaligned_access;
#endif /* !CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
--
2.26.2
^ permalink raw reply related [flat|nested] 69+ messages in thread
* Re: [PATCH v11 00/25] i386 cleanup PART 1
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (24 preceding siblings ...)
2020-12-11 8:31 ` [PATCH v11 25/25] cpu: move do_unaligned_access " Claudio Fontana
@ 2020-12-11 8:57 ` no-reply
2020-12-11 11:07 ` Philippe Mathieu-Daudé
26 siblings, 0 replies; 69+ messages in thread
From: no-reply @ 2020-12-11 8:57 UTC (permalink / raw)
To: cfontana
Cc: peter.maydell, paul, jasowang, qemu-devel, peterx, haxm-team,
colin.xu, ohering, sstabellini, brogers, cota, cfontana,
anthony.perard, philmd, lvivier, thuth, ehabkost,
richard.henderson, dirty, dfaggioli, r.bolshakov, sunilmut,
mtosatti, wenchao.wang, pbonzini
Patchew URL: https://patchew.org/QEMU/20201211083143.14350-1-cfontana@suse.de/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20201211083143.14350-1-cfontana@suse.de
Subject: [PATCH v11 00/25] i386 cleanup PART 1
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20201210190417.31673-1-alex.bennee@linaro.org -> patchew/20201210190417.31673-1-alex.bennee@linaro.org
- [tag update] patchew/20201210223506.263709-1-philmd@redhat.com -> patchew/20201210223506.263709-1-philmd@redhat.com
* [new tag] patchew/20201211083143.14350-1-cfontana@suse.de -> patchew/20201211083143.14350-1-cfontana@suse.de
Switched to a new branch 'test'
a3c83d9 cpu: move do_unaligned_access to tcg_ops
0aecd32 cpu: move cc->transaction_failed to tcg_ops
f569b71 cpu: move cc->do_interrupt to tcg_ops
d72487e target/arm: do not use cc->do_interrupt for KVM directly
32ccc60 cpu: Move debug_excp_handler to tcg_ops
7bb4177 cpu: Move tlb_fill to tcg_ops
79fab44 cpu: Move cpu_exec_* to tcg_ops
cb83174 cpu: Move synchronize_from_tb() to tcg_ops
ecfd44d accel/tcg: split TCG-only code from cpu_exec_realizefn
de4c296 target/riscv: remove CONFIG_TCG, as it is always TCG
c279736 cpu: Introduce TCGCpuOperations struct
bd1deaa cpu: Remove unnecessary noop methods
07018b9 tcg: Make CPUClass.debug_excp_handler optional
e331244 tcg: make CPUClass.cpu_exec_* optional
b26f65d tcg: cpu_exec_{enter,exit} helpers
d7314ca i386: move TCG cpu class initialization out of helper.c
658aed7 i386: move cpu dump out of helper.c into cpu-dump.c
4afbc49 i386: move TCG accel files into tcg/
5904058 i386: hvf: remove stale MAINTAINERS entry for old hvf stubs
ddfe357 i386: move hax accel files into hax/
01e7019 i386: move whpx accel files into whpx/
5f8a34a i386: move kvm accel files into kvm/
1811a42 accel/tcg: rename tcg-cpus functions to match module name
b20ad72 accel/tcg: split tcg_start_vcpu_thread
93622c5 accel/tcg: split CpusAccel into three TCG variants
=== OUTPUT BEGIN ===
1/25 Checking commit 93622c51d180 (accel/tcg: split CpusAccel into three TCG variants)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#57:
new file mode 100644
total: 0 errors, 1 warnings, 1156 lines checked
Patch 1/25 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/25 Checking commit b20ad7218d38 (accel/tcg: split tcg_start_vcpu_thread)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#103:
deleted file mode 100644
total: 0 errors, 1 warnings, 201 lines checked
Patch 2/25 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/25 Checking commit 1811a42dd7b5 (accel/tcg: rename tcg-cpus functions to match module name)
4/25 Checking commit 5f8a34a38c95 (i386: move kvm accel files into kvm/)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#168:
rename from target/i386/hyperv-proto.h
total: 0 errors, 1 warnings, 150 lines checked
Patch 4/25 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/25 Checking commit 01e70198abda (i386: move whpx accel files into whpx/)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 32 lines checked
Patch 5/25 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/25 Checking commit ddfe3572963a (i386: move hax accel files into hax/)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#26:
rename from target/i386/hax-all.c
total: 0 errors, 1 warnings, 47 lines checked
Patch 6/25 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/25 Checking commit 59040585f5e0 (i386: hvf: remove stale MAINTAINERS entry for old hvf stubs)
8/25 Checking commit 4afbc49cc900 (i386: move TCG accel files into tcg/)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#45:
rename from target/i386/bpt_helper.c
total: 0 errors, 1 warnings, 39 lines checked
Patch 8/25 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/25 Checking commit 658aed78b5fa (i386: move cpu dump out of helper.c into cpu-dump.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#12:
new file mode 100644
ERROR: braces {} are necessary for all arms of this statement
#129: FILE: target/i386/cpu-dump.c:113:
+ if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
[...]
WARNING: Block comments use a leading /* on a separate line
#173: FILE: target/i386/cpu-dump.c:157:
+/* ARRAY_SIZE check is not required because
WARNING: Block comments use a leading /* on a separate line
#212: FILE: target/i386/cpu-dump.c:196:
+/* ARRAY_SIZE check is not required because
ERROR: line over 90 characters
#374: FILE: target/i386/cpu-dump.c:358:
+ qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
ERROR: line over 90 characters
#375: FILE: target/i386/cpu-dump.c:359:
+ "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
ERROR: line over 90 characters
#376: FILE: target/i386/cpu-dump.c:360:
+ "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
ERROR: line over 90 characters
#377: FILE: target/i386/cpu-dump.c:361:
+ "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
ERROR: line over 90 characters
#378: FILE: target/i386/cpu-dump.c:362:
+ "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
ERROR: space required before the open parenthesis '('
#437: FILE: target/i386/cpu-dump.c:421:
+ for(i = 0; i < 6; i++) {
WARNING: line over 80 characters
#449: FILE: target/i386/cpu-dump.c:433:
+ qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
ERROR: space required before the open parenthesis '('
#454: FILE: target/i386/cpu-dump.c:438:
+ for(i = 0; i < 4; i++)
ERROR: braces {} are necessary for all arms of this statement
#454: FILE: target/i386/cpu-dump.c:438:
+ for(i = 0; i < 4; i++)
[...]
ERROR: space required before the open parenthesis '('
#470: FILE: target/i386/cpu-dump.c:454:
+ for(i = 0; i < 4; i++) {
ERROR: braces {} are necessary for all arms of this statement
#477: FILE: target/i386/cpu-dump.c:461:
+ if ((unsigned)env->cc_op < CC_OP_NB)
[...]
+ else
[...]
WARNING: line over 80 characters
#478: FILE: target/i386/cpu-dump.c:462:
+ snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
ERROR: space required before the open parenthesis '('
#498: FILE: target/i386/cpu-dump.c:482:
+ for(i = 0; i < 8; i++) {
ERROR: spaces required around that '=' (ctx:VxV)
#508: FILE: target/i386/cpu-dump.c:492:
+ for(i=0;i<8;i++) {
^
ERROR: space required after that ';' (ctx:VxV)
#508: FILE: target/i386/cpu-dump.c:492:
+ for(i=0;i<8;i++) {
^
ERROR: spaces required around that '<' (ctx:VxV)
#508: FILE: target/i386/cpu-dump.c:492:
+ for(i=0;i<8;i++) {
^
ERROR: space required after that ';' (ctx:VxV)
#508: FILE: target/i386/cpu-dump.c:492:
+ for(i=0;i<8;i++) {
^
ERROR: space required before the open parenthesis '('
#508: FILE: target/i386/cpu-dump.c:492:
+ for(i=0;i<8;i++) {
ERROR: braces {} are necessary for all arms of this statement
#513: FILE: target/i386/cpu-dump.c:497:
+ if ((i & 1) == 1)
[...]
+ else
[...]
ERROR: braces {} are necessary for all arms of this statement
#518: FILE: target/i386/cpu-dump.c:502:
+ if (env->hflags & HF_CS64_MASK)
[...]
+ else
[...]
ERROR: spaces required around that '=' (ctx:VxV)
#522: FILE: target/i386/cpu-dump.c:506:
+ for(i=0;i<nb;i++) {
^
ERROR: space required after that ';' (ctx:VxV)
#522: FILE: target/i386/cpu-dump.c:506:
+ for(i=0;i<nb;i++) {
^
ERROR: spaces required around that '<' (ctx:VxV)
#522: FILE: target/i386/cpu-dump.c:506:
+ for(i=0;i<nb;i++) {
^
ERROR: space required after that ';' (ctx:VxV)
#522: FILE: target/i386/cpu-dump.c:506:
+ for(i=0;i<nb;i++) {
^
ERROR: space required before the open parenthesis '('
#522: FILE: target/i386/cpu-dump.c:506:
+ for(i=0;i<nb;i++) {
ERROR: braces {} are necessary for all arms of this statement
#529: FILE: target/i386/cpu-dump.c:513:
+ if ((i & 1) == 1)
[...]
+ else
[...]
total: 25 errors, 5 warnings, 1077 lines checked
Patch 9/25 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/25 Checking commit d7314cab76a0 (i386: move TCG cpu class initialization out of helper.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#412:
new file mode 100644
total: 0 errors, 1 warnings, 608 lines checked
Patch 10/25 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/25 Checking commit b26f65d8444f (tcg: cpu_exec_{enter,exit} helpers)
12/25 Checking commit e33124412d9d (tcg: make CPUClass.cpu_exec_* optional)
13/25 Checking commit 07018b947480 (tcg: Make CPUClass.debug_excp_handler optional)
14/25 Checking commit bd1deaa726fc (cpu: Remove unnecessary noop methods)
15/25 Checking commit c27973682908 (cpu: Introduce TCGCpuOperations struct)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#93:
new file mode 100644
total: 0 errors, 1 warnings, 301 lines checked
Patch 15/25 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
16/25 Checking commit de4c29651b51 (target/riscv: remove CONFIG_TCG, as it is always TCG)
17/25 Checking commit ecfd44dde593 (accel/tcg: split TCG-only code from cpu_exec_realizefn)
18/25 Checking commit cb8317496f91 (cpu: Move synchronize_from_tb() to tcg_ops)
19/25 Checking commit 79fab444bec5 (cpu: Move cpu_exec_* to tcg_ops)
20/25 Checking commit 7bb4177e62f9 (cpu: Move tlb_fill to tcg_ops)
WARNING: line over 80 characters
#23: FILE: accel/tcg/cputlb.c:1289:
+ ok = cc->tcg_ops.tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
total: 0 errors, 1 warnings, 259 lines checked
Patch 20/25 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
21/25 Checking commit 32ccc60a6d38 (cpu: Move debug_excp_handler to tcg_ops)
22/25 Checking commit d72487ea4fa7 (target/arm: do not use cc->do_interrupt for KVM directly)
23/25 Checking commit f569b716427c (cpu: move cc->do_interrupt to tcg_ops)
24/25 Checking commit 0aecd322182a (cpu: move cc->transaction_failed to tcg_ops)
WARNING: line over 80 characters
#87: FILE: include/hw/core/cpu.h:857:
+ cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size, access_type,
total: 0 errors, 1 warnings, 195 lines checked
Patch 24/25 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
25/25 Checking commit a3c83d9f6296 (cpu: move do_unaligned_access to tcg_ops)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20201211083143.14350-1-cfontana@suse.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 24/25] cpu: move cc->transaction_failed to tcg_ops
2020-12-11 8:31 ` [PATCH v11 24/25] cpu: move cc->transaction_failed " Claudio Fontana
@ 2020-12-11 11:00 ` Philippe Mathieu-Daudé
2020-12-11 17:50 ` Richard Henderson
1 sibling, 0 replies; 69+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-11 11:00 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 9:31 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/hw/core/cpu.h | 18 +++++++-----------
> include/hw/core/tcg-cpu-ops.h | 14 ++++++++++++++
> hw/mips/jazz.c | 9 +++++++--
> target/alpha/cpu.c | 2 +-
> target/arm/cpu.c | 4 ++--
> target/m68k/cpu.c | 2 +-
> target/microblaze/cpu.c | 2 +-
> target/mips/cpu.c | 4 +++-
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu_helper.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> target/xtensa/helper.c | 4 ++--
> 13 files changed, 42 insertions(+), 25 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 25/25] cpu: move do_unaligned_access to tcg_ops
2020-12-11 8:31 ` [PATCH v11 25/25] cpu: move do_unaligned_access " Claudio Fontana
@ 2020-12-11 11:01 ` Philippe Mathieu-Daudé
2020-12-11 17:58 ` Richard Henderson
1 sibling, 0 replies; 69+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-11 11:01 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 9:31 AM, Claudio Fontana wrote:
> make it consistently SOFTMMU-only.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/hw/core/cpu.h | 17 +++--------------
> include/hw/core/tcg-cpu-ops.h | 7 +++++++
> target/alpha/cpu.c | 2 +-
> target/arm/cpu.c | 2 +-
> target/hppa/cpu.c | 4 +++-
> target/microblaze/cpu.c | 2 +-
> target/mips/cpu.c | 3 ++-
> target/nios2/cpu.c | 2 +-
> target/riscv/cpu.c | 2 +-
> target/s390x/cpu.c | 2 +-
> target/s390x/excp_helper.c | 2 +-
> target/sh4/cpu.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> target/ppc/translate_init.c.inc | 2 +-
> 15 files changed, 26 insertions(+), 27 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 14/25] cpu: Remove unnecessary noop methods
2020-12-11 8:31 ` [PATCH v11 14/25] cpu: Remove unnecessary noop methods Claudio Fontana
@ 2020-12-11 11:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 69+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-11 11:05 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 9:31 AM, Claudio Fontana wrote:
> From: Eduardo Habkost <ehabkost@redhat.com>
>
Either add:
"In the previous commits we made cpu_exec_* and
debug_excp_handler handlers optional, we can now
remove these no-op handlers."
Or squash in each commit...
Anyhow:
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/core/cpu.c | 13 -------------
> 1 file changed, 13 deletions(-)
>
> diff --git a/hw/core/cpu.c b/hw/core/cpu.c
> index 576fa1d7ba..994a12cb35 100644
> --- a/hw/core/cpu.c
> +++ b/hw/core/cpu.c
> @@ -199,15 +199,6 @@ static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
> return target_words_bigendian();
> }
>
> -static void cpu_common_noop(CPUState *cpu)
> -{
> -}
> -
> -static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req)
> -{
> - return false;
> -}
> -
> #if !defined(CONFIG_USER_ONLY)
> GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
> {
> @@ -410,11 +401,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
> k->gdb_read_register = cpu_common_gdb_read_register;
> k->gdb_write_register = cpu_common_gdb_write_register;
> k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
> - k->debug_excp_handler = cpu_common_noop;
> k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
> - k->cpu_exec_enter = cpu_common_noop;
> - k->cpu_exec_exit = cpu_common_noop;
> - k->cpu_exec_interrupt = cpu_common_exec_interrupt;
> k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
> set_bit(DEVICE_CATEGORY_CPU, dc->categories);
> dc->realize = cpu_common_realizefn;
>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 00/25] i386 cleanup PART 1
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
` (25 preceding siblings ...)
2020-12-11 8:57 ` [PATCH v11 00/25] i386 cleanup PART 1 no-reply
@ 2020-12-11 11:07 ` Philippe Mathieu-Daudé
26 siblings, 0 replies; 69+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-11 11:07 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Richard Henderson,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Jason Wang, Marcelo Tosatti, qemu-devel, Peter Xu,
Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 9:31 AM, Claudio Fontana wrote:
> Hello, this is version 11 of the cleanup.
>
> The series has been split into two separate parts,
> and this is PART 1.
One single patch misses review:
#10 "i386: move TCG cpu class initialization out of helper.c"
>
> v10 -> v11: small tweaks for !CONFIG_USER_ONLY
>
> * make transaction_failed and do_unaligned_access
> consistently !CONFIG_USER_ONLY.
>
> * hw/mips/jazz: wrap mips_jazz_do_transaction_failed in
> CONFIG_TCG && !CONFIG_USER_ONLY
>
> * arm: wrap arm_cpu_synchronize_from_tb in CONFIG_TCG
> * arm: wrap arm_v7m_exec_interrupt in CONFIG_TCG
> * mips: wrap mips_cpu_synchronize_from_tb in CONFIG_TCG
> * mips: do not make mips_cpu_do_interrupt !CONFIG_USER_ONLY
> * ppc: protect cpu_exec_enter/exit in CONFIG_TCG
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 04/25] i386: move kvm accel files into kvm/
2020-12-11 8:31 ` [PATCH v11 04/25] i386: move kvm accel files into kvm/ Claudio Fontana
@ 2020-12-11 16:08 ` Richard Henderson
0 siblings, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 16:08 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> meson.build | 1 +
> target/i386/cpu.h | 2 +-
> target/i386/{ => kvm}/hyperv-proto.h | 0
> target/i386/{ => kvm}/hyperv.h | 0
> target/i386/{ => kvm}/kvm_i386.h | 0
> target/i386/kvm/trace.h | 1 +
> hw/i386/fw_cfg.c | 2 +-
> hw/i386/intel_iommu.c | 2 +-
> hw/i386/kvm/apic.c | 2 +-
> hw/i386/kvm/clock.c | 2 +-
> hw/i386/microvm.c | 2 +-
> hw/i386/pc.c | 2 +-
> hw/i386/x86.c | 2 +-
> target/i386/cpu.c | 2 +-
> target/i386/helper.c | 2 +-
> target/i386/{ => kvm}/hyperv-stub.c | 0
> target/i386/{ => kvm}/hyperv.c | 0
> target/i386/{ => kvm}/kvm-stub.c | 0
> target/i386/{ => kvm}/kvm.c | 0
> target/i386/machine.c | 4 ++--
> MAINTAINERS | 2 +-
> target/i386/kvm/meson.build | 3 +++
> target/i386/kvm/trace-events | 7 +++++++
> target/i386/meson.build | 4 +---
> target/i386/trace-events | 6 ------
> 25 files changed, 26 insertions(+), 22 deletions(-)
> rename target/i386/{ => kvm}/hyperv-proto.h (100%)
> rename target/i386/{ => kvm}/hyperv.h (100%)
> rename target/i386/{ => kvm}/kvm_i386.h (100%)
> create mode 100644 target/i386/kvm/trace.h
> rename target/i386/{ => kvm}/hyperv-stub.c (100%)
> rename target/i386/{ => kvm}/hyperv.c (100%)
> rename target/i386/{ => kvm}/kvm-stub.c (100%)
> rename target/i386/{ => kvm}/kvm.c (100%)
> create mode 100644 target/i386/kvm/meson.build
> create mode 100644 target/i386/kvm/trace-events
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 05/25] i386: move whpx accel files into whpx/
2020-12-11 8:31 ` [PATCH v11 05/25] i386: move whpx accel files into whpx/ Claudio Fontana
@ 2020-12-11 16:09 ` Richard Henderson
2020-12-11 20:41 ` Eduardo Habkost
1 sibling, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 16:09 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/i386/{ => whpx}/whp-dispatch.h | 0
> target/i386/{ => whpx}/whpx-cpus.h | 0
> target/i386/{ => whpx}/whpx-all.c | 0
> target/i386/{ => whpx}/whpx-cpus.c | 0
> MAINTAINERS | 5 +----
> target/i386/meson.build | 5 +----
> target/i386/whpx/meson.build | 4 ++++
> 7 files changed, 6 insertions(+), 8 deletions(-)
> rename target/i386/{ => whpx}/whp-dispatch.h (100%)
> rename target/i386/{ => whpx}/whpx-cpus.h (100%)
> rename target/i386/{ => whpx}/whpx-all.c (100%)
> rename target/i386/{ => whpx}/whpx-cpus.c (100%)
> create mode 100644 target/i386/whpx/meson.build
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 06/25] i386: move hax accel files into hax/
2020-12-11 8:31 ` [PATCH v11 06/25] i386: move hax accel files into hax/ Claudio Fontana
@ 2020-12-11 16:10 ` Richard Henderson
0 siblings, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 16:10 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/i386/{ => hax}/hax-cpus.h | 0
> target/i386/{ => hax}/hax-i386.h | 6 +++---
> target/i386/{ => hax}/hax-interface.h | 0
> target/i386/{ => hax}/hax-posix.h | 0
> target/i386/{ => hax}/hax-windows.h | 0
> target/i386/{ => hax}/hax-all.c | 0
> target/i386/{ => hax}/hax-cpus.c | 0
> target/i386/{ => hax}/hax-mem.c | 0
> target/i386/{ => hax}/hax-posix.c | 0
> target/i386/{ => hax}/hax-windows.c | 0
> MAINTAINERS | 2 +-
> target/i386/hax/meson.build | 7 +++++++
> target/i386/meson.build | 8 +-------
> 13 files changed, 12 insertions(+), 11 deletions(-)
> rename target/i386/{ => hax}/hax-cpus.h (100%)
> rename target/i386/{ => hax}/hax-i386.h (95%)
> rename target/i386/{ => hax}/hax-interface.h (100%)
> rename target/i386/{ => hax}/hax-posix.h (100%)
> rename target/i386/{ => hax}/hax-windows.h (100%)
> rename target/i386/{ => hax}/hax-all.c (100%)
> rename target/i386/{ => hax}/hax-cpus.c (100%)
> rename target/i386/{ => hax}/hax-mem.c (100%)
> rename target/i386/{ => hax}/hax-posix.c (100%)
> rename target/i386/{ => hax}/hax-windows.c (100%)
> create mode 100644 target/i386/hax/meson.build
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 08/25] i386: move TCG accel files into tcg/
2020-12-11 8:31 ` [PATCH v11 08/25] i386: move TCG accel files into tcg/ Claudio Fontana
@ 2020-12-11 16:10 ` Richard Henderson
0 siblings, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 16:10 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/i386/{ => tcg}/bpt_helper.c | 0
> target/i386/{ => tcg}/cc_helper.c | 0
> target/i386/{ => tcg}/excp_helper.c | 0
> target/i386/{ => tcg}/fpu_helper.c | 0
> target/i386/{ => tcg}/int_helper.c | 0
> target/i386/{ => tcg}/mem_helper.c | 0
> target/i386/{ => tcg}/misc_helper.c | 0
> target/i386/{ => tcg}/mpx_helper.c | 0
> target/i386/{ => tcg}/seg_helper.c | 0
> target/i386/{ => tcg}/smm_helper.c | 0
> target/i386/{ => tcg}/svm_helper.c | 0
> target/i386/{ => tcg}/tcg-stub.c | 0
> target/i386/{ => tcg}/translate.c | 0
> target/i386/meson.build | 14 +-------------
> target/i386/tcg/meson.build | 13 +++++++++++++
> 15 files changed, 14 insertions(+), 13 deletions(-)
> rename target/i386/{ => tcg}/bpt_helper.c (100%)
> rename target/i386/{ => tcg}/cc_helper.c (100%)
> rename target/i386/{ => tcg}/excp_helper.c (100%)
> rename target/i386/{ => tcg}/fpu_helper.c (100%)
> rename target/i386/{ => tcg}/int_helper.c (100%)
> rename target/i386/{ => tcg}/mem_helper.c (100%)
> rename target/i386/{ => tcg}/misc_helper.c (100%)
> rename target/i386/{ => tcg}/mpx_helper.c (100%)
> rename target/i386/{ => tcg}/seg_helper.c (100%)
> rename target/i386/{ => tcg}/smm_helper.c (100%)
> rename target/i386/{ => tcg}/svm_helper.c (100%)
> rename target/i386/{ => tcg}/tcg-stub.c (100%)
> rename target/i386/{ => tcg}/translate.c (100%)
> create mode 100644 target/i386/tcg/meson.build
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 09/25] i386: move cpu dump out of helper.c into cpu-dump.c
2020-12-11 8:31 ` [PATCH v11 09/25] i386: move cpu dump out of helper.c into cpu-dump.c Claudio Fontana
@ 2020-12-11 16:13 ` Richard Henderson
2020-12-11 17:21 ` Claudio Fontana
0 siblings, 1 reply; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 16:13 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/i386/cpu.h | 1 +
> target/i386/cpu-dump.c | 537 ++++++++++++++++++++++++++++++++++++++++
> target/i386/helper.c | 514 --------------------------------------
> target/i386/meson.build | 1 +
> 4 files changed, 539 insertions(+), 514 deletions(-)
> create mode 100644 target/i386/cpu-dump.c
There are a fair few "static const char * array[]" that should be "static const
char * const array[]", but is an existing error and this patch is pure code
movement.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 10/25] i386: move TCG cpu class initialization out of helper.c
2020-12-11 8:31 ` [PATCH v11 10/25] i386: move TCG cpu class initialization out of helper.c Claudio Fontana
@ 2020-12-11 16:44 ` Richard Henderson
2020-12-11 17:31 ` Claudio Fontana
0 siblings, 1 reply; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 16:44 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Jason Wang, Marcelo Tosatti, qemu-devel, Peter Xu,
Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> ---
> target/i386/cpu.h | 97 ++---------------------------
> target/i386/tcg/helper-tcg.h | 112 ++++++++++++++++++++++++++++++++++
> target/i386/tcg/tcg-cpu.h | 15 +++++
> target/i386/cpu.c | 33 ++++------
> target/i386/helper.c | 23 -------
> target/i386/tcg/bpt_helper.c | 1 +
> target/i386/tcg/cc_helper.c | 1 +
> target/i386/tcg/excp_helper.c | 1 +
> target/i386/tcg/fpu_helper.c | 33 +++++-----
> target/i386/tcg/int_helper.c | 1 +
> target/i386/tcg/mem_helper.c | 1 +
> target/i386/tcg/misc_helper.c | 1 +
> target/i386/tcg/mpx_helper.c | 1 +
> target/i386/tcg/seg_helper.c | 1 +
> target/i386/tcg/smm_helper.c | 2 +
> target/i386/tcg/svm_helper.c | 1 +
> target/i386/tcg/tcg-cpu.c | 71 +++++++++++++++++++++
> target/i386/tcg/translate.c | 1 +
> target/i386/tcg/meson.build | 1 +
> 19 files changed, 244 insertions(+), 153 deletions(-)
> create mode 100644 target/i386/tcg/helper-tcg.h
> create mode 100644 target/i386/tcg/tcg-cpu.h
> create mode 100644 target/i386/tcg/tcg-cpu.c
This is doing a lot more than $SUBJECT, which afaict would just be the creation
of target/i386/tcg/tcg-cpu.c.
> +#define CC_DST (env->cc_dst)
> +#define CC_SRC (env->cc_src)
> +#define CC_SRC2 (env->cc_src2)
> +#define CC_OP (env->cc_op)
Why are these moving within cpu.h? If they move at all, they should be moved
out of here. Better if they're simply removed -- this is a silly wrapping of
"env->foo" from ancient days.
> +/* float macros */
> +#define FT0 (env->ft0)
> +#define ST0 (env->fpregs[env->fpstt].d)
> +#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
> +#define ST1 ST(1)
Any chance these can move to fpu_helper.c? Or, in the case of FT0, be eliminated?
> +/* cc_helper.c */
> +extern const uint8_t parity_table[256];
We should probably remove this and just use ctpop(x) & 1.
> +/*
> + * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
> + * after generating a call to a helper that uses this.
> + */
> +static inline void cpu_load_eflags(CPUX86State *env, int eflags,
> + int update_mask)
> +{
> + CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
> + CC_OP = CC_OP_EFLAGS;
> + env->df = 1 - (2 * ((eflags >> 10) & 1));
> + env->eflags = (env->eflags & ~update_mask) |
> + (eflags & update_mask) | 0x2;
> +}
This is complex enough I would be in favor of moving it out-of-line somewhere
convenient.
> +++ b/target/i386/tcg/tcg-cpu.h
> @@ -0,0 +1,15 @@
> +/*
> + * i386 TCG CPU class initialization
> + *
> + * Copyright 2020 SUSE LLC
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef TCG_CPU_H
> +#define TCG_CPU_H
> +
> +void tcg_cpu_common_class_init(CPUClass *cc);
> +
Why does the new file need it's own header, with one declaration?
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 11/25] tcg: cpu_exec_{enter,exit} helpers
2020-12-11 8:31 ` [PATCH v11 11/25] tcg: cpu_exec_{enter,exit} helpers Claudio Fontana
@ 2020-12-11 16:45 ` Richard Henderson
0 siblings, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 16:45 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> From: Eduardo Habkost <ehabkost@redhat.com>
>
> Move invocation of CPUClass.cpu_exec_*() to separate helpers,
> to make it easier to refactor that code later.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> accel/tcg/cpu-exec.c | 23 ++++++++++++++++++-----
> 1 file changed, 18 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 15/25] cpu: Introduce TCGCpuOperations struct
2020-12-11 8:31 ` [PATCH v11 15/25] cpu: Introduce TCGCpuOperations struct Claudio Fontana
@ 2020-12-11 16:55 ` Richard Henderson
2020-12-11 16:57 ` Richard Henderson
0 siblings, 1 reply; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 16:55 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> --- a/cpu.c
> +++ b/cpu.c
> @@ -174,14 +174,18 @@ void cpu_exec_initfn(CPUState *cpu)
> void cpu_exec_realizefn(CPUState *cpu, Error **errp)
> {
> CPUClass *cc = CPU_GET_CLASS(cpu);
> +#ifdef CONFIG_TCG
> static bool tcg_target_initialized;
> +#endif /* CONFIG_TCG */
>
> cpu_list_add(cpu);
>
> +#ifdef CONFIG_TCG
> if (tcg_enabled() && !tcg_target_initialized) {
> tcg_target_initialized = true;
> - cc->tcg_initialize();
> + cc->tcg_ops.initialize();
> }
> +#endif /* CONFIG_TCG */
Not a big fan of the extra ifdefs. Are we expecting that there won't be any
more of these, that other references to cc->tcg_ops will be completely within
accel/tcg/?
We can at least combine these two,
#ifdef CONFIG_TCG
if (tcg_enabled()) {
static bool tcg_target_initialized;
if (!tcg_target_initialized) {
tcg_target_initialized = true;
cc->tcg_ops.initialize();
}
}
#endif
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 16/25] target/riscv: remove CONFIG_TCG, as it is always TCG
2020-12-11 8:31 ` [PATCH v11 16/25] target/riscv: remove CONFIG_TCG, as it is always TCG Claudio Fontana
@ 2020-12-11 16:56 ` Richard Henderson
2020-12-11 17:19 ` Claudio Fontana
0 siblings, 1 reply; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 16:56 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Jason Wang, Marcelo Tosatti, qemu-devel, Peter Xu,
Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Alistair Francis, Bruce Rogers, Olaf Hering,
Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> for now only TCG is allowed as an accelerator for riscv,
> so remove the CONFIG_TCG use.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
Aren't there patches on the list to add kvm support for riscv?
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 15/25] cpu: Introduce TCGCpuOperations struct
2020-12-11 16:55 ` Richard Henderson
@ 2020-12-11 16:57 ` Richard Henderson
0 siblings, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 16:57 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 10:55 AM, Richard Henderson wrote:
> On 12/11/20 2:31 AM, Claudio Fontana wrote:
>> --- a/cpu.c
>> +++ b/cpu.c
>> @@ -174,14 +174,18 @@ void cpu_exec_initfn(CPUState *cpu)
>> void cpu_exec_realizefn(CPUState *cpu, Error **errp)
>> {
>> CPUClass *cc = CPU_GET_CLASS(cpu);
>> +#ifdef CONFIG_TCG
>> static bool tcg_target_initialized;
>> +#endif /* CONFIG_TCG */
>>
>> cpu_list_add(cpu);
>>
>> +#ifdef CONFIG_TCG
>> if (tcg_enabled() && !tcg_target_initialized) {
>> tcg_target_initialized = true;
>> - cc->tcg_initialize();
>> + cc->tcg_ops.initialize();
>> }
>> +#endif /* CONFIG_TCG */
>
> Not a big fan of the extra ifdefs. Are we expecting that there won't be any
> more of these, that other references to cc->tcg_ops will be completely within
> accel/tcg/?
>
> We can at least combine these two,
>
> #ifdef CONFIG_TCG
> if (tcg_enabled()) {
> static bool tcg_target_initialized;
> if (!tcg_target_initialized) {
> tcg_target_initialized = true;
> cc->tcg_ops.initialize();
> }
> }
> #endif
Nevermind, I now see this is cleaned up further in patch 17.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 17/25] accel/tcg: split TCG-only code from cpu_exec_realizefn
2020-12-11 8:31 ` [PATCH v11 17/25] accel/tcg: split TCG-only code from cpu_exec_realizefn Claudio Fontana
@ 2020-12-11 16:58 ` Richard Henderson
0 siblings, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 16:58 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> move away TCG-only code, make it compile only on TCG.
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/hw/core/cpu.h | 8 +++++
> accel/tcg/cpu-exec.c | 28 +++++++++++++++++
> cpu.c | 70 ++++++++++++++++++++-----------------------
> hw/core/cpu.c | 6 +++-
> 4 files changed, 74 insertions(+), 38 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 8:31 ` [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops Claudio Fontana
@ 2020-12-11 17:05 ` Richard Henderson
2020-12-11 17:10 ` Claudio Fontana
0 siblings, 1 reply; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 17:05 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> From: Eduardo Habkost <ehabkost@redhat.com>
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> [claudio: wrapped in CONFIG_TCG]
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/hw/core/cpu.h | 8 --------
> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++
> accel/tcg/cpu-exec.c | 4 ++--
> target/arm/cpu.c | 4 +++-
> target/avr/cpu.c | 2 +-
> target/hppa/cpu.c | 2 +-
> target/i386/tcg/tcg-cpu.c | 2 +-
> target/microblaze/cpu.c | 2 +-
> target/mips/cpu.c | 4 +++-
> target/riscv/cpu.c | 2 +-
> target/rx/cpu.c | 2 +-
> target/sh4/cpu.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/tricore/cpu.c | 2 +-
> 14 files changed, 29 insertions(+), 21 deletions(-)
>
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index ea648d52ad..83007d262c 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -110,13 +110,6 @@ struct TranslationBlock;
> * If the target behaviour here is anything other than "set
> * the PC register to the value passed in" then the target must
> * also implement the synchronize_from_tb hook.
> - * @synchronize_from_tb: Callback for synchronizing state from a TCG
> - * #TranslationBlock. This is called when we abandon execution
> - * of a TB before starting it, and must set all parts of the CPU
> - * state which the previous TB in the chain may not have updated.
> - * This always includes at least the program counter; some targets
> - * will need to do more. If this hook is not implemented then the
> - * default is to call @set_pc(tb->pc).
> * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
> * address fault. For system mode, if the access is valid, call
> * tlb_set_page and return true; if the access is invalid, and
> @@ -193,7 +186,6 @@ struct CPUClass {
> void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
> Error **errp);
> void (*set_pc)(CPUState *cpu, vaddr value);
> - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
> bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
> MMUAccessType access_type, int mmu_idx,
> bool probe, uintptr_t retaddr);
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index 4475ef0996..e1d50b3c8b 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -10,6 +10,8 @@
> #ifndef TCG_CPU_OPS_H
> #define TCG_CPU_OPS_H
>
> +#include "hw/core/cpu.h"
This include is circular.
Are you sure that splitting out hw/core/tcg-cpu-ops.h from hw/core/cpu.h in
patch 15 is even useful?
Otherwise the actual code change looks ok.
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 17:05 ` Richard Henderson
@ 2020-12-11 17:10 ` Claudio Fontana
2020-12-11 17:11 ` Claudio Fontana
2020-12-11 17:28 ` Richard Henderson
0 siblings, 2 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 17:10 UTC (permalink / raw)
To: Richard Henderson, Paolo Bonzini, Thomas Huth,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 6:05 PM, Richard Henderson wrote:
> On 12/11/20 2:31 AM, Claudio Fontana wrote:
>> From: Eduardo Habkost <ehabkost@redhat.com>
>>
>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
>> [claudio: wrapped in CONFIG_TCG]
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>> include/hw/core/cpu.h | 8 --------
>> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++
>> accel/tcg/cpu-exec.c | 4 ++--
>> target/arm/cpu.c | 4 +++-
>> target/avr/cpu.c | 2 +-
>> target/hppa/cpu.c | 2 +-
>> target/i386/tcg/tcg-cpu.c | 2 +-
>> target/microblaze/cpu.c | 2 +-
>> target/mips/cpu.c | 4 +++-
>> target/riscv/cpu.c | 2 +-
>> target/rx/cpu.c | 2 +-
>> target/sh4/cpu.c | 2 +-
>> target/sparc/cpu.c | 2 +-
>> target/tricore/cpu.c | 2 +-
>> 14 files changed, 29 insertions(+), 21 deletions(-)
>>
>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
>> index ea648d52ad..83007d262c 100644
>> --- a/include/hw/core/cpu.h
>> +++ b/include/hw/core/cpu.h
>> @@ -110,13 +110,6 @@ struct TranslationBlock;
>> * If the target behaviour here is anything other than "set
>> * the PC register to the value passed in" then the target must
>> * also implement the synchronize_from_tb hook.
>> - * @synchronize_from_tb: Callback for synchronizing state from a TCG
>> - * #TranslationBlock. This is called when we abandon execution
>> - * of a TB before starting it, and must set all parts of the CPU
>> - * state which the previous TB in the chain may not have updated.
>> - * This always includes at least the program counter; some targets
>> - * will need to do more. If this hook is not implemented then the
>> - * default is to call @set_pc(tb->pc).
>> * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
>> * address fault. For system mode, if the access is valid, call
>> * tlb_set_page and return true; if the access is invalid, and
>> @@ -193,7 +186,6 @@ struct CPUClass {
>> void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
>> Error **errp);
>> void (*set_pc)(CPUState *cpu, vaddr value);
>> - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
>> bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
>> MMUAccessType access_type, int mmu_idx,
>> bool probe, uintptr_t retaddr);
>> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
>> index 4475ef0996..e1d50b3c8b 100644
>> --- a/include/hw/core/tcg-cpu-ops.h
>> +++ b/include/hw/core/tcg-cpu-ops.h
>> @@ -10,6 +10,8 @@
>> #ifndef TCG_CPU_OPS_H
>> #define TCG_CPU_OPS_H
>>
>> +#include "hw/core/cpu.h"
>
> This include is circular.
Yes, it's protected though, it was asked that way.
>
> Are you sure that splitting out hw/core/tcg-cpu-ops.h from hw/core/cpu.h in
> patch 15 is even useful?
it avoids a huge #ifdef CONFIG_TCG
>
> Otherwise the actual code change looks ok.
>
>
> r~
>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 17:10 ` Claudio Fontana
@ 2020-12-11 17:11 ` Claudio Fontana
2020-12-11 17:28 ` Richard Henderson
1 sibling, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 17:11 UTC (permalink / raw)
To: Richard Henderson, Paolo Bonzini, Thomas Huth,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 6:10 PM, Claudio Fontana wrote:
> On 12/11/20 6:05 PM, Richard Henderson wrote:
>> On 12/11/20 2:31 AM, Claudio Fontana wrote:
>>> From: Eduardo Habkost <ehabkost@redhat.com>
>>>
>>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
>>> [claudio: wrapped in CONFIG_TCG]
>>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>>> ---
>>> include/hw/core/cpu.h | 8 --------
>>> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++
>>> accel/tcg/cpu-exec.c | 4 ++--
>>> target/arm/cpu.c | 4 +++-
>>> target/avr/cpu.c | 2 +-
>>> target/hppa/cpu.c | 2 +-
>>> target/i386/tcg/tcg-cpu.c | 2 +-
>>> target/microblaze/cpu.c | 2 +-
>>> target/mips/cpu.c | 4 +++-
>>> target/riscv/cpu.c | 2 +-
>>> target/rx/cpu.c | 2 +-
>>> target/sh4/cpu.c | 2 +-
>>> target/sparc/cpu.c | 2 +-
>>> target/tricore/cpu.c | 2 +-
>>> 14 files changed, 29 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
>>> index ea648d52ad..83007d262c 100644
>>> --- a/include/hw/core/cpu.h
>>> +++ b/include/hw/core/cpu.h
>>> @@ -110,13 +110,6 @@ struct TranslationBlock;
>>> * If the target behaviour here is anything other than "set
>>> * the PC register to the value passed in" then the target must
>>> * also implement the synchronize_from_tb hook.
>>> - * @synchronize_from_tb: Callback for synchronizing state from a TCG
>>> - * #TranslationBlock. This is called when we abandon execution
>>> - * of a TB before starting it, and must set all parts of the CPU
>>> - * state which the previous TB in the chain may not have updated.
>>> - * This always includes at least the program counter; some targets
>>> - * will need to do more. If this hook is not implemented then the
>>> - * default is to call @set_pc(tb->pc).
>>> * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
>>> * address fault. For system mode, if the access is valid, call
>>> * tlb_set_page and return true; if the access is invalid, and
>>> @@ -193,7 +186,6 @@ struct CPUClass {
>>> void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
>>> Error **errp);
>>> void (*set_pc)(CPUState *cpu, vaddr value);
>>> - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
>>> bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
>>> MMUAccessType access_type, int mmu_idx,
>>> bool probe, uintptr_t retaddr);
>>> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
>>> index 4475ef0996..e1d50b3c8b 100644
>>> --- a/include/hw/core/tcg-cpu-ops.h
>>> +++ b/include/hw/core/tcg-cpu-ops.h
>>> @@ -10,6 +10,8 @@
>>> #ifndef TCG_CPU_OPS_H
>>> #define TCG_CPU_OPS_H
>>>
>>> +#include "hw/core/cpu.h"
>>
>> This include is circular.
>
> Yes, it's protected though, it was asked that way.
I mean, during the review. I personally would have preferred to avoid these as only cpu.h is including this for now.
>
>>
>> Are you sure that splitting out hw/core/tcg-cpu-ops.h from hw/core/cpu.h in
>> patch 15 is even useful?
>
> it avoids a huge #ifdef CONFIG_TCG
>
>
>>
>> Otherwise the actual code change looks ok.
>>
>>
>> r~
>>
>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 16/25] target/riscv: remove CONFIG_TCG, as it is always TCG
2020-12-11 16:56 ` Richard Henderson
@ 2020-12-11 17:19 ` Claudio Fontana
0 siblings, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 17:19 UTC (permalink / raw)
To: Richard Henderson, Paolo Bonzini, Thomas Huth,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Jason Wang, Marcelo Tosatti, qemu-devel, Peter Xu,
Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Alistair Francis, Bruce Rogers, Olaf Hering,
Emilio G . Cota
On 12/11/20 5:56 PM, Richard Henderson wrote:
> On 12/11/20 2:31 AM, Claudio Fontana wrote:
>> for now only TCG is allowed as an accelerator for riscv,
>> so remove the CONFIG_TCG use.
>>
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>> target/riscv/cpu.c | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> Aren't there patches on the list to add kvm support for riscv?
>
>
> r~
>
Yes I saw something ongoing,
however for the current code, the CONFIG_TCG is not meaningful,
and I think the actual right wrapping of what should and should not be CONFIG_TCG, and the eventual cleanup of that using the build system is going to need more that the CONFIG_TCG that is in there.
Ciao,
Claudio
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 09/25] i386: move cpu dump out of helper.c into cpu-dump.c
2020-12-11 16:13 ` Richard Henderson
@ 2020-12-11 17:21 ` Claudio Fontana
0 siblings, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 17:21 UTC (permalink / raw)
To: Richard Henderson, Paolo Bonzini, Thomas Huth,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 5:13 PM, Richard Henderson wrote:
> On 12/11/20 2:31 AM, Claudio Fontana wrote:
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>> target/i386/cpu.h | 1 +
>> target/i386/cpu-dump.c | 537 ++++++++++++++++++++++++++++++++++++++++
>> target/i386/helper.c | 514 --------------------------------------
>> target/i386/meson.build | 1 +
>> 4 files changed, 539 insertions(+), 514 deletions(-)
>> create mode 100644 target/i386/cpu-dump.c
>
> There are a fair few "static const char * array[]" that should be "static const
> char * const array[]", but is an existing error and this patch is pure code
> movement.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> r~
>
Yes, that code being moved is full of issues, checkpatch goes mad about it.
Probably worth an extra cleanup patch later on.
Claudio
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 17:10 ` Claudio Fontana
2020-12-11 17:11 ` Claudio Fontana
@ 2020-12-11 17:28 ` Richard Henderson
2020-12-11 17:47 ` Claudio Fontana
1 sibling, 1 reply; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 17:28 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 11:10 AM, Claudio Fontana wrote:
> On 12/11/20 6:05 PM, Richard Henderson wrote:
>> On 12/11/20 2:31 AM, Claudio Fontana wrote:
>>> From: Eduardo Habkost <ehabkost@redhat.com>
>>>
>>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
>>> [claudio: wrapped in CONFIG_TCG]
>>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>>> ---
>>> include/hw/core/cpu.h | 8 --------
>>> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++
>>> accel/tcg/cpu-exec.c | 4 ++--
>>> target/arm/cpu.c | 4 +++-
>>> target/avr/cpu.c | 2 +-
>>> target/hppa/cpu.c | 2 +-
>>> target/i386/tcg/tcg-cpu.c | 2 +-
>>> target/microblaze/cpu.c | 2 +-
>>> target/mips/cpu.c | 4 +++-
>>> target/riscv/cpu.c | 2 +-
>>> target/rx/cpu.c | 2 +-
>>> target/sh4/cpu.c | 2 +-
>>> target/sparc/cpu.c | 2 +-
>>> target/tricore/cpu.c | 2 +-
>>> 14 files changed, 29 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
>>> index ea648d52ad..83007d262c 100644
>>> --- a/include/hw/core/cpu.h
>>> +++ b/include/hw/core/cpu.h
>>> @@ -110,13 +110,6 @@ struct TranslationBlock;
>>> * If the target behaviour here is anything other than "set
>>> * the PC register to the value passed in" then the target must
>>> * also implement the synchronize_from_tb hook.
>>> - * @synchronize_from_tb: Callback for synchronizing state from a TCG
>>> - * #TranslationBlock. This is called when we abandon execution
>>> - * of a TB before starting it, and must set all parts of the CPU
>>> - * state which the previous TB in the chain may not have updated.
>>> - * This always includes at least the program counter; some targets
>>> - * will need to do more. If this hook is not implemented then the
>>> - * default is to call @set_pc(tb->pc).
>>> * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
>>> * address fault. For system mode, if the access is valid, call
>>> * tlb_set_page and return true; if the access is invalid, and
>>> @@ -193,7 +186,6 @@ struct CPUClass {
>>> void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
>>> Error **errp);
>>> void (*set_pc)(CPUState *cpu, vaddr value);
>>> - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
>>> bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
>>> MMUAccessType access_type, int mmu_idx,
>>> bool probe, uintptr_t retaddr);
>>> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
>>> index 4475ef0996..e1d50b3c8b 100644
>>> --- a/include/hw/core/tcg-cpu-ops.h
>>> +++ b/include/hw/core/tcg-cpu-ops.h
>>> @@ -10,6 +10,8 @@
>>> #ifndef TCG_CPU_OPS_H
>>> #define TCG_CPU_OPS_H
>>>
>>> +#include "hw/core/cpu.h"
>>
>> This include is circular.
>
> Yes, it's protected though, it was asked that way.
Well, in my strong opinion, someone asked incorrectly. It's "harmless" because
of the protection ifdefs, but it's Wrong because it has the potential to hide bugs.
What is it that you thought you needed from core/cpu.h anyway?
>> Are you sure that splitting out hw/core/tcg-cpu-ops.h from hw/core/cpu.h in
>> patch 15 is even useful?
>
> it avoids a huge #ifdef CONFIG_TCG
So? The question should be: is it useful on its own, and I think the answer to
that is clearly not. Thus it should not pretend to be a standalone header file.
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 19/25] cpu: Move cpu_exec_* to tcg_ops
2020-12-11 8:31 ` [PATCH v11 19/25] cpu: Move cpu_exec_* " Claudio Fontana
@ 2020-12-11 17:30 ` Richard Henderson
0 siblings, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 17:30 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> From: Eduardo Habkost <ehabkost@redhat.com>
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> [claudio: wrapped in CONFIG_TCG]
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/hw/core/cpu.h | 6 ------
> include/hw/core/tcg-cpu-ops.h | 6 ++++++
> accel/tcg/cpu-exec.c | 12 ++++++------
> target/alpha/cpu.c | 2 +-
> target/arm/cpu.c | 2 +-
> target/arm/cpu64.c | 5 ++++-
> target/arm/cpu_tcg.c | 7 ++++++-
> target/avr/cpu.c | 2 +-
> target/cris/cpu.c | 2 +-
> target/hppa/cpu.c | 2 +-
> target/i386/tcg/tcg-cpu.c | 6 +++---
> target/lm32/cpu.c | 2 +-
> target/m68k/cpu.c | 2 +-
> target/microblaze/cpu.c | 2 +-
> target/mips/cpu.c | 2 +-
> target/nios2/cpu.c | 2 +-
> target/openrisc/cpu.c | 2 +-
> target/riscv/cpu.c | 2 +-
> target/rx/cpu.c | 2 +-
> target/s390x/cpu.c | 2 +-
> target/sh4/cpu.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/tilegx/cpu.c | 2 +-
> target/unicore32/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> target/ppc/translate_init.c.inc | 16 ++++++++++------
> 26 files changed, 54 insertions(+), 42 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 10/25] i386: move TCG cpu class initialization out of helper.c
2020-12-11 16:44 ` Richard Henderson
@ 2020-12-11 17:31 ` Claudio Fontana
0 siblings, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 17:31 UTC (permalink / raw)
To: Richard Henderson, Paolo Bonzini, Thomas Huth,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Jason Wang, Marcelo Tosatti, qemu-devel, Peter Xu,
Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 5:44 PM, Richard Henderson wrote:
> On 12/11/20 2:31 AM, Claudio Fontana wrote:
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> ---
>> target/i386/cpu.h | 97 ++---------------------------
>> target/i386/tcg/helper-tcg.h | 112 ++++++++++++++++++++++++++++++++++
>> target/i386/tcg/tcg-cpu.h | 15 +++++
>> target/i386/cpu.c | 33 ++++------
>> target/i386/helper.c | 23 -------
>> target/i386/tcg/bpt_helper.c | 1 +
>> target/i386/tcg/cc_helper.c | 1 +
>> target/i386/tcg/excp_helper.c | 1 +
>> target/i386/tcg/fpu_helper.c | 33 +++++-----
>> target/i386/tcg/int_helper.c | 1 +
>> target/i386/tcg/mem_helper.c | 1 +
>> target/i386/tcg/misc_helper.c | 1 +
>> target/i386/tcg/mpx_helper.c | 1 +
>> target/i386/tcg/seg_helper.c | 1 +
>> target/i386/tcg/smm_helper.c | 2 +
>> target/i386/tcg/svm_helper.c | 1 +
>> target/i386/tcg/tcg-cpu.c | 71 +++++++++++++++++++++
>> target/i386/tcg/translate.c | 1 +
>> target/i386/tcg/meson.build | 1 +
>> 19 files changed, 244 insertions(+), 153 deletions(-)
>> create mode 100644 target/i386/tcg/helper-tcg.h
>> create mode 100644 target/i386/tcg/tcg-cpu.h
>> create mode 100644 target/i386/tcg/tcg-cpu.c
>
> This is doing a lot more than $SUBJECT, which afaict would just be the creation
> of target/i386/tcg/tcg-cpu.c.
>
>> +#define CC_DST (env->cc_dst)
>> +#define CC_SRC (env->cc_src)
>> +#define CC_SRC2 (env->cc_src2)
>> +#define CC_OP (env->cc_op)
>
> Why are these moving within cpu.h? If they move at all, they should be moved
> out of here. Better if they're simply removed -- this is a silly wrapping of
> "env->foo" from ancient days.
>
>> +/* float macros */
>> +#define FT0 (env->ft0)
>> +#define ST0 (env->fpregs[env->fpstt].d)
>> +#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
>> +#define ST1 ST(1)
>
> Any chance these can move to fpu_helper.c? Or, in the case of FT0, be eliminated?
>
>> +/* cc_helper.c */
>> +extern const uint8_t parity_table[256];
>
> We should probably remove this and just use ctpop(x) & 1.
>
>> +/*
>> + * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
>> + * after generating a call to a helper that uses this.
>> + */
>> +static inline void cpu_load_eflags(CPUX86State *env, int eflags,
>> + int update_mask)
>> +{
>> + CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
>> + CC_OP = CC_OP_EFLAGS;
>> + env->df = 1 - (2 * ((eflags >> 10) & 1));
>> + env->eflags = (env->eflags & ~update_mask) |
>> + (eflags & update_mask) | 0x2;
>> +}
>
> This is complex enough I would be in favor of moving it out-of-line somewhere
> convenient.
>
About the above, will work on this for the next spin.
>> +++ b/target/i386/tcg/tcg-cpu.h
>> @@ -0,0 +1,15 @@
>> +/*
>> + * i386 TCG CPU class initialization
>> + *
>> + * Copyright 2020 SUSE LLC
>> + *
>> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
>> + * See the COPYING file in the top-level directory.
>> + */
>> +
>> +#ifndef TCG_CPU_H
>> +#define TCG_CPU_H
>> +
>> +void tcg_cpu_common_class_init(CPUClass *cc);
>> +
>
> Why does the new file need it's own header, with one declaration?
will be removed later when we have the actual classes, so this won't be needed anymore.
But until then, the tcg-cpu.c module exports one function to target/i386/cpu.c, where the tcg-specific class initialization is called.
Thanks!
Claudio
>
>
> r~
>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 20/25] cpu: Move tlb_fill to tcg_ops
2020-12-11 8:31 ` [PATCH v11 20/25] cpu: Move tlb_fill " Claudio Fontana
@ 2020-12-11 17:42 ` Richard Henderson
0 siblings, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 17:42 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> From: Eduardo Habkost <ehabkost@redhat.com>
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> [claudio: wrapped in CONFIG_TCG]
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/hw/core/cpu.h | 9 ---------
> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++
> accel/tcg/cputlb.c | 6 +++---
> accel/tcg/user-exec.c | 6 +++---
> target/alpha/cpu.c | 2 +-
> target/arm/cpu.c | 2 +-
> target/avr/cpu.c | 2 +-
> target/cris/cpu.c | 2 +-
> target/hppa/cpu.c | 2 +-
> target/i386/tcg/tcg-cpu.c | 2 +-
> target/lm32/cpu.c | 2 +-
> target/m68k/cpu.c | 2 +-
> target/microblaze/cpu.c | 2 +-
> target/mips/cpu.c | 2 +-
> target/moxie/cpu.c | 2 +-
> target/nios2/cpu.c | 2 +-
> target/openrisc/cpu.c | 2 +-
> target/riscv/cpu.c | 2 +-
> target/rx/cpu.c | 2 +-
> target/s390x/cpu.c | 2 +-
> target/sh4/cpu.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/tilegx/cpu.c | 2 +-
> target/tricore/cpu.c | 2 +-
> target/unicore32/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> target/ppc/translate_init.c.inc | 2 +-
> 27 files changed, 41 insertions(+), 38 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 21/25] cpu: Move debug_excp_handler to tcg_ops
2020-12-11 8:31 ` [PATCH v11 21/25] cpu: Move debug_excp_handler " Claudio Fontana
@ 2020-12-11 17:44 ` Richard Henderson
0 siblings, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 17:44 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> From: Eduardo Habkost <ehabkost@redhat.com>
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/hw/core/cpu.h | 2 --
> include/hw/core/tcg-cpu-ops.h | 2 ++
> accel/tcg/cpu-exec.c | 4 ++--
> target/arm/cpu.c | 2 +-
> target/i386/tcg/tcg-cpu.c | 2 +-
> target/lm32/cpu.c | 2 +-
> target/s390x/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> 8 files changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 22/25] target/arm: do not use cc->do_interrupt for KVM directly
2020-12-11 8:31 ` [PATCH v11 22/25] target/arm: do not use cc->do_interrupt for KVM directly Claudio Fontana
@ 2020-12-11 17:44 ` Richard Henderson
0 siblings, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 17:44 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> cc->do_interrupt is in theory a TCG callback used in accel/tcg only,
> to prepare the emulated architecture to take an interrupt as defined
> in the hardware specifications,
>
> but in reality the _do_interrupt style of functions in targets are
> also occasionally reused by KVM to prepare the architecture state in a
> similar way where userspace code has identified that it needs to
> deliver an exception to the guest.
>
> In the case of ARM, that includes:
>
> 1) the vcpu thread got a SIGBUS indicating a memory error,
> and we need to deliver a Synchronous External Abort to the guest to
> let it know about the error.
> 2) the kernel told us about a debug exception (breakpoint, watchpoint)
> but it is not for one of QEMU's own gdbstub breakpoints/watchpoints
> so it must be a breakpoint the guest itself has set up, therefore
> we need to deliver it to the guest.
>
> So in order to reuse code, the same arm_do_interrupt function is used.
> This is all fine, but we need to avoid calling it using the callback
> registered in CPUClass, since that one is now TCG-only.
>
> Fortunately this is easily solved by replacing calls to
> CPUClass::do_interrupt() with explicit calls to arm_do_interrupt().
>
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/arm/helper.c | 4 ++++
> target/arm/kvm64.c | 6 ++----
> 2 files changed, 6 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 23/25] cpu: move cc->do_interrupt to tcg_ops
2020-12-11 8:31 ` [PATCH v11 23/25] cpu: move cc->do_interrupt to tcg_ops Claudio Fontana
@ 2020-12-11 17:46 ` Richard Henderson
0 siblings, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 17:46 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/hw/core/cpu.h | 2 --
> include/hw/core/tcg-cpu-ops.h | 3 +++
> accel/tcg/cpu-exec.c | 4 ++--
> target/alpha/cpu.c | 2 +-
> target/arm/cpu.c | 4 ++--
> target/arm/cpu_tcg.c | 9 ++++-----
> target/avr/cpu.c | 2 +-
> target/avr/helper.c | 4 ++--
> target/cris/cpu.c | 12 ++++++------
> target/cris/helper.c | 4 ++--
> target/hppa/cpu.c | 2 +-
> target/i386/tcg/tcg-cpu.c | 2 +-
> target/lm32/cpu.c | 2 +-
> target/m68k/cpu.c | 2 +-
> target/microblaze/cpu.c | 2 +-
> target/mips/cpu.c | 4 ++--
> target/moxie/cpu.c | 2 +-
> target/nios2/cpu.c | 2 +-
> target/openrisc/cpu.c | 2 +-
> target/riscv/cpu.c | 2 +-
> target/rx/cpu.c | 2 +-
> target/s390x/cpu.c | 2 +-
> target/sh4/cpu.c | 2 +-
> target/sparc/cpu.c | 2 +-
> target/tilegx/cpu.c | 2 +-
> target/unicore32/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> target/ppc/translate_init.c.inc | 2 +-
> 28 files changed, 42 insertions(+), 42 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 17:28 ` Richard Henderson
@ 2020-12-11 17:47 ` Claudio Fontana
2020-12-11 18:04 ` Richard Henderson
2020-12-11 18:15 ` Claudio Fontana
0 siblings, 2 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 17:47 UTC (permalink / raw)
To: Richard Henderson, Paolo Bonzini, Thomas Huth,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 6:28 PM, Richard Henderson wrote:
> On 12/11/20 11:10 AM, Claudio Fontana wrote:
>> On 12/11/20 6:05 PM, Richard Henderson wrote:
>>> On 12/11/20 2:31 AM, Claudio Fontana wrote:
>>>> From: Eduardo Habkost <ehabkost@redhat.com>
>>>>
>>>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
>>>> [claudio: wrapped in CONFIG_TCG]
>>>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>>>> ---
>>>> include/hw/core/cpu.h | 8 --------
>>>> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++
>>>> accel/tcg/cpu-exec.c | 4 ++--
>>>> target/arm/cpu.c | 4 +++-
>>>> target/avr/cpu.c | 2 +-
>>>> target/hppa/cpu.c | 2 +-
>>>> target/i386/tcg/tcg-cpu.c | 2 +-
>>>> target/microblaze/cpu.c | 2 +-
>>>> target/mips/cpu.c | 4 +++-
>>>> target/riscv/cpu.c | 2 +-
>>>> target/rx/cpu.c | 2 +-
>>>> target/sh4/cpu.c | 2 +-
>>>> target/sparc/cpu.c | 2 +-
>>>> target/tricore/cpu.c | 2 +-
>>>> 14 files changed, 29 insertions(+), 21 deletions(-)
>>>>
>>>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
>>>> index ea648d52ad..83007d262c 100644
>>>> --- a/include/hw/core/cpu.h
>>>> +++ b/include/hw/core/cpu.h
>>>> @@ -110,13 +110,6 @@ struct TranslationBlock;
>>>> * If the target behaviour here is anything other than "set
>>>> * the PC register to the value passed in" then the target must
>>>> * also implement the synchronize_from_tb hook.
>>>> - * @synchronize_from_tb: Callback for synchronizing state from a TCG
>>>> - * #TranslationBlock. This is called when we abandon execution
>>>> - * of a TB before starting it, and must set all parts of the CPU
>>>> - * state which the previous TB in the chain may not have updated.
>>>> - * This always includes at least the program counter; some targets
>>>> - * will need to do more. If this hook is not implemented then the
>>>> - * default is to call @set_pc(tb->pc).
>>>> * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
>>>> * address fault. For system mode, if the access is valid, call
>>>> * tlb_set_page and return true; if the access is invalid, and
>>>> @@ -193,7 +186,6 @@ struct CPUClass {
>>>> void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
>>>> Error **errp);
>>>> void (*set_pc)(CPUState *cpu, vaddr value);
>>>> - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
>>>> bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
>>>> MMUAccessType access_type, int mmu_idx,
>>>> bool probe, uintptr_t retaddr);
>>>> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
>>>> index 4475ef0996..e1d50b3c8b 100644
>>>> --- a/include/hw/core/tcg-cpu-ops.h
>>>> +++ b/include/hw/core/tcg-cpu-ops.h
>>>> @@ -10,6 +10,8 @@
>>>> #ifndef TCG_CPU_OPS_H
>>>> #define TCG_CPU_OPS_H
>>>>
>>>> +#include "hw/core/cpu.h"
>>>
>>> This include is circular.
>>
>> Yes, it's protected though, it was asked that way.
>
> Well, in my strong opinion, someone asked incorrectly. It's "harmless" because
> of the protection ifdefs, but it's Wrong because it has the potential to hide bugs.
>
> What is it that you thought you needed from core/cpu.h anyway?
>
>>> Are you sure that splitting out hw/core/tcg-cpu-ops.h from hw/core/cpu.h in
>>> patch 15 is even useful?
>>
>> it avoids a huge #ifdef CONFIG_TCG
>
> So? The question should be: is it useful on its own, and I think the answer to
> that is clearly not. Thus it should not pretend to be a standalone header file.
>
>
> r~
>
The whole point of the exercise is to sort out what is tcg specific and only compile it under CONFIG_TCG.
Having everything inside cpu.h wrapped in a 100 line #ifdef is not particularly readable or discoverable,
so I think it is actually useful for understanding purposes to have it separate,
but that said, I don't feel strongly on this, as I intend to improve this in later series.
Thanks,
Claudio
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 24/25] cpu: move cc->transaction_failed to tcg_ops
2020-12-11 8:31 ` [PATCH v11 24/25] cpu: move cc->transaction_failed " Claudio Fontana
2020-12-11 11:00 ` Philippe Mathieu-Daudé
@ 2020-12-11 17:50 ` Richard Henderson
1 sibling, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 17:50 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> @@ -848,7 +842,7 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
>
> cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
> }
> -
> +#ifdef CONFIG_TCG
> static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
Keep the whitespace between functions. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 25/25] cpu: move do_unaligned_access to tcg_ops
2020-12-11 8:31 ` [PATCH v11 25/25] cpu: move do_unaligned_access " Claudio Fontana
2020-12-11 11:01 ` Philippe Mathieu-Daudé
@ 2020-12-11 17:58 ` Richard Henderson
1 sibling, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 17:58 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 2:31 AM, Claudio Fontana wrote:
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -66,6 +66,13 @@ typedef struct TcgCpuOperations {
> unsigned size, MMUAccessType access_type,
> int mmu_idx, MemTxAttrs attrs,
> MemTxResult response, uintptr_t retaddr);
> + /**
> + * @do_unaligned_access: Callback for unaligned access handling, if
> + * the target defines #TARGET_ALIGNED_ONLY.
> + */
> + void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
> + MMUAccessType access_type,
> + int mmu_idx, uintptr_t retaddr);
The comment is out of date. TARGET_ALIGNED_ONLY is no longer relevant. That
define only controls the default for MO_ALIGN. The target can specify all
sorts of alignment apart from the default.
So let's lose everything after the "," and everything is ok.
Amusingly, I was this week considering how easy it would be to add alignment
checks to user-only. But we're a fair way off from that now, so,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 17:47 ` Claudio Fontana
@ 2020-12-11 18:04 ` Richard Henderson
2020-12-11 18:15 ` Claudio Fontana
1 sibling, 0 replies; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 18:04 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 11:47 AM, Claudio Fontana wrote:
>> What is it that you thought you needed from core/cpu.h anyway?
...
>>>> Are you sure that splitting out hw/core/tcg-cpu-ops.h from hw/core/cpu.h in
>>>> patch 15 is even useful?
>>>
>>> it avoids a huge #ifdef CONFIG_TCG
>>
>> So? The question should be: is it useful on its own, and I think the answer to
>> that is clearly not. Thus it should not pretend to be a standalone header file.
>>
>
> The whole point of the exercise is to sort out what is tcg specific and
> only compile it under CONFIG_TCG.
>
> Having everything inside cpu.h wrapped in a 100 line #ifdef is not
> particularly readable or discoverable, so I think it is actually useful
> for understanding purposes to have it separate...
Ok, so separate, but perhaps not standalone.
My question above remains: what did you need from core/cpu.h? Was it in fact
just a typedef for CPUState?
In which case "qemu/typedefs.h" is a better choice.
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 17:47 ` Claudio Fontana
2020-12-11 18:04 ` Richard Henderson
@ 2020-12-11 18:15 ` Claudio Fontana
2020-12-11 18:22 ` Richard Henderson
1 sibling, 1 reply; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 18:15 UTC (permalink / raw)
To: Richard Henderson, Paolo Bonzini, Thomas Huth,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy, Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 6:47 PM, Claudio Fontana wrote:
> On 12/11/20 6:28 PM, Richard Henderson wrote:
>> On 12/11/20 11:10 AM, Claudio Fontana wrote:
>>> On 12/11/20 6:05 PM, Richard Henderson wrote:
>>>> On 12/11/20 2:31 AM, Claudio Fontana wrote:
>>>>> From: Eduardo Habkost <ehabkost@redhat.com>
>>>>>
>>>>> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
>>>>> [claudio: wrapped in CONFIG_TCG]
>>>>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>>>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>>>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>>>>> ---
>>>>> include/hw/core/cpu.h | 8 --------
>>>>> include/hw/core/tcg-cpu-ops.h | 12 ++++++++++++
>>>>> accel/tcg/cpu-exec.c | 4 ++--
>>>>> target/arm/cpu.c | 4 +++-
>>>>> target/avr/cpu.c | 2 +-
>>>>> target/hppa/cpu.c | 2 +-
>>>>> target/i386/tcg/tcg-cpu.c | 2 +-
>>>>> target/microblaze/cpu.c | 2 +-
>>>>> target/mips/cpu.c | 4 +++-
>>>>> target/riscv/cpu.c | 2 +-
>>>>> target/rx/cpu.c | 2 +-
>>>>> target/sh4/cpu.c | 2 +-
>>>>> target/sparc/cpu.c | 2 +-
>>>>> target/tricore/cpu.c | 2 +-
>>>>> 14 files changed, 29 insertions(+), 21 deletions(-)
>>>>>
>>>>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
>>>>> index ea648d52ad..83007d262c 100644
>>>>> --- a/include/hw/core/cpu.h
>>>>> +++ b/include/hw/core/cpu.h
>>>>> @@ -110,13 +110,6 @@ struct TranslationBlock;
>>>>> * If the target behaviour here is anything other than "set
>>>>> * the PC register to the value passed in" then the target must
>>>>> * also implement the synchronize_from_tb hook.
>>>>> - * @synchronize_from_tb: Callback for synchronizing state from a TCG
>>>>> - * #TranslationBlock. This is called when we abandon execution
>>>>> - * of a TB before starting it, and must set all parts of the CPU
>>>>> - * state which the previous TB in the chain may not have updated.
>>>>> - * This always includes at least the program counter; some targets
>>>>> - * will need to do more. If this hook is not implemented then the
>>>>> - * default is to call @set_pc(tb->pc).
>>>>> * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
>>>>> * address fault. For system mode, if the access is valid, call
>>>>> * tlb_set_page and return true; if the access is invalid, and
>>>>> @@ -193,7 +186,6 @@ struct CPUClass {
>>>>> void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
>>>>> Error **errp);
>>>>> void (*set_pc)(CPUState *cpu, vaddr value);
>>>>> - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
>>>>> bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
>>>>> MMUAccessType access_type, int mmu_idx,
>>>>> bool probe, uintptr_t retaddr);
>>>>> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
>>>>> index 4475ef0996..e1d50b3c8b 100644
>>>>> --- a/include/hw/core/tcg-cpu-ops.h
>>>>> +++ b/include/hw/core/tcg-cpu-ops.h
>>>>> @@ -10,6 +10,8 @@
>>>>> #ifndef TCG_CPU_OPS_H
>>>>> #define TCG_CPU_OPS_H
>>>>>
>>>>> +#include "hw/core/cpu.h"
>>>>
>>>> This include is circular.
>>>
>>> Yes, it's protected though, it was asked that way.
>>
>> Well, in my strong opinion, someone asked incorrectly. It's "harmless" because
>> of the protection ifdefs, but it's Wrong because it has the potential to hide bugs.
>>
>> What is it that you thought you needed from core/cpu.h anyway?
>>
>>>> Are you sure that splitting out hw/core/tcg-cpu-ops.h from hw/core/cpu.h in
>>>> patch 15 is even useful?
>>>
>>> it avoids a huge #ifdef CONFIG_TCG
>>
>> So? The question should be: is it useful on its own, and I think the answer to
>> that is clearly not. Thus it should not pretend to be a standalone header file.
>>
>>
>> r~
>>
>
> The whole point of the exercise is to sort out what is tcg specific and only compile it under CONFIG_TCG.
>
> Having everything inside cpu.h wrapped in a 100 line #ifdef is not particularly readable or discoverable,
> so I think it is actually useful for understanding purposes to have it separate,
> but that said, I don't feel strongly on this, as I intend to improve this in later series.
>
Should I return this file to the original state (without the extra #includes that pretend it to be a standalone header file,
and call it
tcg-cpu-ops.h.inc
?
Ciao,
Claudio
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 18:15 ` Claudio Fontana
@ 2020-12-11 18:22 ` Richard Henderson
2020-12-11 18:26 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 69+ messages in thread
From: Richard Henderson @ 2020-12-11 18:22 UTC (permalink / raw)
To: Claudio Fontana, Paolo Bonzini, Thomas Huth, Stefano Stabellini,
Wenchao Wang, Roman Bolshakov, Sunil Muthuswamy,
Philippe Mathieu-Daudé
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 12:15 PM, Claudio Fontana wrote:
> Should I return this file to the original state (without the extra #includes that pretend it to be a standalone header file,
> and call it
>
> tcg-cpu-ops.h.inc
>
> ?
If this header can work with qemu/typedefs.h, then no, because the circularity
has been resolved. Otherwise, yes.
Thanks,
r~
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 18:22 ` Richard Henderson
@ 2020-12-11 18:26 ` Philippe Mathieu-Daudé
2020-12-11 18:51 ` Claudio Fontana
0 siblings, 1 reply; 69+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-11 18:26 UTC (permalink / raw)
To: Richard Henderson, Claudio Fontana, Paolo Bonzini, Thomas Huth,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 7:22 PM, Richard Henderson wrote:
> On 12/11/20 12:15 PM, Claudio Fontana wrote:
>> Should I return this file to the original state (without the extra #includes that pretend it to be a standalone header file,
>> and call it
>>
>> tcg-cpu-ops.h.inc
>>
>> ?
>
> If this header can work with qemu/typedefs.h, then no, because the circularity
> has been resolved. Otherwise, yes.
My editor got confused with TranslationBlock, which is why I asked
to include its declaration.
Easier to forward-declare TranslationBlock in qemu/typedefs.h?
Regards,
Phil.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 18:26 ` Philippe Mathieu-Daudé
@ 2020-12-11 18:51 ` Claudio Fontana
2020-12-11 18:54 ` Philippe Mathieu-Daudé
2020-12-11 20:02 ` Eduardo Habkost
0 siblings, 2 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-11 18:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé,
Richard Henderson, Paolo Bonzini, Thomas Huth,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 7:26 PM, Philippe Mathieu-Daudé wrote:
> On 12/11/20 7:22 PM, Richard Henderson wrote:
>> On 12/11/20 12:15 PM, Claudio Fontana wrote:
>>> Should I return this file to the original state (without the extra #includes that pretend it to be a standalone header file,
>>> and call it
>>>
>>> tcg-cpu-ops.h.inc
>>>
>>> ?
>>
>> If this header can work with qemu/typedefs.h, then no, because the circularity
>> has been resolved. Otherwise, yes.
>
> My editor got confused with TranslationBlock, which is why I asked
> to include its declaration.
>
> Easier to forward-declare TranslationBlock in qemu/typedefs.h?
>
> Regards,
>
> Phil.
>
Hello Philippe,
ok you propose to move the existing fwd declaration of TranslationBlock from cpu.h to qemu/typedefs.h .
And what about #include "exec/memattrs.h"?
I assume you propose to put struct MemTxAttrs there as a fwd declaration too,
and this concludes our experiment here?
Thanks,
Claudio
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 18:51 ` Claudio Fontana
@ 2020-12-11 18:54 ` Philippe Mathieu-Daudé
2020-12-11 20:02 ` Eduardo Habkost
1 sibling, 0 replies; 69+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-12-11 18:54 UTC (permalink / raw)
To: Claudio Fontana, Richard Henderson, Paolo Bonzini, Thomas Huth,
Stefano Stabellini, Wenchao Wang, Roman Bolshakov,
Sunil Muthuswamy
Cc: Laurent Vivier, Peter Maydell, Eduardo Habkost, Paul Durrant,
Alex Bennée, Jason Wang, Marcelo Tosatti, qemu-devel,
Peter Xu, Dario Faggioli, Cameron Esfahani, haxm-team, Colin Xu,
Anthony Perard, Bruce Rogers, Olaf Hering, Emilio G . Cota
On 12/11/20 7:51 PM, Claudio Fontana wrote:
> On 12/11/20 7:26 PM, Philippe Mathieu-Daudé wrote:
>> On 12/11/20 7:22 PM, Richard Henderson wrote:
>>> On 12/11/20 12:15 PM, Claudio Fontana wrote:
>>>> Should I return this file to the original state (without the extra #includes that pretend it to be a standalone header file,
>>>> and call it
>>>>
>>>> tcg-cpu-ops.h.inc
>>>>
>>>> ?
>>>
>>> If this header can work with qemu/typedefs.h, then no, because the circularity
>>> has been resolved. Otherwise, yes.
>>
>> My editor got confused with TranslationBlock, which is why I asked
>> to include its declaration.
>>
>> Easier to forward-declare TranslationBlock in qemu/typedefs.h?
>>
>> Regards,
>>
>> Phil.
>>
>
> Hello Philippe,
>
> ok you propose to move the existing fwd declaration of TranslationBlock from cpu.h to qemu/typedefs.h .
I'll let that answer to Richard =)
>
> And what about #include "exec/memattrs.h"?
>
> I assume you propose to put struct MemTxAttrs there as a fwd declaration too,
>
> and this concludes our experiment here?
Well, there is no circular problem here, right?
(and Richard already reviewed patch #24 :P )
>
> Thanks,
>
> Claudio
>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 18:51 ` Claudio Fontana
2020-12-11 18:54 ` Philippe Mathieu-Daudé
@ 2020-12-11 20:02 ` Eduardo Habkost
2020-12-12 10:00 ` Claudio Fontana
1 sibling, 1 reply; 69+ messages in thread
From: Eduardo Habkost @ 2020-12-11 20:02 UTC (permalink / raw)
To: Claudio Fontana
Cc: Peter Maydell, Paul Durrant, Jason Wang, qemu-devel, Peter Xu,
haxm-team, Colin Xu, Olaf Hering, Stefano Stabellini,
Bruce Rogers, Emilio G . Cota, Anthony Perard,
Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Alex Bennée, Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On Fri, Dec 11, 2020 at 07:51:54PM +0100, Claudio Fontana wrote:
> On 12/11/20 7:26 PM, Philippe Mathieu-Daudé wrote:
> > On 12/11/20 7:22 PM, Richard Henderson wrote:
> >> On 12/11/20 12:15 PM, Claudio Fontana wrote:
> >>> Should I return this file to the original state (without the extra #includes that pretend it to be a standalone header file,
> >>> and call it
> >>>
> >>> tcg-cpu-ops.h.inc
> >>>
> >>> ?
> >>
> >> If this header can work with qemu/typedefs.h, then no, because the circularity
> >> has been resolved. Otherwise, yes.
> >
> > My editor got confused with TranslationBlock, which is why I asked
> > to include its declaration.
> >
> > Easier to forward-declare TranslationBlock in qemu/typedefs.h?
> >
> > Regards,
> >
> > Phil.
> >
>
> Hello Philippe,
>
> ok you propose to move the existing fwd declaration of TranslationBlock from cpu.h to qemu/typedefs.h .
It seems simpler to just add a
typedef struct TranslationBlock TranslationBlock;
line to tcg-cpu-ops.h.
Or, an even simpler solution: just use `struct TranslationBlock`
instead of `TranslationBlock` in the declarations being moved to
tcg-cpu-ops.h.
We don't need to move declarations to typedefs.h anymore, because
now the compilers we support don't warn about typedef
redefinitions:
https://lore.kernel.org/qemu-devel/20200914134636.GZ1618070@habkost.net/
>
> And what about #include "exec/memattrs.h"?
>
> I assume you propose to put struct MemTxAttrs there as a fwd declaration too,
This can't be done, because MemTxAttrs can't be an incomplete
type in the code you are moving (the methods get a MemTxAttrs
value, not a pointer).
>
> and this concludes our experiment here?
>
> Thanks,
>
> Claudio
>
--
Eduardo
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 05/25] i386: move whpx accel files into whpx/
2020-12-11 8:31 ` [PATCH v11 05/25] i386: move whpx accel files into whpx/ Claudio Fontana
2020-12-11 16:09 ` Richard Henderson
@ 2020-12-11 20:41 ` Eduardo Habkost
2020-12-12 9:24 ` Claudio Fontana
1 sibling, 1 reply; 69+ messages in thread
From: Eduardo Habkost @ 2020-12-11 20:41 UTC (permalink / raw)
To: Claudio Fontana
Cc: Peter Maydell, Paul Durrant, Jason Wang, qemu-devel, Peter Xu,
haxm-team, Colin Xu, Olaf Hering, Stefano Stabellini,
Bruce Rogers, Emilio G . Cota, Anthony Perard,
Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Alex Bennée, Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On Fri, Dec 11, 2020 at 09:31:23AM +0100, Claudio Fontana wrote:
> Signed-off-by: Claudio Fontana <cfontana@suse.de>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> target/i386/{ => whpx}/whp-dispatch.h | 0
> target/i386/{ => whpx}/whpx-cpus.h | 0
> target/i386/{ => whpx}/whpx-all.c | 0
> target/i386/{ => whpx}/whpx-cpus.c | 0
> MAINTAINERS | 5 +----
> target/i386/meson.build | 5 +----
> target/i386/whpx/meson.build | 4 ++++
> 7 files changed, 6 insertions(+), 8 deletions(-)
> rename target/i386/{ => whpx}/whp-dispatch.h (100%)
> rename target/i386/{ => whpx}/whpx-cpus.h (100%)
> rename target/i386/{ => whpx}/whpx-all.c (100%)
> rename target/i386/{ => whpx}/whpx-cpus.c (100%)
> create mode 100644 target/i386/whpx/meson.build
>
Unfortunately this conflicts with commit faf20793b5af ("WHPX:
support for the kernel-irqchip on/off") and needs to be redone.
--
Eduardo
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 05/25] i386: move whpx accel files into whpx/
2020-12-11 20:41 ` Eduardo Habkost
@ 2020-12-12 9:24 ` Claudio Fontana
0 siblings, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-12 9:24 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, Paul Durrant, Jason Wang, qemu-devel, Peter Xu,
haxm-team, Colin Xu, Olaf Hering, Stefano Stabellini,
Bruce Rogers, Emilio G . Cota, Anthony Perard,
Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Alex Bennée, Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On 12/11/20 9:41 PM, Eduardo Habkost wrote:
> On Fri, Dec 11, 2020 at 09:31:23AM +0100, Claudio Fontana wrote:
>> Signed-off-by: Claudio Fontana <cfontana@suse.de>
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>> target/i386/{ => whpx}/whp-dispatch.h | 0
>> target/i386/{ => whpx}/whpx-cpus.h | 0
>> target/i386/{ => whpx}/whpx-all.c | 0
>> target/i386/{ => whpx}/whpx-cpus.c | 0
>> MAINTAINERS | 5 +----
>> target/i386/meson.build | 5 +----
>> target/i386/whpx/meson.build | 4 ++++
>> 7 files changed, 6 insertions(+), 8 deletions(-)
>> rename target/i386/{ => whpx}/whp-dispatch.h (100%)
>> rename target/i386/{ => whpx}/whpx-cpus.h (100%)
>> rename target/i386/{ => whpx}/whpx-all.c (100%)
>> rename target/i386/{ => whpx}/whpx-cpus.c (100%)
>> create mode 100644 target/i386/whpx/meson.build
>>
>
> Unfortunately this conflicts with commit faf20793b5af ("WHPX:
> support for the kernel-irqchip on/off") and needs to be redone.
>
Hi Eduardo, I saw some conflict yesterday yes, it's minor, np.
Ciao,
Claudoi
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-11 20:02 ` Eduardo Habkost
@ 2020-12-12 10:00 ` Claudio Fontana
2020-12-12 11:41 ` Claudio Fontana
2020-12-14 21:04 ` Eduardo Habkost
0 siblings, 2 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-12 10:00 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, Paul Durrant, Jason Wang, qemu-devel, Peter Xu,
haxm-team, Colin Xu, Olaf Hering, Stefano Stabellini,
Bruce Rogers, Emilio G . Cota, Anthony Perard,
Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Alex Bennée, Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On 12/11/20 9:02 PM, Eduardo Habkost wrote:
> On Fri, Dec 11, 2020 at 07:51:54PM +0100, Claudio Fontana wrote:
>> On 12/11/20 7:26 PM, Philippe Mathieu-Daudé wrote:
>>> On 12/11/20 7:22 PM, Richard Henderson wrote:
>>>> On 12/11/20 12:15 PM, Claudio Fontana wrote:
>>>>> Should I return this file to the original state (without the extra #includes that pretend it to be a standalone header file,
>>>>> and call it
>>>>>
>>>>> tcg-cpu-ops.h.inc
>>>>>
>>>>> ?
>>>>
>>>> If this header can work with qemu/typedefs.h, then no, because the circularity
>>>> has been resolved. Otherwise, yes.
>>>
>>> My editor got confused with TranslationBlock, which is why I asked
>>> to include its declaration.
>>>
>>> Easier to forward-declare TranslationBlock in qemu/typedefs.h?
>>>
>>> Regards,
>>>
>>> Phil.
>>>
>>
>> Hello Philippe,
>>
>> ok you propose to move the existing fwd declaration of TranslationBlock from cpu.h to qemu/typedefs.h .
>
> It seems simpler to just add a
>
> typedef struct TranslationBlock TranslationBlock;
>
> line to tcg-cpu-ops.h.
>
> Or, an even simpler solution: just use `struct TranslationBlock`
> instead of `TranslationBlock` in the declarations being moved to
> tcg-cpu-ops.h.
>
> We don't need to move declarations to typedefs.h anymore, because
> now the compilers we support don't warn about typedef
> redefinitions:
> https://lore.kernel.org/qemu-devel/20200914134636.GZ1618070@habkost.net/
>
>
>>
>> And what about #include "exec/memattrs.h"?
>>
>> I assume you propose to put struct MemTxAttrs there as a fwd declaration too,
>
> This can't be done, because MemTxAttrs can't be an incomplete
> type in the code you are moving (the methods get a MemTxAttrs
> value, not a pointer).
I'm confused now on what we are trying to do: if we want the file to be a "proper header" or just a TCG-ops-only convenience split of cpu.h.
I thought that we were only solving a highlighting issue in some editor (Philippe),
and I wonder if these changes in qemu/typedef.h help with that?
I tried adding both to qemu/typedef.h, and since cpu.h is the only user of the file, and it already includes memattrs.h, everything is fine.
But here maybe you are proposing to make it a regular header, and include this instead of just hw/core/cpu.h in the targets?
I am thinking whether it is the case to scrap this whole mess, make TCGCPUOps a pointer in CPUClass, and in the targets say for example:
#include "tcg-cpu-ops.h"
...
+static struct TCGCPUOps cris_tcg_ops = {
+ .initialize = cris_initialize_tcg,
+};
+
static void cris_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -284,7 +292,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = cris_disas_set_info;
- cc->tcg_ops.initialize = cris_initialize_tcg;
+ cc->tcg_ops = &cris_tcg_ops;
}
What do you all think of this?
Thanks,
Claudio
>
>>
>> and this concludes our experiment here?
>>
>> Thanks,
>>
>> Claudio
>>
>
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-12 10:00 ` Claudio Fontana
@ 2020-12-12 11:41 ` Claudio Fontana
2020-12-14 21:04 ` Eduardo Habkost
1 sibling, 0 replies; 69+ messages in thread
From: Claudio Fontana @ 2020-12-12 11:41 UTC (permalink / raw)
To: Eduardo Habkost
Cc: Peter Maydell, Paul Durrant, Jason Wang, qemu-devel, Peter Xu,
haxm-team, Colin Xu, Olaf Hering, Stefano Stabellini,
Bruce Rogers, Emilio G . Cota, Anthony Perard,
Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Alex Bennée, Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On 12/12/20 11:00 AM, Claudio Fontana wrote:
> On 12/11/20 9:02 PM, Eduardo Habkost wrote:
>> On Fri, Dec 11, 2020 at 07:51:54PM +0100, Claudio Fontana wrote:
>>> On 12/11/20 7:26 PM, Philippe Mathieu-Daudé wrote:
>>>> On 12/11/20 7:22 PM, Richard Henderson wrote:
>>>>> On 12/11/20 12:15 PM, Claudio Fontana wrote:
>>>>>> Should I return this file to the original state (without the extra #includes that pretend it to be a standalone header file,
>>>>>> and call it
>>>>>>
>>>>>> tcg-cpu-ops.h.inc
>>>>>>
>>>>>> ?
>>>>>
>>>>> If this header can work with qemu/typedefs.h, then no, because the circularity
>>>>> has been resolved. Otherwise, yes.
>>>>
>>>> My editor got confused with TranslationBlock, which is why I asked
>>>> to include its declaration.
>>>>
>>>> Easier to forward-declare TranslationBlock in qemu/typedefs.h?
>>>>
>>>> Regards,
>>>>
>>>> Phil.
>>>>
>>>
>>> Hello Philippe,
>>>
>>> ok you propose to move the existing fwd declaration of TranslationBlock from cpu.h to qemu/typedefs.h .
>>
>> It seems simpler to just add a
>>
>> typedef struct TranslationBlock TranslationBlock;
>>
>> line to tcg-cpu-ops.h.
>>
>> Or, an even simpler solution: just use `struct TranslationBlock`
>> instead of `TranslationBlock` in the declarations being moved to
>> tcg-cpu-ops.h.
>>
>> We don't need to move declarations to typedefs.h anymore, because
>> now the compilers we support don't warn about typedef
>> redefinitions:
>> https://lore.kernel.org/qemu-devel/20200914134636.GZ1618070@habkost.net/
>>
>>
>>>
>>> And what about #include "exec/memattrs.h"?
>>>
>>> I assume you propose to put struct MemTxAttrs there as a fwd declaration too,
>>
>> This can't be done, because MemTxAttrs can't be an incomplete
>> type in the code you are moving (the methods get a MemTxAttrs
>> value, not a pointer).
>
>
>
> I'm confused now on what we are trying to do: if we want the file to be a "proper header" or just a TCG-ops-only convenience split of cpu.h.
>
> I thought that we were only solving a highlighting issue in some editor (Philippe),
> and I wonder if these changes in qemu/typedef.h help with that?
>
> I tried adding both to qemu/typedef.h, and since cpu.h is the only user of the file, and it already includes memattrs.h, everything is fine.
>
> But here maybe you are proposing to make it a regular header, and include this instead of just hw/core/cpu.h in the targets?
>
> I am thinking whether it is the case to scrap this whole mess, make TCGCPUOps a pointer in CPUClass, and in the targets say for example:
>
> #include "tcg-cpu-ops.h"
>
> ...
>
> +static struct TCGCPUOps cris_tcg_ops = {
> + .initialize = cris_initialize_tcg,
> +};
> +
> static void cris_cpu_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -284,7 +292,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_stop_before_watchpoint = true;
>
> cc->disas_set_info = cris_disas_set_info;
> - cc->tcg_ops.initialize = cris_initialize_tcg;
> + cc->tcg_ops = &cris_tcg_ops;
> }
>
>
> What do you all think of this?
>
> Thanks,
>
> Claudio
Not sure it solves all problems: the MMUAccessType is still a cpu.h enum, so we are back to the circular dependency.
Will try the .inc in the next spin, and I hope that the discussion can go on from there, with Eduardo, Philippe and Richard laying out more clearly what your requirements are.
Thanks,
Claudio
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops
2020-12-12 10:00 ` Claudio Fontana
2020-12-12 11:41 ` Claudio Fontana
@ 2020-12-14 21:04 ` Eduardo Habkost
1 sibling, 0 replies; 69+ messages in thread
From: Eduardo Habkost @ 2020-12-14 21:04 UTC (permalink / raw)
To: Claudio Fontana
Cc: Peter Maydell, Paul Durrant, Jason Wang, qemu-devel, Peter Xu,
haxm-team, Colin Xu, Olaf Hering, Stefano Stabellini,
Bruce Rogers, Emilio G . Cota, Anthony Perard,
Philippe Mathieu-Daudé,
Laurent Vivier, Thomas Huth, Richard Henderson, Cameron Esfahani,
Dario Faggioli, Roman Bolshakov, Sunil Muthuswamy,
Alex Bennée, Marcelo Tosatti, Wenchao Wang, Paolo Bonzini
On Sat, Dec 12, 2020 at 11:00:03AM +0100, Claudio Fontana wrote:
> On 12/11/20 9:02 PM, Eduardo Habkost wrote:
> > On Fri, Dec 11, 2020 at 07:51:54PM +0100, Claudio Fontana wrote:
> >> On 12/11/20 7:26 PM, Philippe Mathieu-Daudé wrote:
> >>> On 12/11/20 7:22 PM, Richard Henderson wrote:
> >>>> On 12/11/20 12:15 PM, Claudio Fontana wrote:
> >>>>> Should I return this file to the original state (without the extra #includes that pretend it to be a standalone header file,
> >>>>> and call it
> >>>>>
> >>>>> tcg-cpu-ops.h.inc
> >>>>>
> >>>>> ?
> >>>>
> >>>> If this header can work with qemu/typedefs.h, then no, because the circularity
> >>>> has been resolved. Otherwise, yes.
> >>>
> >>> My editor got confused with TranslationBlock, which is why I asked
> >>> to include its declaration.
> >>>
> >>> Easier to forward-declare TranslationBlock in qemu/typedefs.h?
> >>>
> >>> Regards,
> >>>
> >>> Phil.
> >>>
> >>
> >> Hello Philippe,
> >>
> >> ok you propose to move the existing fwd declaration of TranslationBlock from cpu.h to qemu/typedefs.h .
> >
> > It seems simpler to just add a
> >
> > typedef struct TranslationBlock TranslationBlock;
> >
> > line to tcg-cpu-ops.h.
> >
> > Or, an even simpler solution: just use `struct TranslationBlock`
> > instead of `TranslationBlock` in the declarations being moved to
> > tcg-cpu-ops.h.
> >
> > We don't need to move declarations to typedefs.h anymore, because
> > now the compilers we support don't warn about typedef
> > redefinitions:
> > https://lore.kernel.org/qemu-devel/20200914134636.GZ1618070@habkost.net/
> >
> >
> >>
> >> And what about #include "exec/memattrs.h"?
> >>
> >> I assume you propose to put struct MemTxAttrs there as a fwd declaration too,
> >
> > This can't be done, because MemTxAttrs can't be an incomplete
> > type in the code you are moving (the methods get a MemTxAttrs
> > value, not a pointer).
>
>
>
> I'm confused now on what we are trying to do: if we want the
> file to be a "proper header" or just a TCG-ops-only convenience
> split of cpu.h.
Personally, I don't see the point of creating a new header if
it's not a proper header.
>
> I thought that we were only solving a highlighting issue in some editor (Philippe),
> and I wonder if these changes in qemu/typedef.h help with that?
>
> I tried adding both to qemu/typedef.h, and since cpu.h is the only user of the file, and it already includes memattrs.h, everything is fine.
>
> But here maybe you are proposing to make it a regular header, and include this instead of just hw/core/cpu.h in the targets?
>
> I am thinking whether it is the case to scrap this whole mess, make TCGCPUOps a pointer in CPUClass, and in the targets say for example:
>
> #include "tcg-cpu-ops.h"
>
> ...
>
> +static struct TCGCPUOps cris_tcg_ops = {
> + .initialize = cris_initialize_tcg,
> +};
> +
> static void cris_cpu_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -284,7 +292,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
> cc->gdb_stop_before_watchpoint = true;
>
> cc->disas_set_info = cris_disas_set_info;
> - cc->tcg_ops.initialize = cris_initialize_tcg;
> + cc->tcg_ops = &cris_tcg_ops;
> }
>
>
> What do you all think of this?
Making tcg_ops a pointer may make a lot of sense, but (as
mentioned in my reply to v12) I'm worried by the scope of this
series growing too much.
I suggest doing this refactor in smaller steps, to let us focus
in a single issue at a time. Instead of splitting the struct and
creating a new header file in a single patch, you can first
create the new struct in the same header, and worry about moving
it to a separate header later (in the same series, or in another
series).
--
Eduardo
^ permalink raw reply [flat|nested] 69+ messages in thread
end of thread, other threads:[~2020-12-14 21:06 UTC | newest]
Thread overview: 69+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-11 8:31 [PATCH v11 00/25] i386 cleanup PART 1 Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 01/25] accel/tcg: split CpusAccel into three TCG variants Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 02/25] accel/tcg: split tcg_start_vcpu_thread Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 03/25] accel/tcg: rename tcg-cpus functions to match module name Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 04/25] i386: move kvm accel files into kvm/ Claudio Fontana
2020-12-11 16:08 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 05/25] i386: move whpx accel files into whpx/ Claudio Fontana
2020-12-11 16:09 ` Richard Henderson
2020-12-11 20:41 ` Eduardo Habkost
2020-12-12 9:24 ` Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 06/25] i386: move hax accel files into hax/ Claudio Fontana
2020-12-11 16:10 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 07/25] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 08/25] i386: move TCG accel files into tcg/ Claudio Fontana
2020-12-11 16:10 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 09/25] i386: move cpu dump out of helper.c into cpu-dump.c Claudio Fontana
2020-12-11 16:13 ` Richard Henderson
2020-12-11 17:21 ` Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 10/25] i386: move TCG cpu class initialization out of helper.c Claudio Fontana
2020-12-11 16:44 ` Richard Henderson
2020-12-11 17:31 ` Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 11/25] tcg: cpu_exec_{enter,exit} helpers Claudio Fontana
2020-12-11 16:45 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 12/25] tcg: make CPUClass.cpu_exec_* optional Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 13/25] tcg: Make CPUClass.debug_excp_handler optional Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 14/25] cpu: Remove unnecessary noop methods Claudio Fontana
2020-12-11 11:05 ` Philippe Mathieu-Daudé
2020-12-11 8:31 ` [PATCH v11 15/25] cpu: Introduce TCGCpuOperations struct Claudio Fontana
2020-12-11 16:55 ` Richard Henderson
2020-12-11 16:57 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 16/25] target/riscv: remove CONFIG_TCG, as it is always TCG Claudio Fontana
2020-12-11 16:56 ` Richard Henderson
2020-12-11 17:19 ` Claudio Fontana
2020-12-11 8:31 ` [PATCH v11 17/25] accel/tcg: split TCG-only code from cpu_exec_realizefn Claudio Fontana
2020-12-11 16:58 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 18/25] cpu: Move synchronize_from_tb() to tcg_ops Claudio Fontana
2020-12-11 17:05 ` Richard Henderson
2020-12-11 17:10 ` Claudio Fontana
2020-12-11 17:11 ` Claudio Fontana
2020-12-11 17:28 ` Richard Henderson
2020-12-11 17:47 ` Claudio Fontana
2020-12-11 18:04 ` Richard Henderson
2020-12-11 18:15 ` Claudio Fontana
2020-12-11 18:22 ` Richard Henderson
2020-12-11 18:26 ` Philippe Mathieu-Daudé
2020-12-11 18:51 ` Claudio Fontana
2020-12-11 18:54 ` Philippe Mathieu-Daudé
2020-12-11 20:02 ` Eduardo Habkost
2020-12-12 10:00 ` Claudio Fontana
2020-12-12 11:41 ` Claudio Fontana
2020-12-14 21:04 ` Eduardo Habkost
2020-12-11 8:31 ` [PATCH v11 19/25] cpu: Move cpu_exec_* " Claudio Fontana
2020-12-11 17:30 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 20/25] cpu: Move tlb_fill " Claudio Fontana
2020-12-11 17:42 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 21/25] cpu: Move debug_excp_handler " Claudio Fontana
2020-12-11 17:44 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 22/25] target/arm: do not use cc->do_interrupt for KVM directly Claudio Fontana
2020-12-11 17:44 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 23/25] cpu: move cc->do_interrupt to tcg_ops Claudio Fontana
2020-12-11 17:46 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 24/25] cpu: move cc->transaction_failed " Claudio Fontana
2020-12-11 11:00 ` Philippe Mathieu-Daudé
2020-12-11 17:50 ` Richard Henderson
2020-12-11 8:31 ` [PATCH v11 25/25] cpu: move do_unaligned_access " Claudio Fontana
2020-12-11 11:01 ` Philippe Mathieu-Daudé
2020-12-11 17:58 ` Richard Henderson
2020-12-11 8:57 ` [PATCH v11 00/25] i386 cleanup PART 1 no-reply
2020-12-11 11:07 ` Philippe Mathieu-Daudé
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