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Mon, 14 Dec 2020 09:14:02 -0500 (EST) Date: Mon, 14 Dec 2020 15:14:00 +0100 From: Maxime Ripard To: Chen-Yu Tsai Cc: =?utf-8?B?QW5kcsOp?= Przywara , Jernej Skrabec , Icenowy Zheng , Linus Walleij , Rob Herring , =?utf-8?B?Q2zDqW1lbnQgUMOpcm9u?= , Shuosheng Huang , Yangtao Li , linux-arm-kernel , linux-kernel , linux-sunxi , devicetree Subject: Re: [linux-sunxi] Re: [PATCH v2 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Message-ID: <20201214141400.des3jwfhmbnxd7xe@gilmour> References: <20201211011934.6171-1-andre.przywara@arm.com> <20201211011934.6171-20-andre.przywara@arm.com> <20201214095831.j63nks3fqxlaw75w@gilmour> <20201214125343.0cd1bc6a@slackpad.fritz.box> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="64zcwd4wdxdwsyj3" Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --64zcwd4wdxdwsyj3 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Dec 14, 2020 at 09:28:36PM +0800, Chen-Yu Tsai wrote: > On Mon, Dec 14, 2020 at 8:53 PM Andre Przywara w= rote: > > > > On Mon, 14 Dec 2020 10:58:31 +0100 > > Maxime Ripard wrote: > > > > Hi, > > > > > On Fri, Dec 11, 2020 at 01:19:32AM +0000, Andre Przywara wrote: > > > > + reserved-memory { > > > > + #address-cells =3D <2>; > > > > + #size-cells =3D <2>; > > > > + ranges; > > > > + > > > > + /* 512KiB reserved for ARM Trusted Firmware (BL31) > > > > */ > > > > + secmon_reserved: secmon@40000000 { > > > > + reg =3D <0x0 0x40000000 0x0 0x80000>; > > > > + no-map; > > > > + }; > > > > + }; > > > > > > This should still be set by the firmware > > > > > > > + mmc0: mmc@4020000 { > > > > + compatible =3D "allwinner,sun50i-h616-mmc", > > > > + "allwinner,sun50i-a100-mmc"; > > > > + reg =3D <0x04020000 0x1000>; > > > > + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu > > > > CLK_MMC0>; > > > > + clock-names =3D "ahb", "mmc"; > > > > + resets =3D <&ccu RST_BUS_MMC0>; > > > > + reset-names =3D "ahb"; > > > > + interrupts =3D > > > IRQ_TYPE_LEVEL_HIGH>; > > > > + pinctrl-names =3D "default"; > > > > + pinctrl-0 =3D <&mmc0_pins>; > > > > + status =3D "disabled"; > > > > + #address-cells =3D <1>; > > > > + #size-cells =3D <0>; > > > > + }; > > > > > > Somewhat related: we shouldn't set the MMC speed flags in the drivers. > > > This is biting us on the already supported SoCs, so it would be great > > > to not repeat the same mistake with the new ones > > > > Do you mean to list the "sd-uhs-sdr50" and friends properties here in > > the DT? > > What is the best practice here in terms putting them in the .dts vs. > > the .dtsi? Surely the controller has limits, but bad traces on a board > > could impose further restrictions, right? > > Though that's probably rare, so it sounds like a lot of churn to list > > them in every board DT. So can we list everything in here (.dtsi), then > > delete in those affected boards only? >=20 > The driver will most certainly already have the basic high speed modes > enabled. Or we can list them in the .dtsi file. I'd list them all in the DTSI, trying to be smart has bitten us already so I'd like to avoid it as much as possible. And if we find a better way, we can set it in the driver if it's in the DTSI already. doing the opposite would be harder Maxime --64zcwd4wdxdwsyj3 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCX9dzKAAKCRDj7w1vZxhR xYxQAQD05F90JhDUdr3GvaKEJQquCi8Tn5R6I8mNQHN9twlqtAEA/M9pX42neqt3 LRIEV6YkIcUb/12pIeA4eDNUBy27sgk= =gQPC -----END PGP SIGNATURE----- --64zcwd4wdxdwsyj3-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD2E9C4361B for ; Mon, 14 Dec 2020 14:15:20 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8AE2522B47 for ; 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Mon, 14 Dec 2020 09:14:02 -0500 (EST) Date: Mon, 14 Dec 2020 15:14:00 +0100 From: Maxime Ripard To: Chen-Yu Tsai Subject: Re: [linux-sunxi] Re: [PATCH v2 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Message-ID: <20201214141400.des3jwfhmbnxd7xe@gilmour> References: <20201211011934.6171-1-andre.przywara@arm.com> <20201211011934.6171-20-andre.przywara@arm.com> <20201214095831.j63nks3fqxlaw75w@gilmour> <20201214125343.0cd1bc6a@slackpad.fritz.box> MIME-Version: 1.0 In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201214_091405_156317_EF4F81A5 X-CRM114-Status: GOOD ( 24.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Jernej Skrabec , devicetree , Yangtao Li , =?utf-8?B?QW5kcsOp?= Przywara , Linus Walleij , linux-kernel , linux-sunxi , =?utf-8?B?Q2zDqW1lbnQgUMOpcm9u?= , Icenowy Zheng , Shuosheng Huang , linux-arm-kernel Content-Type: multipart/mixed; boundary="===============7031461577754395114==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============7031461577754395114== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="64zcwd4wdxdwsyj3" Content-Disposition: inline --64zcwd4wdxdwsyj3 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Dec 14, 2020 at 09:28:36PM +0800, Chen-Yu Tsai wrote: > On Mon, Dec 14, 2020 at 8:53 PM Andre Przywara w= rote: > > > > On Mon, 14 Dec 2020 10:58:31 +0100 > > Maxime Ripard wrote: > > > > Hi, > > > > > On Fri, Dec 11, 2020 at 01:19:32AM +0000, Andre Przywara wrote: > > > > + reserved-memory { > > > > + #address-cells =3D <2>; > > > > + #size-cells =3D <2>; > > > > + ranges; > > > > + > > > > + /* 512KiB reserved for ARM Trusted Firmware (BL31) > > > > */ > > > > + secmon_reserved: secmon@40000000 { > > > > + reg =3D <0x0 0x40000000 0x0 0x80000>; > > > > + no-map; > > > > + }; > > > > + }; > > > > > > This should still be set by the firmware > > > > > > > + mmc0: mmc@4020000 { > > > > + compatible =3D "allwinner,sun50i-h616-mmc", > > > > + "allwinner,sun50i-a100-mmc"; > > > > + reg =3D <0x04020000 0x1000>; > > > > + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu > > > > CLK_MMC0>; > > > > + clock-names =3D "ahb", "mmc"; > > > > + resets =3D <&ccu RST_BUS_MMC0>; > > > > + reset-names =3D "ahb"; > > > > + interrupts =3D > > > IRQ_TYPE_LEVEL_HIGH>; > > > > + pinctrl-names =3D "default"; > > > > + pinctrl-0 =3D <&mmc0_pins>; > > > > + status =3D "disabled"; > > > > + #address-cells =3D <1>; > > > > + #size-cells =3D <0>; > > > > + }; > > > > > > Somewhat related: we shouldn't set the MMC speed flags in the drivers. > > > This is biting us on the already supported SoCs, so it would be great > > > to not repeat the same mistake with the new ones > > > > Do you mean to list the "sd-uhs-sdr50" and friends properties here in > > the DT? > > What is the best practice here in terms putting them in the .dts vs. > > the .dtsi? Surely the controller has limits, but bad traces on a board > > could impose further restrictions, right? > > Though that's probably rare, so it sounds like a lot of churn to list > > them in every board DT. So can we list everything in here (.dtsi), then > > delete in those affected boards only? >=20 > The driver will most certainly already have the basic high speed modes > enabled. Or we can list them in the .dtsi file. I'd list them all in the DTSI, trying to be smart has bitten us already so I'd like to avoid it as much as possible. And if we find a better way, we can set it in the driver if it's in the DTSI already. doing the opposite would be harder Maxime --64zcwd4wdxdwsyj3 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCX9dzKAAKCRDj7w1vZxhR xYxQAQD05F90JhDUdr3GvaKEJQquCi8Tn5R6I8mNQHN9twlqtAEA/M9pX42neqt3 LRIEV6YkIcUb/12pIeA4eDNUBy27sgk= =gQPC -----END PGP SIGNATURE----- --64zcwd4wdxdwsyj3-- --===============7031461577754395114== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============7031461577754395114==--