[PATCH 05/26] x86: apl: Move priv/plat structs to headers

From: Simon Glass <sjg@chromium.org>
To: u-boot@lists.denx.de
Subject: [PATCH 05/26] x86: apl: Move priv/plat structs to headers
Date: Sat, 19 Dec 2020 10:39:57 -0700	[thread overview]
Message-ID: <20201219174018.1114146-4-sjg@chromium.org> (raw)
In-Reply-To: <20201219174018.1114146-1-sjg@chromium.org>

With the new of-platdata, these need to be available to dt_platdata.c
so must be in header files. Move them.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/apollolake/hostbridge.c          | 20 +------------
 arch/x86/cpu/apollolake/pmc.c                 |  8 +-----
 arch/x86/include/asm/arch-apollolake/gpio.h   | 18 ++++++++++++
 .../include/asm/arch-apollolake/hostbridge.h  | 28 +++++++++++++++++++
 arch/x86/include/asm/arch-apollolake/pmc.h    | 16 +++++++++++
 drivers/pinctrl/intel/pinctrl_apl.c           | 12 --------
 6 files changed, 64 insertions(+), 38 deletions(-)
 create mode 100644 arch/x86/include/asm/arch-apollolake/hostbridge.h
 create mode 100644 arch/x86/include/asm/arch-apollolake/pmc.h

diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c
index 9ec2309d086..9decab7aa33 100644
--- a/arch/x86/cpu/apollolake/hostbridge.c
+++ b/arch/x86/cpu/apollolake/hostbridge.c
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/arch/acpi.h>
+#include <asm/arch/hostbridge.h>
 #include <asm/arch/systemagent.h>
 #include <dt-bindings/sound/nhlt.h>
 #include <dm/acpi.h>
@@ -41,25 +42,6 @@ enum {
 	TOLUD			= 0xbc,
 };
 
-/**
- * struct apl_hostbridge_plat - platform data for hostbridge
- *
- * @dtplat: Platform data for of-platdata
- * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
- * @early_pads_count: Number of pads to process
- * @pciex_region_size: BAR length in bytes
- * @bdf: Bus/device/function of hostbridge
- */
-struct apl_hostbridge_plat {
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-	struct dtd_intel_apl_hostbridge dtplat;
-#endif
-	u32 *early_pads;
-	int early_pads_count;
-	uint pciex_region_size;
-	pci_dev_t bdf;
-};
-
 #if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
 static const struct nhlt_format_config dmic_1ch_formats[] = {
 	/* 48 KHz 16-bits per sample. */
diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c
index e033baf1205..e23d38ea072 100644
--- a/arch/x86/cpu/apollolake/pmc.c
+++ b/arch/x86/cpu/apollolake/pmc.c
@@ -16,6 +16,7 @@
 #include <acpi/acpi_s3.h>
 #include <asm/io.h>
 #include <asm/pci.h>
+#include <asm/arch/pmc.h>
 #include <linux/bitops.h>
 #include <power/acpi_pmc.h>
 
@@ -53,13 +54,6 @@ enum {
 	CF9_GLB_RST	= 1 << 20,
 };
 
-struct apl_pmc_plat {
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-	struct dtd_intel_apl_pmc dtplat;
-#endif
-	pci_dev_t bdf;
-};
-
 static int apl_pmc_fill_power_state(struct udevice *dev)
 {
 	struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
diff --git a/arch/x86/include/asm/arch-apollolake/gpio.h b/arch/x86/include/asm/arch-apollolake/gpio.h
index ab5860c0fd0..762160da882 100644
--- a/arch/x86/include/asm/arch-apollolake/gpio.h
+++ b/arch/x86/include/asm/arch-apollolake/gpio.h
@@ -485,4 +485,22 @@
 /* This is needed by ACPI */
 #define GPIO_NUM_PAD_CFG_REGS   2 /* DW0, DW1 */
 
+#ifndef __ASSEMBLY__
+
+#include <dt-structs.h>
+
+/**
+ * struct apl_gpio_plat - platform data for each device
+ *
+ * @dtplat: of-platdata data from C struct
+ */
+struct apl_gpio_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	/* Put this first since driver model will copy the data here */
+	struct dtd_intel_apl_pinctrl dtplat;
+#endif
+};
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* _ASM_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-apollolake/hostbridge.h b/arch/x86/include/asm/arch-apollolake/hostbridge.h
new file mode 100644
index 00000000000..f4dce0d5224
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/hostbridge.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef _ASM_ARCH_HOSTBRIDGE_H_
+#define _ASM_ARCH_HOSTBRIDGE_H_
+
+/**
+ * struct apl_hostbridge_plat - platform data for hostbridge
+ *
+ * @dtplat: Platform data for of-platdata
+ * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
+ * @early_pads_count: Number of pads to process
+ * @pciex_region_size: BAR length in bytes
+ * @bdf: Bus/device/function of hostbridge
+ */
+struct apl_hostbridge_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_intel_apl_hostbridge dtplat;
+#endif
+	u32 *early_pads;
+	int early_pads_count;
+	uint pciex_region_size;
+	pci_dev_t bdf;
+};
+
+#endif /* _ASM_ARCH_HOSTBRIDGE_H_ */
diff --git a/arch/x86/include/asm/arch-apollolake/pmc.h b/arch/x86/include/asm/arch-apollolake/pmc.h
new file mode 100644
index 00000000000..23ac8fe7e20
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/pmc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef ASM_ARCH_PMC_H
+#define ASM_ARCH_PMC_H
+
+struct apl_pmc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_intel_apl_pmc dtplat;
+#endif
+	pci_dev_t bdf;
+};
+
+#endif	/* ASM_ARCH_PMC_H */
diff --git a/drivers/pinctrl/intel/pinctrl_apl.c b/drivers/pinctrl/intel/pinctrl_apl.c
index b512a85f3e6..acaa55d2e7f 100644
--- a/drivers/pinctrl/intel/pinctrl_apl.c
+++ b/drivers/pinctrl/intel/pinctrl_apl.c
@@ -17,18 +17,6 @@
 #include <asm-generic/gpio.h>
 #include <asm/intel_pinctrl_defs.h>
 
-/**
- * struct apl_gpio_plat - platform data for each device
- *
- * @dtplat: of-platdata data from C struct
- */
-struct apl_gpio_plat {
-#if CONFIG_IS_ENABLED(OF_PLATDATA)
-	/* Put this first since driver model will copy the data here */
-	struct dtd_intel_apl_pinctrl dtplat;
-#endif
-};
-
 static const struct reset_mapping rst_map[] = {
 	{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
 	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
-- 
2.29.2.684.gfbc64c5ab5-goog
