From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AB3DC0018C for ; Sat, 19 Dec 2020 19:52:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E50B023131 for ; Sat, 19 Dec 2020 19:52:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727677AbgLSTwY (ORCPT ); Sat, 19 Dec 2020 14:52:24 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:34364 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727435AbgLSTwY (ORCPT ); Sat, 19 Dec 2020 14:52:24 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kqiGL-00CtDB-9X; Sat, 19 Dec 2020 20:51:33 +0100 Date: Sat, 19 Dec 2020 20:51:33 +0100 From: Andrew Lunn To: Steen Hegelund Cc: "David S. Miller" , Jakub Kicinski , Russell King , Lars Povlsen , Bjarni Jonasson , Microchip Linux Driver Support , Alexandre Belloni , Madalin Bucur , Nicolas Ferre , Mark Einon , Masahiro Yamada , Arnd Bergmann , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [RFC PATCH v2 3/8] net: sparx5: add hostmode with phylink support Message-ID: <20201219195133.GD3026679@lunn.ch> References: <20201217075134.919699-1-steen.hegelund@microchip.com> <20201217075134.919699-4-steen.hegelund@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201217075134.919699-4-steen.hegelund@microchip.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > + /* Create a phylink for PHY management. Also handles SFPs */ > + spx5_port->phylink_config.dev = &spx5_port->ndev->dev; > + spx5_port->phylink_config.type = PHYLINK_NETDEV; > + spx5_port->phylink_config.pcs_poll = true; > + > + /* phylink needs a valid interface mode to parse dt node */ > + if (phy_mode == PHY_INTERFACE_MODE_NA) > + phy_mode = PHY_INTERFACE_MODE_10GBASER; Maybe just enforce a valid value in DT? > +/* Configuration */ > +static inline bool sparx5_use_cu_phy(struct sparx5_port *port) > +{ > + return port->conf.phy_mode != PHY_INTERFACE_MODE_NA; > +} That is a rather odd definition of copper. > diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c > new file mode 100644 > index 000000000000..6f9282e9d3f4 > --- /dev/null > +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c > @@ -0,0 +1,203 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* Microchip Sparx5 Switch driver > + * > + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. > + */ > + > +#include "sparx5_main.h" I don't actually know what is preferred here, but very few drivers i've reviewed put all the required headers into another header file. They normally list them in each .c file. > +static int sparx5_port_open(struct net_device *ndev) > +{ > + struct sparx5_port *port = netdev_priv(ndev); > + int err = 0; > + > + err = phylink_of_phy_connect(port->phylink, port->of_node, 0); > + if (err) { > + netdev_err(ndev, "Could not attach to PHY\n"); > + return err; > + } > + > + phylink_start(port->phylink); > + > + if (!ndev->phydev) { Humm. When is ndev->phydev set? I don't think phylink ever sets it. > + /* power up serdes */ > + port->conf.power_down = false; > + err = phy_power_on(port->serdes); > + if (err) > + netdev_err(ndev, "%s failed\n", __func__); > + } > + > + return err; > +} > +struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno) > +{ > + struct net_device *ndev; > + struct sparx5_port *spx5_port; > + > + ndev = devm_alloc_etherdev(sparx5->dev, sizeof(struct sparx5_port)); > + if (!ndev) > + return ERR_PTR(-ENOMEM); > + > + SET_NETDEV_DEV(ndev, sparx5->dev); > + spx5_port = netdev_priv(ndev); > + spx5_port->ndev = ndev; > + spx5_port->sparx5 = sparx5; > + spx5_port->portno = portno; > + sparx5_set_port_ifh(spx5_port->ifh, portno); > + snprintf(ndev->name, IFNAMSIZ, "eth%d", portno); > + > + ether_setup(ndev); devm_alloc_etherdev() should of already called ether_setup(). > + ndev->netdev_ops = &sparx5_port_netdev_ops; > + ndev->features |= NETIF_F_LLTX; /* software tx */ > + > + ether_addr_copy(ndev->dev_addr, sparx5->base_mac); > + ndev->dev_addr[ETH_ALEN - 1] += portno + 1; That will cause some surprises with wrap around. Use eth_addr_inc() > +static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap) > +{ > + int i, byte_cnt = 0; > + bool eof_flag = false, pruned_flag = false, abort_flag = false; > + u32 ifh[IFH_LEN]; > + struct sk_buff *skb; > + struct frame_info fi; > + struct sparx5_port *port; > + struct net_device *netdev; > + u32 *rxbuf; > + > + /* Get IFH */ > + for (i = 0; i < IFH_LEN; i++) > + ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp)); > + > + /* Decode IFH (whats needed) */ > + sparx5_ifh_parse(ifh, &fi); > + > + /* Map to port netdev */ > + port = fi.src_port < SPX5_PORTS ? > + sparx5->ports[fi.src_port] : NULL; > + if (!port || !port->ndev) { > + dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); > + sparx5_xtr_flush(sparx5, grp); > + return; > + } > + > + /* Have netdev, get skb */ > + netdev = port->ndev; > + skb = netdev_alloc_skb(netdev, netdev->mtu + ETH_HLEN); > + if (!skb) { > + sparx5_xtr_flush(sparx5, grp); > + dev_err(sparx5->dev, "No skb allocated\n"); > + return; > + } > + rxbuf = (u32 *)skb->data; > + > + /* Now, pull frame data */ > + while (!eof_flag) { > + u32 val = spx5_rd(sparx5, QS_XTR_RD(grp)); > + u32 cmp = val; > + > + if (byte_swap) > + cmp = ntohl((__force __be32)val); > + > + switch (cmp) { > + case XTR_NOT_READY: > + break; > + case XTR_ABORT: > + /* No accompanying data */ > + abort_flag = true; > + eof_flag = true; > + break; > + case XTR_EOF_0: > + case XTR_EOF_1: > + case XTR_EOF_2: > + case XTR_EOF_3: > + /* This assumes STATUS_WORD_POS == 1, Status > + * just after last data > + */ > + byte_cnt -= (4 - XTR_VALID_BYTES(val)); > + eof_flag = true; > + break; > + case XTR_PRUNED: > + /* But get the last 4 bytes as well */ > + eof_flag = true; > + pruned_flag = true; > + fallthrough; > + case XTR_ESCAPE: > + *rxbuf = spx5_rd(sparx5, QS_XTR_RD(grp)); > + byte_cnt += 4; > + rxbuf++; > + break; > + default: > + *rxbuf = val; > + byte_cnt += 4; > + rxbuf++; > + } > + } > + > + if (abort_flag || pruned_flag || !eof_flag) { > + netdev_err(netdev, "Discarded frame: abort:%d pruned:%d eof:%d\n", > + abort_flag, pruned_flag, eof_flag); > + kfree_skb(skb); > + return; > + } > + > + if (!netif_oper_up(netdev)) { > + netdev_err(netdev, "Discarded frame: Interface not up\n"); > + kfree_skb(skb); > + return; > + } Why is it sending frames when it is not up? > +static int sparx5_inject(struct sparx5 *sparx5, > + u32 *ifh, > + struct sk_buff *skb) > +{ > + u32 val, w, count; > + int grp = INJ_QUEUE; > + u8 *buf; > + > + val = spx5_rd(sparx5, QS_INJ_STATUS); > + if (!(QS_INJ_STATUS_FIFO_RDY_GET(val) & BIT(grp))) { > + pr_err("Injection: Queue not ready: 0x%lx\n", > + QS_INJ_STATUS_FIFO_RDY_GET(val)); > + return -1; Always use -ESOMETHING. > + } > + > + if (QS_INJ_STATUS_WMARK_REACHED_GET(val) & BIT(grp)) { > + pr_err("Injection: Watermark reached: 0x%lx\n", > + QS_INJ_STATUS_WMARK_REACHED_GET(val)); > + return -1; > + } > + > + /* Indicate SOF */ > + spx5_wr(QS_INJ_CTRL_SOF_SET(1) | > + QS_INJ_CTRL_GAP_SIZE_SET(1), > + sparx5, QS_INJ_CTRL(grp)); > + > + // Write the IFH to the chip. > + for (w = 0; w < IFH_LEN; w++) > + spx5_wr(ifh[w], sparx5, QS_INJ_WR(grp)); > + > + /* Write words, round up */ > + count = ((skb->len + 3) / 4); > + buf = skb->data; > + for (w = 0; w < count; w++, buf += 4) { > + val = get_unaligned((const u32 *)buf); > + spx5_wr(val, sparx5, QS_INJ_WR(grp)); > + } No DMA? What sort of performance do you get? Enough for the odd BPDU, IGMP frame etc, but i guess you don't want any real bulk data to be sent this way? > +irqreturn_t sparx5_xtr_handler(int irq, void *_sparx5) > +{ > + struct sparx5 *sparx5 = _sparx5; > + > + /* Check data in queue */ > + while (spx5_rd(sparx5, QS_XTR_DATA_PRESENT) & BIT(XTR_QUEUE)) > + sparx5_xtr_grp(sparx5, XTR_QUEUE, false); > + > + return IRQ_HANDLED; > +} Is there any sort of limit how many times this will loop? If somebody is blasting 10Gbps at the CPU, will it ever get out of this loop? Andrew From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC691C4361B for ; Sat, 19 Dec 2020 19:53:11 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 83F0A227BF for ; Sat, 19 Dec 2020 19:53:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 83F0A227BF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=lunn.ch Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=CvEu8nKkxFbAMwpTyntK3gLxL10sTG5p/pi7zhkaXKo=; b=YXtXgJsXNJi9v5k3VvS/6wkZN 0E7m8YTKXpCLfQSjQsC0keBi4KCuFOxn3AvefD6+PSRTZ4zD89kkSLcX6GYuuyEX79F7lbiNp4mx6 qysGNZ2AaQRxWTU00kxb8pX2cog85jVjBeudFgViSO0nPVjwylLBc1DCHdBduZYkIQyrs/hoqhwHu 4iFeO4w5nuzSb0WatObeyyz+IXqSOU2O/Rq8E3OlT38AJVouHS3NmLYrTPEH5AfTPL38Ys1HEu5DV 3OSms57c9ReSU+NcBMSneefOX9zsq/nnADX1isg+bz5SJTDmYGYqbNQickx1n8vcWHOc5fTal2ack SwWFYkZag==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kqiGa-00058u-Jf; Sat, 19 Dec 2020 19:51:48 +0000 Received: from vps0.lunn.ch ([185.16.172.187]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kqiGX-00058T-FO for linux-arm-kernel@lists.infradead.org; Sat, 19 Dec 2020 19:51:46 +0000 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kqiGL-00CtDB-9X; Sat, 19 Dec 2020 20:51:33 +0100 Date: Sat, 19 Dec 2020 20:51:33 +0100 From: Andrew Lunn To: Steen Hegelund Subject: Re: [RFC PATCH v2 3/8] net: sparx5: add hostmode with phylink support Message-ID: <20201219195133.GD3026679@lunn.ch> References: <20201217075134.919699-1-steen.hegelund@microchip.com> <20201217075134.919699-4-steen.hegelund@microchip.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201217075134.919699-4-steen.hegelund@microchip.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201219_145145_632125_464F7129 X-CRM114-Status: GOOD ( 27.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bjarni Jonasson , Alexandre Belloni , linux-kernel@vger.kernel.org, Arnd Bergmann , Madalin Bucur , netdev@vger.kernel.org, Masahiro Yamada , Russell King , Microchip Linux Driver Support , linux-arm-kernel@lists.infradead.org, Mark Einon , Jakub Kicinski , "David S. Miller" , Lars Povlsen Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > + /* Create a phylink for PHY management. Also handles SFPs */ > + spx5_port->phylink_config.dev = &spx5_port->ndev->dev; > + spx5_port->phylink_config.type = PHYLINK_NETDEV; > + spx5_port->phylink_config.pcs_poll = true; > + > + /* phylink needs a valid interface mode to parse dt node */ > + if (phy_mode == PHY_INTERFACE_MODE_NA) > + phy_mode = PHY_INTERFACE_MODE_10GBASER; Maybe just enforce a valid value in DT? > +/* Configuration */ > +static inline bool sparx5_use_cu_phy(struct sparx5_port *port) > +{ > + return port->conf.phy_mode != PHY_INTERFACE_MODE_NA; > +} That is a rather odd definition of copper. > diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c > new file mode 100644 > index 000000000000..6f9282e9d3f4 > --- /dev/null > +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c > @@ -0,0 +1,203 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* Microchip Sparx5 Switch driver > + * > + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. > + */ > + > +#include "sparx5_main.h" I don't actually know what is preferred here, but very few drivers i've reviewed put all the required headers into another header file. They normally list them in each .c file. > +static int sparx5_port_open(struct net_device *ndev) > +{ > + struct sparx5_port *port = netdev_priv(ndev); > + int err = 0; > + > + err = phylink_of_phy_connect(port->phylink, port->of_node, 0); > + if (err) { > + netdev_err(ndev, "Could not attach to PHY\n"); > + return err; > + } > + > + phylink_start(port->phylink); > + > + if (!ndev->phydev) { Humm. When is ndev->phydev set? I don't think phylink ever sets it. > + /* power up serdes */ > + port->conf.power_down = false; > + err = phy_power_on(port->serdes); > + if (err) > + netdev_err(ndev, "%s failed\n", __func__); > + } > + > + return err; > +} > +struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno) > +{ > + struct net_device *ndev; > + struct sparx5_port *spx5_port; > + > + ndev = devm_alloc_etherdev(sparx5->dev, sizeof(struct sparx5_port)); > + if (!ndev) > + return ERR_PTR(-ENOMEM); > + > + SET_NETDEV_DEV(ndev, sparx5->dev); > + spx5_port = netdev_priv(ndev); > + spx5_port->ndev = ndev; > + spx5_port->sparx5 = sparx5; > + spx5_port->portno = portno; > + sparx5_set_port_ifh(spx5_port->ifh, portno); > + snprintf(ndev->name, IFNAMSIZ, "eth%d", portno); > + > + ether_setup(ndev); devm_alloc_etherdev() should of already called ether_setup(). > + ndev->netdev_ops = &sparx5_port_netdev_ops; > + ndev->features |= NETIF_F_LLTX; /* software tx */ > + > + ether_addr_copy(ndev->dev_addr, sparx5->base_mac); > + ndev->dev_addr[ETH_ALEN - 1] += portno + 1; That will cause some surprises with wrap around. Use eth_addr_inc() > +static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap) > +{ > + int i, byte_cnt = 0; > + bool eof_flag = false, pruned_flag = false, abort_flag = false; > + u32 ifh[IFH_LEN]; > + struct sk_buff *skb; > + struct frame_info fi; > + struct sparx5_port *port; > + struct net_device *netdev; > + u32 *rxbuf; > + > + /* Get IFH */ > + for (i = 0; i < IFH_LEN; i++) > + ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp)); > + > + /* Decode IFH (whats needed) */ > + sparx5_ifh_parse(ifh, &fi); > + > + /* Map to port netdev */ > + port = fi.src_port < SPX5_PORTS ? > + sparx5->ports[fi.src_port] : NULL; > + if (!port || !port->ndev) { > + dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); > + sparx5_xtr_flush(sparx5, grp); > + return; > + } > + > + /* Have netdev, get skb */ > + netdev = port->ndev; > + skb = netdev_alloc_skb(netdev, netdev->mtu + ETH_HLEN); > + if (!skb) { > + sparx5_xtr_flush(sparx5, grp); > + dev_err(sparx5->dev, "No skb allocated\n"); > + return; > + } > + rxbuf = (u32 *)skb->data; > + > + /* Now, pull frame data */ > + while (!eof_flag) { > + u32 val = spx5_rd(sparx5, QS_XTR_RD(grp)); > + u32 cmp = val; > + > + if (byte_swap) > + cmp = ntohl((__force __be32)val); > + > + switch (cmp) { > + case XTR_NOT_READY: > + break; > + case XTR_ABORT: > + /* No accompanying data */ > + abort_flag = true; > + eof_flag = true; > + break; > + case XTR_EOF_0: > + case XTR_EOF_1: > + case XTR_EOF_2: > + case XTR_EOF_3: > + /* This assumes STATUS_WORD_POS == 1, Status > + * just after last data > + */ > + byte_cnt -= (4 - XTR_VALID_BYTES(val)); > + eof_flag = true; > + break; > + case XTR_PRUNED: > + /* But get the last 4 bytes as well */ > + eof_flag = true; > + pruned_flag = true; > + fallthrough; > + case XTR_ESCAPE: > + *rxbuf = spx5_rd(sparx5, QS_XTR_RD(grp)); > + byte_cnt += 4; > + rxbuf++; > + break; > + default: > + *rxbuf = val; > + byte_cnt += 4; > + rxbuf++; > + } > + } > + > + if (abort_flag || pruned_flag || !eof_flag) { > + netdev_err(netdev, "Discarded frame: abort:%d pruned:%d eof:%d\n", > + abort_flag, pruned_flag, eof_flag); > + kfree_skb(skb); > + return; > + } > + > + if (!netif_oper_up(netdev)) { > + netdev_err(netdev, "Discarded frame: Interface not up\n"); > + kfree_skb(skb); > + return; > + } Why is it sending frames when it is not up? > +static int sparx5_inject(struct sparx5 *sparx5, > + u32 *ifh, > + struct sk_buff *skb) > +{ > + u32 val, w, count; > + int grp = INJ_QUEUE; > + u8 *buf; > + > + val = spx5_rd(sparx5, QS_INJ_STATUS); > + if (!(QS_INJ_STATUS_FIFO_RDY_GET(val) & BIT(grp))) { > + pr_err("Injection: Queue not ready: 0x%lx\n", > + QS_INJ_STATUS_FIFO_RDY_GET(val)); > + return -1; Always use -ESOMETHING. > + } > + > + if (QS_INJ_STATUS_WMARK_REACHED_GET(val) & BIT(grp)) { > + pr_err("Injection: Watermark reached: 0x%lx\n", > + QS_INJ_STATUS_WMARK_REACHED_GET(val)); > + return -1; > + } > + > + /* Indicate SOF */ > + spx5_wr(QS_INJ_CTRL_SOF_SET(1) | > + QS_INJ_CTRL_GAP_SIZE_SET(1), > + sparx5, QS_INJ_CTRL(grp)); > + > + // Write the IFH to the chip. > + for (w = 0; w < IFH_LEN; w++) > + spx5_wr(ifh[w], sparx5, QS_INJ_WR(grp)); > + > + /* Write words, round up */ > + count = ((skb->len + 3) / 4); > + buf = skb->data; > + for (w = 0; w < count; w++, buf += 4) { > + val = get_unaligned((const u32 *)buf); > + spx5_wr(val, sparx5, QS_INJ_WR(grp)); > + } No DMA? What sort of performance do you get? Enough for the odd BPDU, IGMP frame etc, but i guess you don't want any real bulk data to be sent this way? > +irqreturn_t sparx5_xtr_handler(int irq, void *_sparx5) > +{ > + struct sparx5 *sparx5 = _sparx5; > + > + /* Check data in queue */ > + while (spx5_rd(sparx5, QS_XTR_DATA_PRESENT) & BIT(XTR_QUEUE)) > + sparx5_xtr_grp(sparx5, XTR_QUEUE, false); > + > + return IRQ_HANDLED; > +} Is there any sort of limit how many times this will loop? If somebody is blasting 10Gbps at the CPU, will it ever get out of this loop? Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel