From mboxrd@z Thu Jan 1 00:00:00 1970 From: Siew Chin Lim Date: Tue, 22 Dec 2020 00:49:33 +0800 Subject: [v5 09/18] mmc: dwmmc: socfpga: Add ATF support for MMC driver In-Reply-To: <20201221164942.11640-1-elly.siew.chin.lim@intel.com> References: <20201221164942.11640-1-elly.siew.chin.lim@intel.com> Message-ID: <20201221164942.11640-10-elly.siew.chin.lim@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Chee Hong Ang In non-secure mode (EL2), MMC driver calls the SMC/PSCI services provided by ATF to set SDMMC's DRVSEL and SMPLSEL. Signed-off-by: Chee Hong Ang Signed-off-by: Siew Chin Lim --- v5 --- Call secure register access helper function to write the secure register. Return error if fail to write the secure register. --- drivers/mmc/socfpga_dw_mmc.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 0a2845bcc2..7a485b492d 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -13,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -58,10 +60,22 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + int ret; + + ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC, + sdmmc_mask); + if (ret) { + printf("DWMMC: Failed to set clksel via SMC call"); + return ret; + } +#else writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC); debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); +#endif /* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, -- 2.13.0