From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: wsa@the-dreams.de, geert@linux-m68k.org, hoai.luu.ub@renesas.com,
Ulrich Hecht <uli+renesas@fpond.eu>
Subject: [PATCH v2 1/5] pinctrl: renesas: implement unlock register masks
Date: Mon, 21 Dec 2020 17:54:44 +0100 [thread overview]
Message-ID: <20201221165448.27312-2-uli+renesas@fpond.eu> (raw)
In-Reply-To: <20201221165448.27312-1-uli+renesas@fpond.eu>
The V3U SoC has several unlock registers, one per register group. They
reside at offset zero in each 0x200 bytes-sized block.
To avoid adding yet another table to the PFC implementation, this
patch adds the option to specify an address mask instead of the fixed
address in sh_pfc_soc_info::unlock_reg.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
drivers/pinctrl/renesas/core.c | 28 ++++++++++++++++++----------
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c
index 2cc457279345..4cd95e220900 100644
--- a/drivers/pinctrl/renesas/core.c
+++ b/drivers/pinctrl/renesas/core.c
@@ -175,13 +175,25 @@ u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
}
-void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
+static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
{
- if (pfc->info->unlock_reg)
- sh_pfc_write_raw_reg(
- sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
- ~data);
+ u32 unlock;
+
+ if (!pfc->info->unlock_reg)
+ return;
+ if (pfc->info->unlock_reg >= 0x80000000UL)
+ unlock = pfc->info->unlock_reg;
+ else
+ /* unlock_reg is a mask */
+ unlock = reg & ~pfc->info->unlock_reg;
+
+ sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data);
+}
+
+void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
+{
+ sh_pfc_unlock_reg(pfc, reg, data);
sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
}
@@ -227,11 +239,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
data &= mask;
data |= value;
- if (pfc->info->unlock_reg)
- sh_pfc_write_raw_reg(
- sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
- ~data);
-
+ sh_pfc_unlock_reg(pfc, crp->reg, data);
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
--
2.20.1
next prev parent reply other threads:[~2020-12-21 16:58 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-21 16:54 [PATCH v2 0/5] pinctrl: renesas: basic R8A779A0 (V3U) support Ulrich Hecht
2020-12-21 16:54 ` Ulrich Hecht [this message]
2020-12-22 10:31 ` [PATCH v2 1/5] pinctrl: renesas: implement unlock register masks Geert Uytterhoeven
2020-12-21 16:54 ` [PATCH v2 2/5] pinctrl: renesas: add I/O voltage level flag Ulrich Hecht
2020-12-22 10:45 ` Geert Uytterhoeven
2020-12-22 16:47 ` Ulrich Hecht
2020-12-22 18:44 ` Geert Uytterhoeven
2020-12-22 11:44 ` Geert Uytterhoeven
2020-12-22 16:47 ` Ulrich Hecht
2020-12-21 16:54 ` [PATCH v2 3/5] pinctrl: renesas: add PORT_GP_CFG_{2,31} macros Ulrich Hecht
2020-12-22 10:35 ` Geert Uytterhoeven
2020-12-21 16:54 ` [PATCH v2 5/5] pinctrl: renesas: r8a779a0: Add SCIF pins, groups and functions Ulrich Hecht
2020-12-22 10:05 ` Geert Uytterhoeven
2020-12-28 12:17 ` Wolfram Sang
[not found] ` <20201221165448.27312-5-uli+renesas@fpond.eu>
2020-12-22 11:42 ` [PATCH v2 4/5] pinctrl: renesas: Initial R8A779A0 (V3U) PFC support Geert Uytterhoeven
2021-01-12 16:58 ` Ulrich Hecht
2020-12-27 20:27 ` Wolfram Sang
2020-12-23 15:59 ` [PATCH v2 0/5] pinctrl: renesas: basic R8A779A0 (V3U) support Wolfram Sang
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