From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02A97C433E0 for ; Wed, 23 Dec 2020 09:13:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 646DD207A2 for ; Wed, 23 Dec 2020 09:13:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 646DD207A2 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:43434 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ks0Cd-0006eu-CI for qemu-devel@archiver.kernel.org; Wed, 23 Dec 2020 04:13:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52756) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks0Av-0004l2-Nd for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:11:17 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:3007) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ks0Aq-0002Xq-Tj for qemu-devel@nongnu.org; Wed, 23 Dec 2020 04:11:17 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4D16pN1Xl9zhwSf; Wed, 23 Dec 2020 17:09:16 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.498.0; Wed, 23 Dec 2020 17:09:52 +0800 From: Jiahui Cen To: Subject: [PATCH v3 2/8] acpi: Add addr offset in build_crs Date: Wed, 23 Dec 2020 17:08:30 +0800 Message-ID: <20201223090836.9075-3-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201223090836.9075-1-cenjiahui@huawei.com> References: <20201223090836.9075-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=cenjiahui@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Jiahui Cen , Eduardo Habkost , "Michael S. Tsirkin" , Ard Biesheuvel , Richard Henderson , Paolo Bonzini , Igor Mammedov , Laszlo Ersek , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" AML needs Address Translation offset to describe how a bridge translates addresses accross the bridge when using an address descriptor, and especially on ARM, the translation offset of pio resource is usually non zero. Therefore, it's necessary to pass offset for pio, mmio32, mmio64 and bus number into build_crs. Signed-off-by: Jiahui Cen --- hw/acpi/aml-build.c | 18 ++++++++++-------- hw/i386/acpi-build.c | 3 ++- hw/pci-host/gpex-acpi.c | 3 ++- include/hw/acpi/aml-build.h | 4 +++- 4 files changed, 17 insertions(+), 11 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index f976aa667b..7b6ebb0cc8 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2076,7 +2076,9 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL, NULL); } -Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) +Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, + uint32_t mmio32_offset, uint64_t mmio64_offset, + uint16_t bus_nr_offset) { Aml *crs = aml_resource_template(); CrsRangeSet temp_range_set; @@ -2189,10 +2191,10 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) for (i = 0; i < temp_range_set.io_ranges->len; i++) { entry = g_ptr_array_index(temp_range_set.io_ranges, i); aml_append(crs, - aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, - AML_POS_DECODE, AML_ENTIRE_RANGE, - 0, entry->base, entry->limit, 0, - entry->limit - entry->base + 1)); + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0, entry->base, entry->limit, io_offset, + entry->limit - entry->base + 1)); crs_range_insert(range_set->io_ranges, entry->base, entry->limit); } @@ -2205,7 +2207,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, - 0, entry->base, entry->limit, 0, + 0, entry->base, entry->limit, mmio32_offset, entry->limit - entry->base + 1)); crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); } @@ -2217,7 +2219,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, - 0, entry->base, entry->limit, 0, + 0, entry->base, entry->limit, mmio64_offset, entry->limit - entry->base + 1)); crs_range_insert(range_set->mem_64bit_ranges, entry->base, entry->limit); @@ -2230,7 +2232,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) 0, pci_bus_num(host->bus), max_bus, - 0, + bus_nr_offset, max_bus - pci_bus_num(host->bus) + 1)); return crs; diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index f18b71dea9..f56d699c7f 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1360,7 +1360,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } aml_append(dev, build_prt(false)); - crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, + 0, 0, 0, 0); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); aml_append(dsdt, scope); diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 7f20ee1c98..11b3db8f71 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -168,7 +168,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) * 1. The resources the pci-brige/pcie-root-port need. * 2. The resources the devices behind pxb need. */ - crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set); + crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, + cfg->pio.base, 0, 0, 0); aml_append(dev, aml_name_decl("_CRS", crs)); acpi_dsdt_add_pci_osc(dev); diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index e727bea1bc..54a5aec4d7 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -452,7 +452,9 @@ void crs_replace_with_free_ranges(GPtrArray *ranges, void crs_range_set_init(CrsRangeSet *range_set); void crs_range_set_free(CrsRangeSet *range_set); -Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set); +Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, + uint32_t mmio32_offset, uint64_t mmio64_offset, + uint16_t bus_nr_offset); void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, uint64_t len, int node, MemoryAffinityFlags flags); -- 2.29.2