From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1570C433E0 for ; Wed, 23 Dec 2020 16:34:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7C1632226A for ; Wed, 23 Dec 2020 16:34:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725988AbgLWQeX (ORCPT ); Wed, 23 Dec 2020 11:34:23 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:10493 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725785AbgLWQeW (ORCPT ); Wed, 23 Dec 2020 11:34:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1608741262; x=1640277262; h=from:to:cc:subject:date:message-id:mime-version; bh=h1uU/xZB+u65R9PycjaTtcUTsDJER2E6v6lRjGcr7MY=; b=BVwbE267a1p/y1SrZLus0qaBJuY0VulufgTMIni6buwrw6+bxkHrrPQv A/CazTIk3KOhXCL1hnNBsQFMSDtOUrP0qW4ylr/e7dznGIuRvtFUbQorA qzmDyxE7VEju5JMdryW5bzwJVdOwMZIITc9qjsu09YpxrvNhuU7VF07BM 7D15558H6EVunocHIZRSAbQC4/APo7hmzqyWpJxIK6UGAU3PFgtEDLibg UPWeeS8GzsMZdbbbURSFzpfUT4aSmOD+Y3HvnE18AnEzIcSR5ncDyQSGE Er+RDYTDdIT6aOHPJvG8MbDLANWfJs2qIshPdxK42TuhdD3eHzQzrPQ8U w==; IronPort-SDR: oh4ujwtW0+2ocjPCLo+sBsWgV7rQeYWKTsmjw3cPi2gPsVn361FffOmr+D6Whuw8TlodKwcVb0 hgZk+Dl2pxIYGCET6DDNaIOiaVFMgwSCeVS792woC7SBNAcuco4CfXaE3VfqwmGE/HUQX/svGq ov0ns3IFfSTb/WmsS7WQ1OAGn4I21LfIDo0xeybb0ZTeXQzk74Q4AtpRuOch4s6wzdB2ObC6G4 sTMXVWXumOyi+29LoOnSyVoEgeTQXCu/rHkrWfgDD14Z0fxjFeWZJ5EtkeURZlXYC/wV79WcfE Yv0= X-IronPort-AV: E=Sophos;i="5.78,441,1599548400"; d="scan'208";a="108748448" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Dec 2020 09:33:06 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 23 Dec 2020 09:33:06 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 23 Dec 2020 09:33:03 -0700 From: To: , , , , , , , CC: , , , , , , , Conor Dooley Subject: [PATCH v3 2/5] dt-bindings: add bindings for polarfire soc mailbox Date: Wed, 23 Dec 2020 16:33:02 +0000 Message-ID: <20201223163302.29057-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add device tree bindings for the MSS system controller mailbox on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../mailbox/microchip,mailbox-mpfs.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml new file mode 100644 index 000000000000..c5b126c6fb66 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/microchip,mailbox-mpfs.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip PolarFire SoC (MPFS) mss mailbox controller + +maintainers: + - Conor Dooley + +properties: + compatible: + const: microchip,polarfire-soc-mailbox + + reg: + items: + - description: mailbox data registers + - description: mailbox int registers + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + mbox: mailbox@37020000 { + compatible = "microchip,polarfire-soc-mailbox"; + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>; + interrupt-parent = <&L1>; + interrupts = <96>; + #mbox-cells = <1>; + }; + }; -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2487DC433E0 for ; Wed, 23 Dec 2020 16:33:18 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1D59D2229C for ; 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d="scan'208";a="108748448" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Dec 2020 09:33:06 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 23 Dec 2020 09:33:06 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Wed, 23 Dec 2020 09:33:03 -0700 From: To: , , , , , , , Subject: [PATCH v3 2/5] dt-bindings: add bindings for polarfire soc mailbox Date: Wed, 23 Dec 2020 16:33:02 +0000 Message-ID: <20201223163302.29057-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201223_113308_036392_FBACE952 X-CRM114-Status: GOOD ( 10.44 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cyril.jean@microchip.com, david.abdurachmanov@gmail.com, daire.mcnamara@microchip.com, anup.patel@wdc.com, j.neuschaefer@gmx.net, atish.patra@wdc.com, Conor Dooley , lewis.hanly@microchip.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Add device tree bindings for the MSS system controller mailbox on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley --- .../mailbox/microchip,mailbox-mpfs.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml new file mode 100644 index 000000000000..c5b126c6fb66 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/microchip,mailbox-mpfs.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/microchip,mailbox-mpfs.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip PolarFire SoC (MPFS) mss mailbox controller + +maintainers: + - Conor Dooley + +properties: + compatible: + const: microchip,polarfire-soc-mailbox + + reg: + items: + - description: mailbox data registers + - description: mailbox int registers + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + mbox: mailbox@37020000 { + compatible = "microchip,polarfire-soc-mailbox"; + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>; + interrupt-parent = <&L1>; + interrupts = <96>; + #mbox-cells = <1>; + }; + }; -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv