* [PATCH v7 00/28] Add DM support for omap PWM backlight
@ 2020-12-24 7:25 Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 01/28] clk: export generic routines Dario Binacchi
` (12 more replies)
0 siblings, 13 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
The series was born from the need to manage the PWM backlight of the
display connected to my beaglebone board. To hit the target, I had to
develop drivers for PWM management which in turn relied on drivers for
managing timers and clocks, all developed according to the driver model.
My intention was to use the SoC-specific API only at strictly necessary
points in the code. My previous patches for migrating the AM335x display
driver to the driver model had required the implementation of additional
functions outside the concerns of the driver, (settings for dividing the
pixel clock rate, configuring the display DPLL rate, ....) not being
able to use the API of the related clock drivers. This series shouldn't
have repeated the same kind of mistake. Furthermore, I also wanted to fix
that kind of forced choice. Almost everything should have been accessible
via the driver model API. In the series there are also some patches that
could be submitted separately, but which I have however inserted to avoid
applying future patches to incorporate them.
With this last consideration, I hope I have convincingly justified the
large number of patches in the series.
The patch enabling address translation into a CPU physical address from
device-tree even in case of crossing levels with #size-cells = <0>, is
crucial for the series. The previous implementation was unable to
perform the address translation required by the am33xx device tree.
I tried to apply in a conservative way as few changes as possible and
to verify the execution of all the tests already developed, as well as
the new ones I added for the new feature.
The patch series can be cleanly applied to the HEAD of the master which
at the time of release points to c15f44acf9 commit.
Changes in v7:
- Not all OMAP2 platform need CONFIG_TI_SYSC.
Set CONFIG_TI_SYSC as imply and disable it to fix building errors in:
nokia_rx51_defconfig
cm_t335_defconfig
- Add gd_size_cells_0 macro to fix building errors for boards that do
not use CONFIG_DM.
- Add dm8168-evm-u-boot.dtsi to fix building errors for
ti816x_evm_defconfig.
- Add linux/err.h header in am335x-fb.c to fix building errors for
brxre1_defconfig.
- Fix building errors for:
brppt1_mmc_defconfig
brppt1_nand_defconfig
brppt1_spi_defconfig
brxre1_defconfig
brsmarc1_defconfig
Changes in v6:
- Remove the 'am3-prcm' driver.
- Add the 'simple-bus' compatible string to the prcm_clocks node.
- Remove the 'am3-scm' driver.
- Add the 'simple-bus' compatible string to the scm_clocks node.
Changes in v5:
- Create drivers/clk/ti directory.
- Move the clk-ti-mux.c file to drivers/clk/ti and rename it clk-mux.c
- Move the clk-ti-am3-dpll.c file to drivers/clk/ti with the name
clk-am3-dpll.c.
- Move the clk-ti-am3-dpll-x2.c file to drivers/clk/ti with the name
clk-am3-dpll-x2.c.
- Move the clk-ti.c file to drivers/clk/ti with the name clk.c.
- Move the clk-ti.h file to drivers/clk/ti with the name clk.h.
- Move the clk-ti-divider.c file to drivers/clk/ti with the name
clk-divider.c.
- Move the clk-ti-gate.c file to drivers/clk/ti with the name
clk-gate.c.
- Move the clk-ti-ctrl.c file to drivers/clk/ti with the name
clk-ctrl.c.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
- Remove a blank line at end of file arch/arm/dts/am33xx-l4.dtsi.
- Update clk_round_rate description.
- Add Sean Anderson review.
- Include device_compat.h header for dev_xxx macros.
- Include device_compat.h header for dev_xxx macros.
- Fix compilation errors on the dev parameter of the dev_xx macros.
- Include device_compat.h header for dev_xxx macros.
- Fix compilation errors on the dev parameter of the dev_xx macros.
- Include device_compat.h header for dev_xxx macros.
- Include device_compat.h header for dev_xxx macros.
- Fix compilation errors on the dev parameter of the dev_xx macros.
- Include device_compat.h header for dev_xxx macros.
- Add Sphinx documentation for dm_flags.
- Convert GD_DM_FLG_* to enum.
- Include device_compat.h header in test/dm/test-fdt.c for dev_xxx macros.
- Include device_compat.h header for dev_xxx macros.
- Include device_compat.h header for dev_xxx macros.
- Include device_compat.h header for dev_xxx macros.
- Add Simon Glass review.
- Include device_compat.h header for dev_xxx macros.
Changes in v3:
- Remove doc/device-tree-bindings/clock/clock-bindings.txt.
- Remove doc/device-tree-bindings/clock/ti,mux.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
- Remove doc/device-tree-bindings/clock/ti,dpll.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
- Remove doc/device-tree-bindings/clock/ti,autoidle.txt.
- Remove doc/device-tree-bindings/clock/ti,divider.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
- Remove doc/device-tree-bindings/clock/gpio-gate-clock.txt.
- Remove doc/device-tree-bindings/clock/ti,clockdomain.txt.
- Remove doc/device-tree-bindings/clock/ti,gate.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
- Fix access to registers listed by device tree following resync of
am33xx-clock.dtsi with Linux 5.9-rc7.
- Remove doc/device-tree-bindings/clock/ti,clkctrl.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
- doc/device-tree-bindings/arm/omap,prcm.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
- Add to commit message the references to linux kernel dt binding
documentation.
- Comment dm_flags field in the global_data structure.
- Remove doc/device-tree-bindings/arm/omap,ctrl.txt.
- Remove doc/device-tree-bindings/pinctrl/pinctrl-single.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
- Adds PWM_TI_EHRPWM dependency on ARCH_OMAP2PLUS in Kconfig.
- Add error message in case of invalid address.
- Remove doc/device-tree-bindings/pwm/ti,ehrpwm.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
- Move Kconfig symbol from drivers/pwm to drivers/bus.
- Remove the domain clock reference from the pwmss nodes of the device
tree in am33xx.dtsi. The resync of am33xx.dtsi with Linux 5.9-rc7
already contains such references.
- Remove domain clock enabling/disabling. Enabling the domain clock is
performed by the sysc interconnect target module driver during the pwm
device probing.
- Remove doc/device-tree-bindings/pwm/ti,pwmss.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
- Update the DTS lcdc node of the am335x boards because of the
am33xx.dtsi resynced with Linux 5.9-rc7.
- Remove clock domain enabling/disabling.
- Update the commit message.
- Add clk.h header.
- Fix an error code returned by the probe function.
Changes in v2:
- Add the clk_ prefix to the divider functions.
- Add kernel-doc comments to the exported functions.
- Merged to patch [09/31] clk: ti: refactor mux and divider clock
drivers.
- Remove the 'ti_am3_prcm_clocks' driver. Handle 'prcm_clocks' node in
the 'ti_am3_prcm' driver.
- Update the commit message.
- Fix a missing line in the commit message.
- Add dm_flags to global_data structure and GD_DM_FLG_SIZE_CELLS_0 macro
to test without recompiling.
- Update the OF_CHECK_COUNTS macro in order to have just one
#define by bringing the GD_DM_FLG_SIZE_CELLS_0 into the expression.
- Lower-case the 0xC019 hex number.
- Remove the 'ti_am3_scm_clocks' driver. Handle 'scm_clocks' node in
the 'ti_am3_scm' driver.
- Update the commit message.
Dario Binacchi (28):
clk: export generic routines
dt-bindings: bus: ti-sysc: resync with Linux 5.9-rc7
bus: ti: add minimal sysc interconnect target driver
arm: dts: sync am33xx with Linux 5.9-rc7
clk: add clk_round_rate()
clk: ti: add mux clock driver
arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macro
clk: ti: am33xx: add DPLL clock drivers
clk: ti: add divider clock driver
clk: ti: add gate clock driver
arm: dts: am335x: include am33xx-u-boot.dtsi
ti: am33xx: fix do_enable_clocks() to accept NULL parameters
clk: ti: add support for clkctrl clocks
clk: ti: omap4: add clock manager driver
arm: dts: am335x: enable prcm_clocks auto binding
clk: move clk-ti-sci driver to 'ti' directory
fdt: translate address if #size-cells = <0>
omap: timer: fix the rate setting
arm: dts: am335x: enable scm_clocks auto binding
pwm: ti: am33xx: add enhanced pwm driver
bus: ti: am33xx: add pwm subsystem driver
dm: core: add a function to decode display timings
video: omap: add panel driver
video: omap: drop domain clock enabling by SOC api
video: omap: set LCD clock rate through DM API
video: omap: split the legacy code from the DM code
video: omap: move drivers to 'ti' directory
board: ti: am335x-ice: get CDCE913 clock device
arch/arm/Kconfig | 1 +
arch/arm/dts/am335x-brppt1-mmc.dts | 17 +-
arch/arm/dts/am335x-brppt1-nand.dts | 17 +-
arch/arm/dts/am335x-brppt1-spi.dts | 17 +-
arch/arm/dts/am335x-brsmarc1.dts | 20 +-
arch/arm/dts/am335x-brxre1.dts | 21 +-
arch/arm/dts/am335x-chiliboard-u-boot.dtsi | 2 +
arch/arm/dts/am335x-draco.dtsi | 11 +-
arch/arm/dts/am335x-evm-u-boot.dtsi | 17 +-
arch/arm/dts/am335x-evm.dts | 2 +-
arch/arm/dts/am335x-evmsk-u-boot.dtsi | 16 +-
arch/arm/dts/am335x-evmsk.dts | 2 +-
arch/arm/dts/am335x-guardian-u-boot.dtsi | 25 +-
arch/arm/dts/am335x-icev2-u-boot.dtsi | 3 +
arch/arm/dts/am335x-pdu001-u-boot.dtsi | 20 +-
arch/arm/dts/am335x-pxm2.dtsi | 2 +-
arch/arm/dts/am335x-pxm50-u-boot.dtsi | 16 +-
arch/arm/dts/am335x-regor-rdk-u-boot.dtsi | 2 +
arch/arm/dts/am335x-rut-u-boot.dtsi | 16 +-
arch/arm/dts/am335x-rut.dts | 2 +-
arch/arm/dts/am335x-shc-u-boot.dtsi | 2 +
arch/arm/dts/am335x-shc.dts | 2 +-
arch/arm/dts/am335x-wega-rdk-u-boot.dtsi | 2 +
arch/arm/dts/am33xx-clocks.dtsi | 106 +-
arch/arm/dts/am33xx-l4.dtsi | 1962 ++++++++++++++++++++
arch/arm/dts/am33xx-u-boot.dtsi | 8 +
arch/arm/dts/am33xx.dtsi | 721 +++----
arch/arm/dts/da850-evm-u-boot.dtsi | 18 +-
arch/arm/dts/dm8168-evm-u-boot.dtsi | 12 +
arch/arm/include/asm/arch-am33xx/clock.h | 1 +
arch/arm/mach-omap2/am33xx/clock.c | 10 +-
arch/arm/mach-omap2/am33xx/clock_am33xx.c | 2 +-
arch/sandbox/dts/test.dts | 67 +
arch/sandbox/include/asm/clk.h | 9 +
board/BuR/common/bur_common.h | 2 +-
board/BuR/common/common.c | 2 +-
board/ti/am335x/board.c | 2 +-
board/ti/am43xx/board.c | 2 +-
common/fdt_support.c | 6 +-
configs/cm_t335_defconfig | 1 +
configs/nokia_rx51_defconfig | 1 +
drivers/bus/Kconfig | 13 +
drivers/bus/Makefile | 2 +
drivers/bus/ti-pwmss.c | 21 +
drivers/bus/ti-sysc.c | 166 ++
drivers/clk/Kconfig | 9 +-
drivers/clk/Makefile | 2 +-
drivers/clk/clk-divider.c | 24 +-
drivers/clk/clk-uclass.c | 15 +
drivers/clk/clk_sandbox.c | 17 +
drivers/clk/clk_sandbox_test.c | 10 +
drivers/clk/ti/Kconfig | 43 +
drivers/clk/ti/Makefile | 13 +
drivers/clk/ti/clk-am3-dpll-x2.c | 79 +
drivers/clk/ti/clk-am3-dpll.c | 268 +++
drivers/clk/ti/clk-ctrl.c | 154 ++
drivers/clk/ti/clk-divider.c | 381 ++++
drivers/clk/ti/clk-gate.c | 93 +
drivers/clk/ti/clk-mux.c | 253 +++
drivers/clk/{clk-ti-sci.c => ti/clk-sci.c} | 0
drivers/clk/ti/clk.c | 34 +
drivers/clk/ti/clk.h | 13 +
drivers/clk/ti/omap4-cm.c | 22 +
drivers/core/Kconfig | 12 +
drivers/core/fdtaddr.c | 2 +-
drivers/core/of_addr.c | 13 +-
drivers/core/ofnode.c | 7 +-
drivers/core/read.c | 6 +
drivers/core/root.c | 3 +
drivers/pwm/Kconfig | 7 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-ti-ehrpwm.c | 468 +++++
drivers/timer/omap-timer.c | 6 +-
drivers/video/Kconfig | 5 +-
drivers/video/Makefile | 2 +-
drivers/video/ti/Kconfig | 8 +
drivers/video/ti/Makefile | 10 +
drivers/video/{ => ti}/am335x-fb.c | 341 +---
drivers/video/{ => ti}/am335x-fb.h | 4 -
drivers/video/ti/tilcdc-panel.c | 172 ++
drivers/video/ti/tilcdc-panel.h | 14 +
drivers/video/ti/tilcdc.c | 425 +++++
drivers/video/ti/tilcdc.h | 38 +
include/asm-generic/global_data.h | 24 +
include/clk-uclass.h | 8 +
include/clk.h | 28 +
include/dm/read.h | 24 +
include/dt-bindings/bus/ti-sysc.h | 6 +
include/linux/clk-provider.h | 57 +
test/dm/clk.c | 22 +
test/dm/test-fdt.c | 149 +-
91 files changed, 5691 insertions(+), 970 deletions(-)
create mode 100644 arch/arm/dts/am33xx-l4.dtsi
create mode 100644 arch/arm/dts/dm8168-evm-u-boot.dtsi
create mode 100644 drivers/bus/ti-pwmss.c
create mode 100644 drivers/bus/ti-sysc.c
create mode 100644 drivers/clk/ti/Kconfig
create mode 100644 drivers/clk/ti/Makefile
create mode 100644 drivers/clk/ti/clk-am3-dpll-x2.c
create mode 100644 drivers/clk/ti/clk-am3-dpll.c
create mode 100644 drivers/clk/ti/clk-ctrl.c
create mode 100644 drivers/clk/ti/clk-divider.c
create mode 100644 drivers/clk/ti/clk-gate.c
create mode 100644 drivers/clk/ti/clk-mux.c
rename drivers/clk/{clk-ti-sci.c => ti/clk-sci.c} (100%)
create mode 100644 drivers/clk/ti/clk.c
create mode 100644 drivers/clk/ti/clk.h
create mode 100644 drivers/clk/ti/omap4-cm.c
create mode 100644 drivers/pwm/pwm-ti-ehrpwm.c
create mode 100644 drivers/video/ti/Kconfig
create mode 100644 drivers/video/ti/Makefile
rename drivers/video/{ => ti}/am335x-fb.c (54%)
rename drivers/video/{ => ti}/am335x-fb.h (97%)
create mode 100644 drivers/video/ti/tilcdc-panel.c
create mode 100644 drivers/video/ti/tilcdc-panel.h
create mode 100644 drivers/video/ti/tilcdc.c
create mode 100644 drivers/video/ti/tilcdc.h
--
2.17.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v7 01/28] clk: export generic routines
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 02/28] dt-bindings: bus: ti-sysc: resync with Linux 5.9-rc7 Dario Binacchi
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
Export routines that can be used by other drivers avoiding duplicating
code.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
(no changes since v2)
Changes in v2:
- Add the clk_ prefix to the divider functions.
- Add kernel-doc comments to the exported functions.
drivers/clk/clk-divider.c | 24 +++++++--------
include/linux/clk-provider.h | 57 ++++++++++++++++++++++++++++++++++++
2 files changed, 69 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8f59d7fb72..9df50a5e72 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -28,8 +28,8 @@
#define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
-static unsigned int _get_table_div(const struct clk_div_table *table,
- unsigned int val)
+unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
+ unsigned int val)
{
const struct clk_div_table *clkt;
@@ -49,7 +49,7 @@ static unsigned int _get_div(const struct clk_div_table *table,
if (flags & CLK_DIVIDER_MAX_AT_ZERO)
return val ? val : clk_div_mask(width) + 1;
if (table)
- return _get_table_div(table, val);
+ return clk_divider_get_table_div(table, val);
return val + 1;
}
@@ -89,8 +89,8 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
divider->flags, divider->width);
}
-static bool _is_valid_table_div(const struct clk_div_table *table,
- unsigned int div)
+bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
+ unsigned int div)
{
const struct clk_div_table *clkt;
@@ -100,18 +100,18 @@ static bool _is_valid_table_div(const struct clk_div_table *table,
return false;
}
-static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
- unsigned long flags)
+bool clk_divider_is_valid_div(const struct clk_div_table *table,
+ unsigned int div, unsigned long flags)
{
if (flags & CLK_DIVIDER_POWER_OF_TWO)
return is_power_of_2(div);
if (table)
- return _is_valid_table_div(table, div);
+ return clk_divider_is_valid_table_div(table, div);
return true;
}
-static unsigned int _get_table_val(const struct clk_div_table *table,
- unsigned int div)
+unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
+ unsigned int div)
{
const struct clk_div_table *clkt;
@@ -131,7 +131,7 @@ static unsigned int _get_val(const struct clk_div_table *table,
if (flags & CLK_DIVIDER_MAX_AT_ZERO)
return (div == clk_div_mask(width) + 1) ? 0 : div;
if (table)
- return _get_table_val(table, div);
+ return clk_divider_get_table_val(table, div);
return div - 1;
}
int divider_get_val(unsigned long rate, unsigned long parent_rate,
@@ -142,7 +142,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
- if (!_is_valid_div(table, div, flags))
+ if (!clk_divider_is_valid_div(table, div, flags))
return -EINVAL;
value = _get_val(table, div, flags, width);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 79dce8f0ad..a94539037a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -76,6 +76,19 @@ struct clk_mux {
extern const struct clk_ops clk_mux_ops;
u8 clk_mux_get_parent(struct clk *clk);
+/**
+ * clk_mux_index_to_val() - Convert the parent index to the register value
+ *
+ * It returns the value to write in the hardware register to output the selected
+ * input clock parent.
+ *
+ * @table: array of register values corresponding to the parent index (optional)
+ * @flags: hardware-specific flags
+ * @index: parent clock index
+ * @return the register value
+ */
+unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
+
struct clk_gate {
struct clk clk;
void __iomem *reg;
@@ -125,6 +138,50 @@ struct clk_divider {
#define CLK_DIVIDER_READ_ONLY BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
extern const struct clk_ops clk_divider_ops;
+
+/**
+ * clk_divider_get_table_div() - convert the register value to the divider
+ *
+ * @table: array of register values corresponding to valid dividers
+ * @val: value to convert
+ * @return the divider
+ */
+unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
+ unsigned int val);
+
+/**
+ * clk_divider_get_table_val() - convert the divider to the register value
+ *
+ * It returns the value to write in the hardware register to divide the input
+ * clock rate by @div.
+ *
+ * @table: array of register values corresponding to valid dividers
+ * @div: requested divider
+ * @return the register value
+ */
+unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
+ unsigned int div);
+
+/**
+ * clk_divider_is_valid_div() - check if the divider is valid
+ *
+ * @table: array of valid dividers (optional)
+ * @div: divider to check
+ * @flags: hardware-specific flags
+ * @return true if the divider is valid, false otherwise
+ */
+bool clk_divider_is_valid_div(const struct clk_div_table *table,
+ unsigned int div, unsigned long flags);
+
+/**
+ * clk_divider_is_valid_table_div - check if the divider is in the @table array
+ *
+ * @table: array of valid dividers
+ * @div: divider to check
+ * @return true if the divider is found in the @table array, false otherwise
+ */
+bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
+ unsigned int div);
unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
unsigned int val,
const struct clk_div_table *table,
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 02/28] dt-bindings: bus: ti-sysc: resync with Linux 5.9-rc7
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 01/28] clk: export generic routines Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 03/28] bus: ti: add minimal sysc interconnect target driver Dario Binacchi
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
Add support for PRUSS SYSC type:
The PRUSS module has a SYSCFG which is unique. The SYSCFG has two
additional unique fields called STANDBY_INIT and SUB_MWAIT in addition
to regular IDLE_MODE and STANDBY_MODE fields. Add the bindings for this
new sysc type.
Add support for MCAN on dra76x:
The dra76x MCAN generic interconnect module has a its own format for the
bits in the control registers.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
---
(no changes since v1)
include/dt-bindings/bus/ti-sysc.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h
index 2c005376ac..eae4274543 100644
--- a/include/dt-bindings/bus/ti-sysc.h
+++ b/include/dt-bindings/bus/ti-sysc.h
@@ -15,6 +15,12 @@
/* SmartReflex sysc found on 36xx and later */
#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26)
+#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4)
+
+/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */
+#define SYSC_PRUSS_SUB_MWAIT (1 << 5)
+#define SYSC_PRUSS_STANDBY_INIT (1 << 4)
+
/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
#define SYSC_IDLE_FORCE 0
#define SYSC_IDLE_NO 1
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 03/28] bus: ti: add minimal sysc interconnect target driver
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 01/28] clk: export generic routines Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 02/28] dt-bindings: bus: ti-sysc: resync with Linux 5.9-rc7 Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 04/28] arm: dts: sync am33xx with Linux 5.9-rc7 Dario Binacchi
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
We can handle the sysc interconnect target module in a generic way for
many TI SoCs. Initially let's just enable domain clocks before the
children are probed.
The code is loosely based on the drivers/bus/ti-sysc.c of the Linux
kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/bus/ti-sysc.txt
Signed-off-by: Dario Binacchi <dariobin@libero.it>
---
Changes in v7:
- Not all OMAP2 platform need CONFIG_TI_SYSC.
Set CONFIG_TI_SYSC as imply and disable it to fix building errors in:
nokia_rx51_defconfig
cm_t335_defconfig
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
arch/arm/Kconfig | 1 +
configs/cm_t335_defconfig | 1 +
configs/nokia_rx51_defconfig | 1 +
drivers/bus/Kconfig | 7 ++
drivers/bus/Makefile | 1 +
drivers/bus/ti-sysc.c | 166 +++++++++++++++++++++++++++++++++++
6 files changed, 177 insertions(+)
create mode 100644 drivers/bus/ti-sysc.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fbe90875ae..6f039f7909 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -799,6 +799,7 @@ config ARCH_OMAP2PLUS
select SPL_BOARD_INIT if SPL
select SPL_STACK_R if SPL
select SUPPORT_SPL
+ imply TI_SYSC
imply FIT
config ARCH_MESON
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 3112915dc1..c4fd56b673 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
+# CONFIG_TI_SYSC is not set
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index d0c8929525..30a02e2bc3 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -4,6 +4,7 @@ CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NOKIA_RX51=y
+# CONFIG_TI_SYSC is not set
# CONFIG_FIT is not set
CONFIG_BOOTDELAY=30
CONFIG_AUTOBOOT_KEYED=y
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 07a33c6287..733bec5a56 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -5,6 +5,13 @@
menu "Bus devices"
+config TI_SYSC
+ bool "TI sysc interconnect target module driver"
+ depends on ARCH_OMAP2PLUS
+ help
+ Generic driver for Texas Instruments interconnect target module
+ found on many TI SoCs.
+
config UNIPHIER_SYSTEM_BUS
bool "UniPhier System Bus driver"
depends on ARCH_UNIPHIER
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 0b97fc1f8b..875bb4ed42 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -3,4 +3,5 @@
# Makefile for the bus drivers.
#
+obj-$(CONFIG_TI_SYSC) += ti-sysc.o
obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
new file mode 100644
index 0000000000..65974a70a6
--- /dev/null
+++ b/drivers/bus/ti-sysc.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments sysc interconnect target driver
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+
+enum ti_sysc_clocks {
+ TI_SYSC_FCK,
+ TI_SYSC_ICK,
+ TI_SYSC_MAX_CLOCKS,
+};
+
+static const char *const clock_names[] = {"fck", "ick"};
+
+struct ti_sysc_priv {
+ int clocks_count;
+ struct clk clocks[TI_SYSC_MAX_CLOCKS];
+};
+
+static const struct udevice_id ti_sysc_ids[] = {
+ {.compatible = "ti,sysc-omap2"},
+ {.compatible = "ti,sysc-omap4"},
+ {.compatible = "ti,sysc-omap4-simple"},
+ {.compatible = "ti,sysc-omap3430-sr"},
+ {.compatible = "ti,sysc-omap3630-sr"},
+ {.compatible = "ti,sysc-omap4-sr"},
+ {.compatible = "ti,sysc-omap3-sham"},
+ {.compatible = "ti,sysc-omap-aes"},
+ {.compatible = "ti,sysc-mcasp"},
+ {.compatible = "ti,sysc-usb-host-fs"},
+ {}
+};
+
+static int ti_sysc_get_one_clock(struct udevice *dev, enum ti_sysc_clocks index)
+{
+ struct ti_sysc_priv *priv = dev_get_priv(dev);
+ const char *name;
+ int err;
+
+ switch (index) {
+ case TI_SYSC_FCK:
+ break;
+ case TI_SYSC_ICK:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ name = clock_names[index];
+
+ err = clk_get_by_name(dev, name, &priv->clocks[index]);
+ if (err) {
+ if (err == -ENODATA)
+ return 0;
+
+ dev_err(dev, "failed to get %s clock\n", name);
+ return err;
+ }
+
+ return 0;
+}
+
+static int ti_sysc_put_clocks(struct udevice *dev)
+{
+ struct ti_sysc_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_release_all(priv->clocks, priv->clocks_count);
+ if (err)
+ dev_err(dev, "failed to release all clocks\n");
+
+ return err;
+}
+
+static int ti_sysc_get_clocks(struct udevice *dev)
+{
+ struct ti_sysc_priv *priv = dev_get_priv(dev);
+ int i, err;
+
+ for (i = 0; i < TI_SYSC_MAX_CLOCKS; i++) {
+ err = ti_sysc_get_one_clock(dev, i);
+ if (!err)
+ priv->clocks_count++;
+ else if (err != -ENOENT)
+ return err;
+ }
+
+ return 0;
+}
+
+static int ti_sysc_child_post_remove(struct udevice *dev)
+{
+ struct ti_sysc_priv *priv = dev_get_priv(dev->parent);
+ int i, err;
+
+ for (i = 0; i < priv->clocks_count; i++) {
+ err = clk_disable(&priv->clocks[i]);
+ if (err) {
+ dev_err(dev->parent, "failed to disable %s clock\n",
+ clock_names[i]);
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+static int ti_sysc_child_pre_probe(struct udevice *dev)
+{
+ struct ti_sysc_priv *priv = dev_get_priv(dev->parent);
+ int i, err;
+
+ for (i = 0; i < priv->clocks_count; i++) {
+ err = clk_enable(&priv->clocks[i]);
+ if (err) {
+ dev_err(dev->parent, "failed to enable %s clock\n",
+ clock_names[i]);
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+static int ti_sysc_remove(struct udevice *dev)
+{
+ return ti_sysc_put_clocks(dev);
+}
+
+static int ti_sysc_probe(struct udevice *dev)
+{
+ int err;
+
+ err = ti_sysc_get_clocks(dev);
+ if (err)
+ goto clocks_err;
+
+ return 0;
+
+clocks_err:
+ ti_sysc_put_clocks(dev);
+ return err;
+}
+
+UCLASS_DRIVER(ti_sysc) = {
+ .id = UCLASS_SIMPLE_BUS,
+ .name = "ti_sysc",
+ .post_bind = dm_scan_fdt_dev
+};
+
+U_BOOT_DRIVER(ti_sysc) = {
+ .name = "ti_sysc",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = ti_sysc_ids,
+ .probe = ti_sysc_probe,
+ .remove = ti_sysc_remove,
+ .child_pre_probe = ti_sysc_child_pre_probe,
+ .child_post_remove = ti_sysc_child_post_remove,
+ .priv_auto_alloc_size = sizeof(struct ti_sysc_priv)
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 04/28] arm: dts: sync am33xx with Linux 5.9-rc7
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
` (2 preceding siblings ...)
2020-12-24 7:25 ` [PATCH v7 03/28] bus: ti: add minimal sysc interconnect target driver Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 05/28] clk: add clk_round_rate() Dario Binacchi
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
There have been several changes to the am33xx.dtsi, so this patch
re-syncs it with Linux.
Let's add proper interconnect hierarchy for l4 interconnect instances
with the related ti-sysc interconnect module data as documented in
Documentation/devicetree/bindings/bus/ti-sysc.txt of the Linux kernel.
With l4 interconnect hierarchy and ti-sysc interconnect target module
data in place, we can simply move all the related child devices to their
proper location and enable probing using ti-sysc.
The am33xx-clock.dtsi file is the same as that of the Linux kernel,
except for the reg property of the node l4-wkup-clkctrl at 0.
As for the am33xx.dtsi file, all the devices with drivers not yet
implemented and those I was able to test with this patch have been moved
to am33xx-l4.dtsi. In case of any regressions, problem devices can be
reverted by moving them back and removing the related interconnect
target module node.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
---
(no changes since v4)
Changes in v4:
- Remove a blank line at end of file arch/arm/dts/am33xx-l4.dtsi.
arch/arm/dts/am335x-draco.dtsi | 11 +-
arch/arm/dts/am335x-evm.dts | 2 +-
arch/arm/dts/am335x-evmsk.dts | 2 +-
arch/arm/dts/am335x-guardian-u-boot.dtsi | 5 -
arch/arm/dts/am335x-pxm2.dtsi | 2 +-
arch/arm/dts/am335x-rut.dts | 2 +-
arch/arm/dts/am335x-shc.dts | 2 +-
arch/arm/dts/am33xx-clocks.dtsi | 106 +-
arch/arm/dts/am33xx-l4.dtsi | 1962 ++++++++++++++++++++++
arch/arm/dts/am33xx.dtsi | 721 +++-----
10 files changed, 2273 insertions(+), 542 deletions(-)
create mode 100644 arch/arm/dts/am33xx-l4.dtsi
diff --git a/arch/arm/dts/am335x-draco.dtsi b/arch/arm/dts/am335x-draco.dtsi
index b38ff55e1d..2c125fcec9 100644
--- a/arch/arm/dts/am335x-draco.dtsi
+++ b/arch/arm/dts/am335x-draco.dtsi
@@ -20,11 +20,6 @@
};
ocp {
- uart0: serial at 44e09000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
- };
i2c0: i2c at 44e0b000 {
pinctrl-names = "default";
@@ -112,6 +107,12 @@
status = "disabled";
};
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
&uart4 {
status = "disabled";
};
diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
index 0bda4d4429..07288fb188 100644
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -486,7 +486,7 @@
&epwmss0 {
status = "okay";
- ecap0: ecap at 48300100 {
+ ecap0: ecap at 100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts
index 5762967cf7..c94c33b595 100644
--- a/arch/arm/dts/am335x-evmsk.dts
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -531,7 +531,7 @@
&epwmss2 {
status = "okay";
- ecap2: ecap at 48304100 {
+ ecap2: ecap at 100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap2_pins>;
diff --git a/arch/arm/dts/am335x-guardian-u-boot.dtsi b/arch/arm/dts/am335x-guardian-u-boot.dtsi
index 705ef335bf..eae027c541 100644
--- a/arch/arm/dts/am335x-guardian-u-boot.dtsi
+++ b/arch/arm/dts/am335x-guardian-u-boot.dtsi
@@ -26,11 +26,6 @@
u-boot,dm-pre-reloc;
};
-&rtc {
- clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
- clock-names = "int-clk";
-};
-
&scm {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/am335x-pxm2.dtsi b/arch/arm/dts/am335x-pxm2.dtsi
index 19bd7e2420..645d221507 100644
--- a/arch/arm/dts/am335x-pxm2.dtsi
+++ b/arch/arm/dts/am335x-pxm2.dtsi
@@ -148,7 +148,7 @@
&epwmss0 {
status = "okay";
- ecap0: ecap at 48300100 {
+ ecap0: ecap at 100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
diff --git a/arch/arm/dts/am335x-rut.dts b/arch/arm/dts/am335x-rut.dts
index 145247344f..cc06f5d23a 100644
--- a/arch/arm/dts/am335x-rut.dts
+++ b/arch/arm/dts/am335x-rut.dts
@@ -174,7 +174,7 @@
&epwmss0 {
status = "okay";
- ecap0: ecap at 48300100 {
+ ecap0: ecap at 100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
diff --git a/arch/arm/dts/am335x-shc.dts b/arch/arm/dts/am335x-shc.dts
index 8e35c439e5..a41a0606b1 100644
--- a/arch/arm/dts/am335x-shc.dts
+++ b/arch/arm/dts/am335x-shc.dts
@@ -136,7 +136,7 @@
&epwmss1 {
status = "okay";
- ehrpwm1: pwm at 48302200 {
+ ehrpwm1: pwm at 200 {
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm1_pins>;
status = "okay";
diff --git a/arch/arm/dts/am33xx-clocks.dtsi b/arch/arm/dts/am33xx-clocks.dtsi
index 95d5c9d136..87c4410ee2 100644
--- a/arch/arm/dts/am33xx-clocks.dtsi
+++ b/arch/arm/dts/am33xx-clocks.dtsi
@@ -334,49 +334,49 @@
timer1_fck: timer1_fck at 528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+ clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
timer2_fck: timer2_fck at 508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
timer3_fck: timer3_fck at 50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
timer4_fck: timer4_fck at 510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
timer5_fck: timer5_fck at 518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
timer6_fck: timer6_fck at 51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
timer7_fck: timer7_fck at 504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
@@ -407,7 +407,7 @@
wdt1_fck: wdt1_fck at 538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
@@ -477,7 +477,7 @@
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck at 53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
@@ -539,77 +539,131 @@
};
&prcm {
- l4_per_cm: l4_per_cm at 0 {
+ l4_per_cm: l4_per-cm at 0 {
compatible = "ti,omap4-cm";
- reg = <0x0 0x200>;
+ reg = <0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x0 0x200>;
+ ranges = <0 0x0 0x400>;
- l4_per_clkctrl: clk at 14 {
+ l4ls_clkctrl: l4ls-clkctrl at 38 {
compatible = "ti,clkctrl";
- reg = <0x14 0x13c>;
+ reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
+ #clock-cells = <2>;
+ };
+
+ l3s_clkctrl: l3s-clkctrl at 1c {
+ compatible = "ti,clkctrl";
+ reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
+ #clock-cells = <2>;
+ };
+
+ l3_clkctrl: l3-clkctrl at 24 {
+ compatible = "ti,clkctrl";
+ reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
+ #clock-cells = <2>;
+ };
+
+ l4hs_clkctrl: l4hs-clkctrl at 120 {
+ compatible = "ti,clkctrl";
+ reg = <0x120 0x4>;
+ #clock-cells = <2>;
+ };
+
+ pruss_ocp_clkctrl: pruss-ocp-clkctrl at e8 {
+ compatible = "ti,clkctrl";
+ reg = <0xe8 0x4>;
+ #clock-cells = <2>;
+ };
+
+ cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl at 0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x18>;
+ #clock-cells = <2>;
+ };
+
+ lcdc_clkctrl: lcdc-clkctrl at 18 {
+ compatible = "ti,clkctrl";
+ reg = <0x18 0x4>;
+ #clock-cells = <2>;
+ };
+
+ clk_24mhz_clkctrl: clk-24mhz-clkctrl at 14c {
+ compatible = "ti,clkctrl";
+ reg = <0x14c 0x4>;
#clock-cells = <2>;
};
};
- l4_wkup_cm: l4_wkup_cm at 400 {
+ wkup_cm: wkup-cm at 400 {
compatible = "ti,omap4-cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
- l4_wkup_clkctrl: clk at 4 {
+ l4_wkup_clkctrl: l4-wkup-clkctrl at 0 {
+ compatible = "ti,clkctrl";
+ reg = <0x4 0x10>, <0xb4 0x24>;
+ #clock-cells = <2>;
+ };
+
+ l3_aon_clkctrl: l3-aon-clkctrl at 14 {
+ compatible = "ti,clkctrl";
+ reg = <0x14 0x4>;
+ #clock-cells = <2>;
+ };
+
+ l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl at b0 {
compatible = "ti,clkctrl";
- reg = <0x4 0xd4>;
+ reg = <0xb0 0x4>;
#clock-cells = <2>;
};
};
- mpu_cm: mpu_cm at 600 {
+ mpu_cm: mpu-cm at 600 {
compatible = "ti,omap4-cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
- mpu_clkctrl: clk at 4 {
+ mpu_clkctrl: mpu-clkctrl at 0 {
compatible = "ti,clkctrl";
- reg = <0x4 0x4>;
+ reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
- l4_rtc_cm: l4_rtc_cm at 800 {
+ l4_rtc_cm: l4-rtc-cm at 800 {
compatible = "ti,omap4-cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x100>;
- l4_rtc_clkctrl: clk at 0 {
+ l4_rtc_clkctrl: l4-rtc-clkctrl at 0 {
compatible = "ti,clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
- gfx_l3_cm: gfx_l3_cm at 900 {
+ gfx_l3_cm: gfx-l3-cm at 900 {
compatible = "ti,omap4-cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
- gfx_l3_clkctrl: clk at 4 {
+ gfx_l3_clkctrl: gfx-l3-clkctrl at 0 {
compatible = "ti,clkctrl";
- reg = <0x4 0x4>;
+ reg = <0x0 0x8>;
#clock-cells = <2>;
};
};
- l4_cefuse_cm: l4_cefuse_cm at a00 {
+ l4_cefuse_cm: l4-cefuse-cm at a00 {
compatible = "ti,omap4-cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
diff --git a/arch/arm/dts/am33xx-l4.dtsi b/arch/arm/dts/am33xx-l4.dtsi
new file mode 100644
index 0000000000..257991e2ad
--- /dev/null
+++ b/arch/arm/dts/am33xx-l4.dtsi
@@ -0,0 +1,1962 @@
+&l4_wkup { /* 0x44c00000 */
+ compatible = "ti,am33xx-l4-wkup", "simple-bus";
+ reg = <0x44c00000 0x800>,
+ <0x44c00800 0x800>,
+ <0x44c01000 0x400>,
+ <0x44c01400 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
+ <0x00100000 0x44d00000 0x100000>, /* segment 1 */
+ <0x00200000 0x44e00000 0x100000>; /* segment 2 */
+
+ segment at 0 { /* 0x44c00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x000400>, /* ap 2 */
+ <0x00001400 0x00001400 0x000400>; /* ap 3 */
+ };
+
+ segment at 100000 { /* 0x44d00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
+ <0x00004000 0x00104000 0x001000>, /* ap 5 */
+ <0x00080000 0x00180000 0x002000>, /* ap 6 */
+ <0x00082000 0x00182000 0x001000>; /* ap 7 */
+
+ target-module at 0 { /* 0x44d00000, ap 4 28.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x0 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x4000>;
+ status = "disabled";
+ };
+
+ target-module at 80000 { /* 0x44d80000, ap 6 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x2000>;
+ };
+ };
+
+ segment at 200000 { /* 0x44e00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */
+ <0x00002000 0x00202000 0x001000>, /* ap 9 */
+ <0x00003000 0x00203000 0x001000>, /* ap 10 */
+ <0x00004000 0x00204000 0x001000>, /* ap 11 */
+ <0x00005000 0x00205000 0x001000>, /* ap 12 */
+ <0x00006000 0x00206000 0x001000>, /* ap 13 */
+ <0x00007000 0x00207000 0x001000>, /* ap 14 */
+ <0x00008000 0x00208000 0x001000>, /* ap 15 */
+ <0x00009000 0x00209000 0x001000>, /* ap 16 */
+ <0x0000a000 0x0020a000 0x001000>, /* ap 17 */
+ <0x0000b000 0x0020b000 0x001000>, /* ap 18 */
+ <0x0000c000 0x0020c000 0x001000>, /* ap 19 */
+ <0x0000d000 0x0020d000 0x001000>, /* ap 20 */
+ <0x0000f000 0x0020f000 0x001000>, /* ap 21 */
+ <0x00010000 0x00210000 0x010000>, /* ap 22 */
+ <0x00020000 0x00220000 0x010000>, /* ap 23 */
+ <0x00030000 0x00230000 0x001000>, /* ap 24 */
+ <0x00031000 0x00231000 0x001000>, /* ap 25 */
+ <0x00032000 0x00232000 0x001000>, /* ap 26 */
+ <0x00033000 0x00233000 0x001000>, /* ap 27 */
+ <0x00034000 0x00234000 0x001000>, /* ap 28 */
+ <0x00035000 0x00235000 0x001000>, /* ap 29 */
+ <0x00036000 0x00236000 0x001000>, /* ap 30 */
+ <0x00037000 0x00237000 0x001000>, /* ap 31 */
+ <0x00038000 0x00238000 0x001000>, /* ap 32 */
+ <0x00039000 0x00239000 0x001000>, /* ap 33 */
+ <0x0003a000 0x0023a000 0x001000>, /* ap 34 */
+ <0x0003e000 0x0023e000 0x001000>, /* ap 35 */
+ <0x0003f000 0x0023f000 0x001000>, /* ap 36 */
+ <0x0000e000 0x0020e000 0x001000>, /* ap 37 */
+ <0x00040000 0x00240000 0x040000>, /* ap 38 */
+ <0x00080000 0x00280000 0x001000>; /* ap 39 */
+
+ target-module at 0 { /* 0x44e00000, ap 8 58.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x2000>;
+
+ prcm: prcm at 0 {
+ compatible = "ti,am3-prcm", "simple-bus";
+ reg = <0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ prcm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prcm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ target-module at 3000 { /* 0x44e03000, ap 10 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3000 0x1000>;
+ };
+
+ target-module at 5000 { /* 0x44e05000, ap 12 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x5000 0x1000>;
+ };
+
+ gpio0_target: target-module at 7000 { /* 0x44e07000, ap 14 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x7000 0x4>,
+ <0x7010 0x4>,
+ <0x7114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
+ <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x7000 0x1000>;
+ };
+
+ target-module at 9000 { /* 0x44e09000, ap 16 04.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x9050 0x4>,
+ <0x9054 0x4>,
+ <0x9058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9000 0x1000>;
+
+ uart0: serial at 0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x1000>;
+ interrupts = <72>;
+ status = "disabled";
+ dmas = <&edma 26 0>, <&edma 27 0>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module at b000 { /* 0x44e0b000, ap 18 48.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xb000 0x8>,
+ <0xb010 0x8>,
+ <0xb090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb000 0x1000>;
+ };
+
+ target-module at d000 { /* 0x44e0d000, ap 20 38.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xd000 0x4>,
+ <0xd010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x0000d000 0x00001000>,
+ <0x00001000 0x0000e000 0x00001000>;
+
+ tscadc: tscadc at 0 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x0 0x1000>;
+ interrupts = <16>;
+ status = "disabled";
+ dmas = <&edma 53 0>, <&edma 57 0>;
+ dma-names = "fifo0", "fifo1";
+
+ tsc {
+ compatible = "ti,am3359-tsc";
+ };
+ am335x_adc: adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am3359-adc";
+ };
+ };
+
+ };
+
+ target-module at 10000 { /* 0x44e10000, ap 22 0c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x10000 0x4>;
+ reg-names = "rev";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00010000 0x00010000>,
+ <0x00010000 0x00020000 0x00010000>;
+
+ scm: scm at 0 {
+ compatible = "ti,am3-scm", "simple-bus";
+ reg = <0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #pinctrl-cells = <1>;
+ ranges = <0 0 0x2000>;
+
+ am33xx_pinmux: pinmux at 800 {
+ compatible = "pinctrl-single";
+ reg = <0x800 0x238>;
+ #pinctrl-cells = <2>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x7f>;
+ };
+
+ scm_conf: scm_conf at 0 {
+ compatible = "syscon", "simple-bus";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x800>;
+
+ phy_gmii_sel: phy-gmii-sel {
+ compatible = "ti,am3352-phy-gmii-sel";
+ reg = <0x650 0x4>;
+ #phy-cells = <2>;
+ };
+
+ scm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ wkup_m3_ipc: wkup_m3_ipc at 1324 {
+ compatible = "ti,am3352-wkup-m3-ipc";
+ reg = <0x1324 0x24>;
+ interrupts = <78>;
+ ti,rproc = <&wkup_m3>;
+ mboxes = <&mailbox &mbox_wkupm3>;
+ };
+
+ edma_xbar: dma-router at f90 {
+ compatible = "ti,am335x-edma-crossbar";
+ reg = <0xf90 0x40>;
+ #dma-cells = <3>;
+ dma-requests = <32>;
+ dma-masters = <&edma>;
+ };
+
+ scm_clockdomains: clockdomains {
+ };
+ };
+ };
+
+ timer1_target: target-module at 31000 { /* 0x44e31000, ap 25 40.0 */
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x31000 0x4>,
+ <0x31010 0x4>,
+ <0x31014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x31000 0x1000>;
+
+ timer1: timer at 0 {
+ compatible = "ti,am335x-timer-1ms";
+ reg = <0x0 0x400>;
+ interrupts = <67>;
+ ti,timer-alwon;
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module at 33000 { /* 0x44e33000, ap 27 18.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x33000 0x1000>;
+ };
+
+ target-module at 35000 { /* 0x44e35000, ap 29 50.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x35000 0x4>,
+ <0x35010 0x4>,
+ <0x35014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_SOFTRESET)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
+ clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x35000 0x1000>;
+ };
+
+ target-module at 37000 { /* 0x44e37000, ap 31 08.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x37000 0x1000>;
+ };
+
+ target-module at 39000 { /* 0x44e39000, ap 33 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x39000 0x1000>;
+ };
+
+ target-module at 3e000 { /* 0x44e3e000, ap 35 60.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ reg = <0x3e074 0x4>,
+ <0x3e078 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
+ clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>;
+
+ rtc: rtc at 0 {
+ compatible = "ti,am3352-rtc", "ti,da830-rtc";
+ reg = <0x0 0x1000>;
+ interrupts = <75 76>;
+ };
+ };
+
+ target-module at 40000 { /* 0x44e40000, ap 38 68.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x40000>;
+ };
+ };
+};
+
+&l4_fw { /* 0x47c00000 */
+ compatible = "ti,am33xx-l4-fw", "simple-bus";
+ reg = <0x47c00000 0x800>,
+ <0x47c00800 0x800>,
+ <0x47c01000 0x400>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */
+
+ segment at 0 { /* 0x47c00000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x000400>, /* ap 2 */
+ <0x0000c000 0x0000c000 0x001000>, /* ap 3 */
+ <0x0000d000 0x0000d000 0x001000>, /* ap 4 */
+ <0x0000e000 0x0000e000 0x001000>, /* ap 5 */
+ <0x0000f000 0x0000f000 0x001000>, /* ap 6 */
+ <0x00010000 0x00010000 0x001000>, /* ap 7 */
+ <0x00011000 0x00011000 0x001000>, /* ap 8 */
+ <0x0001a000 0x0001a000 0x001000>, /* ap 9 */
+ <0x0001b000 0x0001b000 0x001000>, /* ap 10 */
+ <0x00024000 0x00024000 0x001000>, /* ap 11 */
+ <0x00025000 0x00025000 0x001000>, /* ap 12 */
+ <0x00026000 0x00026000 0x001000>, /* ap 13 */
+ <0x00027000 0x00027000 0x001000>, /* ap 14 */
+ <0x00030000 0x00030000 0x001000>, /* ap 15 */
+ <0x00031000 0x00031000 0x001000>, /* ap 16 */
+ <0x00038000 0x00038000 0x001000>, /* ap 17 */
+ <0x00039000 0x00039000 0x001000>, /* ap 18 */
+ <0x0003a000 0x0003a000 0x001000>, /* ap 19 */
+ <0x0003b000 0x0003b000 0x001000>, /* ap 20 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
+ <0x0003f000 0x0003f000 0x001000>, /* ap 22 */
+ <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
+ <0x00040000 0x00040000 0x001000>, /* ap 24 */
+ <0x00046000 0x00046000 0x001000>, /* ap 25 */
+ <0x00047000 0x00047000 0x001000>, /* ap 26 */
+ <0x00044000 0x00044000 0x001000>, /* ap 27 */
+ <0x00045000 0x00045000 0x001000>, /* ap 28 */
+ <0x00028000 0x00028000 0x001000>, /* ap 29 */
+ <0x00029000 0x00029000 0x001000>, /* ap 30 */
+ <0x00032000 0x00032000 0x001000>, /* ap 31 */
+ <0x00033000 0x00033000 0x001000>, /* ap 32 */
+ <0x0003d000 0x0003d000 0x001000>, /* ap 33 */
+ <0x00041000 0x00041000 0x001000>, /* ap 34 */
+ <0x00042000 0x00042000 0x001000>, /* ap 35 */
+ <0x00043000 0x00043000 0x001000>, /* ap 36 */
+ <0x00014000 0x00014000 0x001000>, /* ap 37 */
+ <0x00015000 0x00015000 0x001000>; /* ap 38 */
+
+ target-module at c000 { /* 0x47c0c000, ap 3 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc000 0x1000>;
+ };
+
+ target-module at e000 { /* 0x47c0e000, ap 5 0c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe000 0x1000>;
+ };
+
+ target-module at 10000 { /* 0x47c10000, ap 7 20.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000 0x1000>;
+ };
+
+ target-module at 14000 { /* 0x47c14000, ap 37 3c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x14000 0x1000>;
+ };
+
+ target-module at 1a000 { /* 0x47c1a000, ap 9 08.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1a000 0x1000>;
+ };
+
+ target-module at 24000 { /* 0x47c24000, ap 11 28.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+ };
+
+ target-module at 26000 { /* 0x47c26000, ap 13 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x26000 0x1000>;
+ };
+
+ target-module at 28000 { /* 0x47c28000, ap 29 40.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x28000 0x1000>;
+ };
+
+ target-module at 30000 { /* 0x47c30000, ap 15 14.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000 0x1000>;
+ };
+
+ target-module at 32000 { /* 0x47c32000, ap 31 06.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x32000 0x1000>;
+ };
+
+ target-module at 38000 { /* 0x47c38000, ap 17 18.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x38000 0x1000>;
+ };
+
+ target-module at 3a000 { /* 0x47c3a000, ap 19 1c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3a000 0x1000>;
+ };
+
+ target-module at 3c000 { /* 0x47c3c000, ap 23 38.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3c000 0x1000>;
+ };
+
+ target-module at 3e000 { /* 0x47c3e000, ap 21 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3e000 0x1000>;
+ };
+
+ target-module at 40000 { /* 0x47c40000, ap 24 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x1000>;
+ };
+
+ target-module at 42000 { /* 0x47c42000, ap 35 34.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x42000 0x1000>;
+ };
+
+ target-module at 44000 { /* 0x47c44000, ap 27 24.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x44000 0x1000>;
+ };
+
+ target-module at 46000 { /* 0x47c46000, ap 25 2c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x46000 0x1000>;
+ };
+ };
+};
+
+&l4_fast { /* 0x4a000000 */
+ compatible = "ti,am33xx-l4-fast", "simple-bus";
+ reg = <0x4a000000 0x800>,
+ <0x4a000800 0x800>,
+ <0x4a001000 0x400>;
+ reg-names = "ap", "la", "ia0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
+
+ segment at 0 { /* 0x4a000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x000400>, /* ap 2 */
+ <0x00100000 0x00100000 0x008000>, /* ap 3 */
+ <0x00108000 0x00108000 0x001000>, /* ap 4 */
+ <0x00180000 0x00180000 0x020000>, /* ap 5 */
+ <0x001a0000 0x001a0000 0x001000>, /* ap 6 */
+ <0x00200000 0x00200000 0x080000>, /* ap 7 */
+ <0x00280000 0x00280000 0x001000>, /* ap 8 */
+ <0x00300000 0x00300000 0x080000>, /* ap 9 */
+ <0x00380000 0x00380000 0x001000>; /* ap 10 */
+
+ target-module at 100000 { /* 0x4a100000, ap 3 08.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ reg = <0x101200 0x4>,
+ <0x101208 0x4>,
+ <0x101204 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <0>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ ti,syss-mask = <1>;
+ clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x100000 0x8000>;
+ };
+
+ target-module at 180000 { /* 0x4a180000, ap 5 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x180000 0x20000>;
+ };
+
+ target-module at 200000 { /* 0x4a200000, ap 7 02.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x200000 0x80000>;
+ };
+
+ pruss_tm: target-module at 300000 { /* 0x4a300000, ap 9 04.0 */
+ compatible = "ti,sysc-pruss", "ti,sysc";
+ reg = <0x326000 0x4>,
+ <0x326004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
+ SYSC_PRUSS_SUB_MWAIT)>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&pruss_ocp_clkctrl AM3_PRUSS_OCP_PRUSS_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_per 1>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x300000 0x80000>;
+ status = "disabled";
+ };
+ };
+};
+
+&l4_mpuss { /* 0x4b140000 */
+ compatible = "ti,am33xx-l4-mpuss", "simple-bus";
+ reg = <0x4b144400 0x100>,
+ <0x4b144800 0x400>;
+ reg-names = "la", "ap";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */
+
+ segment at 0 { /* 0x4b140000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */
+ <0x00001000 0x00001000 0x001000>, /* ap 1 */
+ <0x00002000 0x00002000 0x001000>, /* ap 2 */
+ <0x00004000 0x00004000 0x000400>, /* ap 3 */
+ <0x00005000 0x00005000 0x000400>, /* ap 4 */
+ <0x00000000 0x00000000 0x001000>, /* ap 5 */
+ <0x00003000 0x00003000 0x001000>, /* ap 6 */
+ <0x00000800 0x00000800 0x000800>; /* ap 7 */
+
+ target-module at 0 { /* 0x4b140000, ap 5 02.2 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x00001000>,
+ <0x00001000 0x00001000 0x00001000>,
+ <0x00002000 0x00002000 0x00001000>;
+ };
+
+ target-module at 3000 { /* 0x4b143000, ap 6 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3000 0x1000>;
+ };
+ };
+};
+
+&l4_per { /* 0x48000000 */
+ compatible = "ti,am33xx-l4-per", "simple-bus";
+ reg = <0x48000000 0x800>,
+ <0x48000800 0x800>,
+ <0x48001000 0x400>,
+ <0x48001400 0x400>,
+ <0x48001800 0x400>,
+ <0x48001c00 0x400>;
+ reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
+ <0x00100000 0x48100000 0x100000>, /* segment 1 */
+ <0x00200000 0x48200000 0x100000>, /* segment 2 */
+ <0x00300000 0x48300000 0x100000>, /* segment 3 */
+ <0x46000000 0x46000000 0x400000>, /* l3 data port */
+ <0x46400000 0x46400000 0x400000>; /* l3 data port */
+
+ segment at 0 { /* 0x48000000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
+ <0x00000800 0x00000800 0x000800>, /* ap 1 */
+ <0x00001000 0x00001000 0x000400>, /* ap 2 */
+ <0x00001400 0x00001400 0x000400>, /* ap 3 */
+ <0x00001800 0x00001800 0x000400>, /* ap 4 */
+ <0x00001c00 0x00001c00 0x000400>, /* ap 5 */
+ <0x00008000 0x00008000 0x001000>, /* ap 6 */
+ <0x00009000 0x00009000 0x001000>, /* ap 7 */
+ <0x00016000 0x00016000 0x001000>, /* ap 8 */
+ <0x00017000 0x00017000 0x001000>, /* ap 9 */
+ <0x00022000 0x00022000 0x001000>, /* ap 10 */
+ <0x00023000 0x00023000 0x001000>, /* ap 11 */
+ <0x00024000 0x00024000 0x001000>, /* ap 12 */
+ <0x00025000 0x00025000 0x001000>, /* ap 13 */
+ <0x0002a000 0x0002a000 0x001000>, /* ap 14 */
+ <0x0002b000 0x0002b000 0x001000>, /* ap 15 */
+ <0x00038000 0x00038000 0x002000>, /* ap 16 */
+ <0x0003a000 0x0003a000 0x001000>, /* ap 17 */
+ <0x00014000 0x00014000 0x001000>, /* ap 18 */
+ <0x00015000 0x00015000 0x001000>, /* ap 19 */
+ <0x0003c000 0x0003c000 0x002000>, /* ap 20 */
+ <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
+ <0x00040000 0x00040000 0x001000>, /* ap 22 */
+ <0x00041000 0x00041000 0x001000>, /* ap 23 */
+ <0x00042000 0x00042000 0x001000>, /* ap 24 */
+ <0x00043000 0x00043000 0x001000>, /* ap 25 */
+ <0x00044000 0x00044000 0x001000>, /* ap 26 */
+ <0x00045000 0x00045000 0x001000>, /* ap 27 */
+ <0x00046000 0x00046000 0x001000>, /* ap 28 */
+ <0x00047000 0x00047000 0x001000>, /* ap 29 */
+ <0x00048000 0x00048000 0x001000>, /* ap 30 */
+ <0x00049000 0x00049000 0x001000>, /* ap 31 */
+ <0x0004c000 0x0004c000 0x001000>, /* ap 32 */
+ <0x0004d000 0x0004d000 0x001000>, /* ap 33 */
+ <0x00050000 0x00050000 0x002000>, /* ap 34 */
+ <0x00052000 0x00052000 0x001000>, /* ap 35 */
+ <0x00060000 0x00060000 0x001000>, /* ap 36 */
+ <0x00061000 0x00061000 0x001000>, /* ap 37 */
+ <0x00080000 0x00080000 0x010000>, /* ap 38 */
+ <0x00090000 0x00090000 0x001000>, /* ap 39 */
+ <0x000a0000 0x000a0000 0x010000>, /* ap 40 */
+ <0x000b0000 0x000b0000 0x001000>, /* ap 41 */
+ <0x00030000 0x00030000 0x001000>, /* ap 77 */
+ <0x00031000 0x00031000 0x001000>, /* ap 78 */
+ <0x0004a000 0x0004a000 0x001000>, /* ap 85 */
+ <0x0004b000 0x0004b000 0x001000>, /* ap 86 */
+ <0x000c8000 0x000c8000 0x001000>, /* ap 87 */
+ <0x000c9000 0x000c9000 0x001000>, /* ap 88 */
+ <0x000cc000 0x000cc000 0x001000>, /* ap 89 */
+ <0x000cd000 0x000cd000 0x001000>, /* ap 90 */
+ <0x000ca000 0x000ca000 0x001000>, /* ap 91 */
+ <0x000cb000 0x000cb000 0x001000>, /* ap 92 */
+ <0x46000000 0x46000000 0x400000>, /* l3 data port */
+ <0x46400000 0x46400000 0x400000>; /* l3 data port */
+
+ target-module at 8000 { /* 0x48008000, ap 6 10.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8000 0x1000>;
+ };
+
+ target-module at 14000 { /* 0x48014000, ap 18 58.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x14000 0x1000>;
+ };
+
+ target-module at 16000 { /* 0x48016000, ap 8 3c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x16000 0x1000>;
+ };
+
+ target-module at 22000 { /* 0x48022000, ap 10 12.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x22050 0x4>,
+ <0x22054 0x4>,
+ <0x22058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>;
+
+ uart1: serial at 0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x1000>;
+ interrupts = <73>;
+ status = "disabled";
+ dmas = <&edma 28 0>, <&edma 29 0>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module at 24000 { /* 0x48024000, ap 12 14.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x24050 0x4>,
+ <0x24054 0x4>,
+ <0x24058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+
+ uart2: serial at 0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x1000>;
+ interrupts = <74>;
+ status = "disabled";
+ dmas = <&edma 30 0>, <&edma 31 0>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module at 2a000 { /* 0x4802a000, ap 14 2a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x2a000 0x8>,
+ <0x2a010 0x8>,
+ <0x2a090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2a000 0x1000>;
+ };
+
+ target-module at 30000 { /* 0x48030000, ap 77 08.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x30000 0x4>,
+ <0x30110 0x4>,
+ <0x30114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x30000 0x1000>;
+
+ spi0: spi at 0 {
+ compatible = "ti,omap4-mcspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x400>;
+ interrupts = <65>;
+ ti,spi-num-cs = <2>;
+ dmas = <&edma 16 0
+ &edma 17 0
+ &edma 18 0
+ &edma 19 0>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ status = "disabled";
+ };
+ };
+
+ target-module at 38000 { /* 0x48038000, ap 16 02.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ reg = <0x38000 0x4>,
+ <0x38004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, l3s_clkdm */
+ clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x38000 0x2000>,
+ <0x46000000 0x46000000 0x400000>;
+
+ mcasp0: mcasp at 0 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x2000>,
+ <0x46000000 0x400000>;
+ reg-names = "mpu", "dat";
+ interrupts = <80>, <81>;
+ interrupt-names = "tx", "rx";
+ status = "disabled";
+ dmas = <&edma 8 2>,
+ <&edma 9 2>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ target-module at 3c000 { /* 0x4803c000, ap 20 32.0 */
+ compatible = "ti,sysc-omap4-simple", "ti,sysc";
+ reg = <0x3c000 0x4>,
+ <0x3c004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, l3s_clkdm */
+ clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x3c000 0x2000>,
+ <0x46400000 0x46400000 0x400000>;
+
+ mcasp1: mcasp at 0 {
+ compatible = "ti,am33xx-mcasp-audio";
+ reg = <0x0 0x2000>,
+ <0x46400000 0x400000>;
+ reg-names = "mpu", "dat";
+ interrupts = <82>, <83>;
+ interrupt-names = "tx", "rx";
+ status = "disabled";
+ dmas = <&edma 10 2>,
+ <&edma 11 2>;
+ dma-names = "tx", "rx";
+ };
+ };
+
+ timer2_target: target-module at 40000 { /* 0x48040000, ap 22 1e.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x40000 0x4>,
+ <0x40010 0x4>,
+ <0x40014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x1000>;
+
+ timer2: timer at 0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <68>;
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
+ };
+ };
+
+ target-module at 42000 { /* 0x48042000, ap 24 1c.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x42000 0x4>,
+ <0x42010 0x4>,
+ <0x42014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x42000 0x1000>;
+
+ timer3: timer at 0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <69>;
+ };
+ };
+
+ target-module at 44000 { /* 0x48044000, ap 26 26.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x44000 0x4>,
+ <0x44010 0x4>,
+ <0x44014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x44000 0x1000>;
+
+ timer4: timer at 0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <92>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module at 46000 { /* 0x48046000, ap 28 28.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x46000 0x4>,
+ <0x46010 0x4>,
+ <0x46014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x46000 0x1000>;
+
+ timer5: timer at 0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <93>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module at 48000 { /* 0x48048000, ap 30 22.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x48000 0x4>,
+ <0x48010 0x4>,
+ <0x48014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48000 0x1000>;
+
+ timer6: timer at 0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <94>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module at 4a000 { /* 0x4804a000, ap 85 60.0 */
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x4a000 0x4>,
+ <0x4a010 0x4>,
+ <0x4a014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4a000 0x1000>;
+
+ timer7: timer at 0 {
+ compatible = "ti,am335x-timer";
+ reg = <0x0 0x400>;
+ interrupts = <95>;
+ ti,timer-pwm;
+ };
+ };
+
+ target-module at 4c000 { /* 0x4804c000, ap 32 36.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4c000 0x4>,
+ <0x4c010 0x4>,
+ <0x4c114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>,
+ <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4c000 0x1000>;
+ };
+
+ target-module at 50000 { /* 0x48050000, ap 34 2c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x50000 0x2000>;
+ };
+
+ target-module at 60000 { /* 0x48060000, ap 36 0c.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x602fc 0x4>,
+ <0x60110 0x4>,
+ <0x60114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x60000 0x1000>;
+ };
+
+ target-module at 80000 { /* 0x48080000, ap 38 18.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x80000 0x4>,
+ <0x80010 0x4>,
+ <0x80014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x10000>;
+
+ elm: elm at 0 {
+ compatible = "ti,am3352-elm";
+ reg = <0x0 0x2000>;
+ interrupts = <4>;
+ status = "disabled";
+ };
+ };
+
+ target-module at a0000 { /* 0x480a0000, ap 40 5e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa0000 0x10000>;
+ };
+
+ target-module at c8000 { /* 0x480c8000, ap 87 06.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xc8000 0x4>,
+ <0xc8010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xc8000 0x1000>;
+
+ mailbox: mailbox at 0 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x0 0x200>;
+ interrupts = <77>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <8>;
+ mbox_wkupm3: wkup_m3 {
+ ti,mbox-send-noirq;
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <0 0 3>;
+ };
+ };
+ };
+
+ target-module at ca000 { /* 0x480ca000, ap 91 40.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xca000 0x4>,
+ <0xca010 0x4>,
+ <0xca014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xca000 0x1000>;
+
+ hwspinlock: spinlock at 0 {
+ compatible = "ti,omap4-hwspinlock";
+ reg = <0x0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+ };
+
+ target-module at cc000 { /* 0x480cc000, ap 89 0e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xcc000 0x1000>;
+ };
+ };
+
+ segment at 100000 { /* 0x48100000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */
+ <0x0008d000 0x0018d000 0x001000>, /* ap 43 */
+ <0x0008e000 0x0018e000 0x001000>, /* ap 44 */
+ <0x0008f000 0x0018f000 0x001000>, /* ap 45 */
+ <0x0009c000 0x0019c000 0x001000>, /* ap 46 */
+ <0x0009d000 0x0019d000 0x001000>, /* ap 47 */
+ <0x000a6000 0x001a6000 0x001000>, /* ap 48 */
+ <0x000a7000 0x001a7000 0x001000>, /* ap 49 */
+ <0x000a8000 0x001a8000 0x001000>, /* ap 50 */
+ <0x000a9000 0x001a9000 0x001000>, /* ap 51 */
+ <0x000aa000 0x001aa000 0x001000>, /* ap 52 */
+ <0x000ab000 0x001ab000 0x001000>, /* ap 53 */
+ <0x000ac000 0x001ac000 0x001000>, /* ap 54 */
+ <0x000ad000 0x001ad000 0x001000>, /* ap 55 */
+ <0x000ae000 0x001ae000 0x001000>, /* ap 56 */
+ <0x000af000 0x001af000 0x001000>, /* ap 57 */
+ <0x000b0000 0x001b0000 0x010000>, /* ap 58 */
+ <0x000c0000 0x001c0000 0x001000>, /* ap 59 */
+ <0x000cc000 0x001cc000 0x002000>, /* ap 60 */
+ <0x000ce000 0x001ce000 0x002000>, /* ap 61 */
+ <0x000d0000 0x001d0000 0x002000>, /* ap 62 */
+ <0x000d2000 0x001d2000 0x002000>, /* ap 63 */
+ <0x000d8000 0x001d8000 0x001000>, /* ap 64 */
+ <0x000d9000 0x001d9000 0x001000>, /* ap 65 */
+ <0x000a0000 0x001a0000 0x001000>, /* ap 79 */
+ <0x000a1000 0x001a1000 0x001000>, /* ap 80 */
+ <0x000a2000 0x001a2000 0x001000>, /* ap 81 */
+ <0x000a3000 0x001a3000 0x001000>, /* ap 82 */
+ <0x000a4000 0x001a4000 0x001000>, /* ap 83 */
+ <0x000a5000 0x001a5000 0x001000>; /* ap 84 */
+
+ target-module at 8c000 { /* 0x4818c000, ap 42 04.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8c000 0x1000>;
+ };
+
+ target-module at 8e000 { /* 0x4818e000, ap 44 0a.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8e000 0x1000>;
+ };
+
+ target-module at 9c000 { /* 0x4819c000, ap 46 5a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x9c000 0x8>,
+ <0x9c010 0x8>,
+ <0x9c090 0x8>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x9c000 0x1000>;
+ };
+
+ target-module at a0000 { /* 0x481a0000, ap 79 24.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xa0000 0x4>,
+ <0xa0110 0x4>,
+ <0xa0114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa0000 0x1000>;
+
+ spi1: spi at 0 {
+ compatible = "ti,omap4-mcspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x400>;
+ interrupts = <125>;
+ ti,spi-num-cs = <2>;
+ dmas = <&edma 42 0
+ &edma 43 0
+ &edma 44 0
+ &edma 45 0>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ status = "disabled";
+ };
+ };
+
+ target-module at a2000 { /* 0x481a2000, ap 81 2e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa2000 0x1000>;
+ };
+
+ target-module at a4000 { /* 0x481a4000, ap 83 30.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa4000 0x1000>;
+ };
+
+ target-module at a6000 { /* 0x481a6000, ap 48 16.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xa6050 0x4>,
+ <0xa6054 0x4>,
+ <0xa6058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa6000 0x1000>;
+
+ uart3: serial at 0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x1000>;
+ interrupts = <44>;
+ status = "disabled";
+ };
+ };
+
+ target-module at a8000 { /* 0x481a8000, ap 50 20.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xa8050 0x4>,
+ <0xa8054 0x4>,
+ <0xa8058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xa8000 0x1000>;
+
+ uart4: serial at 0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x1000>;
+ interrupts = <45>;
+ status = "disabled";
+ };
+ };
+
+ target-module at aa000 { /* 0x481aa000, ap 52 1a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xaa050 0x4>,
+ <0xaa054 0x4>,
+ <0xaa058 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xaa000 0x1000>;
+
+ uart5: serial at 0 {
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
+ clock-frequency = <48000000>;
+ reg = <0x0 0x1000>;
+ interrupts = <46>;
+ status = "disabled";
+ };
+ };
+
+ target-module at ac000 { /* 0x481ac000, ap 54 38.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xac000 0x4>,
+ <0xac010 0x4>,
+ <0xac114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>,
+ <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xac000 0x1000>;
+ };
+
+ target-module at ae000 { /* 0x481ae000, ap 56 3a.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xae000 0x4>,
+ <0xae010 0x4>,
+ <0xae114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>,
+ <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>;
+ clock-names = "fck", "dbclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xae000 0x1000>;
+ };
+
+ target-module at b0000 { /* 0x481b0000, ap 58 50.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xb0000 0x10000>;
+ };
+
+ target-module at cc000 { /* 0x481cc000, ap 60 46.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xcc020 0x4>;
+ reg-names = "rev";
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
+ <&dcan0_fck>;
+ clock-names = "fck", "osc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xcc000 0x2000>;
+
+ dcan0: can at 0 {
+ compatible = "ti,am3352-d_can";
+ reg = <0x0 0x2000>;
+ clocks = <&dcan0_fck>;
+ clock-names = "fck";
+ syscon-raminit = <&scm_conf 0x644 0>;
+ interrupts = <52>;
+ status = "disabled";
+ };
+ };
+
+ target-module at d0000 { /* 0x481d0000, ap 62 42.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xd0020 0x4>;
+ reg-names = "rev";
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
+ <&dcan1_fck>;
+ clock-names = "fck", "osc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd0000 0x2000>;
+
+ dcan1: can at 0 {
+ compatible = "ti,am3352-d_can";
+ reg = <0x0 0x2000>;
+ clocks = <&dcan1_fck>;
+ clock-names = "fck";
+ syscon-raminit = <&scm_conf 0x644 1>;
+ interrupts = <55>;
+ status = "disabled";
+ };
+ };
+
+ target-module at d8000 { /* 0x481d8000, ap 64 66.0 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0xd82fc 0x4>,
+ <0xd8110 0x4>,
+ <0xd8114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xd8000 0x1000>;
+ };
+ };
+
+ segment at 200000 { /* 0x48200000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ segment at 300000 { /* 0x48300000 */
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */
+ <0x00001000 0x00301000 0x001000>, /* ap 67 */
+ <0x00002000 0x00302000 0x001000>, /* ap 68 */
+ <0x00003000 0x00303000 0x001000>, /* ap 69 */
+ <0x00004000 0x00304000 0x001000>, /* ap 70 */
+ <0x00005000 0x00305000 0x001000>, /* ap 71 */
+ <0x0000e000 0x0030e000 0x001000>, /* ap 72 */
+ <0x0000f000 0x0030f000 0x001000>, /* ap 73 */
+ <0x00018000 0x00318000 0x004000>, /* ap 74 */
+ <0x0001c000 0x0031c000 0x001000>, /* ap 75 */
+ <0x00010000 0x00310000 0x002000>, /* ap 76 */
+ <0x00012000 0x00312000 0x001000>, /* ap 93 */
+ <0x00015000 0x00315000 0x001000>, /* ap 94 */
+ <0x00016000 0x00316000 0x001000>, /* ap 95 */
+ <0x00017000 0x00317000 0x001000>, /* ap 96 */
+ <0x00013000 0x00313000 0x001000>, /* ap 97 */
+ <0x00014000 0x00314000 0x001000>, /* ap 98 */
+ <0x00020000 0x00320000 0x001000>, /* ap 99 */
+ <0x00021000 0x00321000 0x001000>, /* ap 100 */
+ <0x00022000 0x00322000 0x001000>, /* ap 101 */
+ <0x00023000 0x00323000 0x001000>, /* ap 102 */
+ <0x00024000 0x00324000 0x001000>, /* ap 103 */
+ <0x00025000 0x00325000 0x001000>; /* ap 104 */
+
+ target-module at 0 { /* 0x48300000, ap 66 48.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x0 0x4>,
+ <0x4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1000>;
+
+ epwmss0: epwmss at 0 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0 0 0x1000>;
+
+ ecap0: ecap at 100 {
+ compatible = "ti,am3352-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x100 0x80>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+ interrupts = <31>;
+ interrupt-names = "ecap0";
+ status = "disabled";
+ };
+
+ ehrpwm0: pwm at 200 {
+ compatible = "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module at 2000 { /* 0x48302000, ap 68 52.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x2000 0x4>,
+ <0x2004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2000 0x1000>;
+
+ epwmss1: epwmss at 0 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0 0 0x1000>;
+
+ ecap1: ecap at 100 {
+ compatible = "ti,am3352-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x100 0x80>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+ interrupts = <47>;
+ interrupt-names = "ecap1";
+ status = "disabled";
+ };
+
+ ehrpwm1: pwm at 200 {
+ compatible = "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module at 4000 { /* 0x48304000, ap 70 44.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x4000 0x4>,
+ <0x4004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ epwmss2: epwmss at 0 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x0 0x10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0 0 0x1000>;
+
+ ecap2: ecap at 100 {
+ compatible = "ti,am3352-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x100 0x80>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+ interrupts = <61>;
+ interrupt-names = "ecap2";
+ status = "disabled";
+ };
+
+ ehrpwm2: pwm at 200 {
+ compatible = "ti,am3352-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x200 0x80>;
+ clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ status = "disabled";
+ };
+ };
+ };
+
+ target-module at e000 { /* 0x4830e000, ap 72 4a.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0xe000 0x4>,
+ <0xe054 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ /* Domains (P, C): per_pwrdm, lcdc_clkdm */
+ clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0xe000 0x1000>;
+
+ lcdc: lcdc at 0 {
+ compatible = "ti,am33xx-tilcdc";
+ reg = <0x0 0x1000>;
+ interrupts = <36>;
+ status = "disabled";
+ };
+ };
+
+ target-module at 10000 { /* 0x48310000, ap 76 4e.1 */
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x11fe0 0x4>,
+ <0x11fe4 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ /* Domains (P, C): per_pwrdm, l4ls_clkdm */
+ clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10000 0x2000>;
+
+ rng: rng at 0 {
+ compatible = "ti,omap4-rng";
+ reg = <0x0 0x2000>;
+ interrupts = <111>;
+ };
+ };
+
+ target-module at 13000 { /* 0x48313000, ap 97 62.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x13000 0x1000>;
+ };
+
+ target-module at 15000 { /* 0x48315000, ap 94 56.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00015000 0x00001000>,
+ <0x00001000 0x00016000 0x00001000>;
+ };
+
+ target-module at 18000 { /* 0x48318000, ap 74 4c.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000 0x4000>;
+ };
+
+ target-module at 20000 { /* 0x48320000, ap 99 34.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+ };
+
+ target-module at 22000 { /* 0x48322000, ap 101 3e.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x22000 0x1000>;
+ };
+
+ target-module at 24000 { /* 0x48324000, ap 103 68.0 */
+ compatible = "ti,sysc";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x24000 0x1000>;
+ };
+ };
+};
diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi
index d3dd6a16e7..3e5ed00aae 100644
--- a/arch/arm/dts/am33xx.dtsi
+++ b/arch/arm/dts/am33xx.dtsi
@@ -8,6 +8,7 @@
* kind, whether express or implied.
*/
+#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
#include <dt-bindings/clock/am3.h>
@@ -46,6 +47,7 @@
#size-cells = <0>;
cpu at 0 {
compatible = "arm,cortex-a8";
+ enable-method = "ti,am3352";
device_type = "cpu";
reg = <0>;
@@ -55,6 +57,17 @@
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
+ cpu-idle-states = <&mpu_gate>;
+ };
+
+ idle-states {
+ mpu_gate: mpu_gate {
+ compatible = "arm,idle-state";
+ entry-latency-us = <40>;
+ exit-latency-us = <90>;
+ min-residency-us = <300>;
+ ti,idle-wkup-m3;
+ };
};
};
@@ -167,11 +180,6 @@
ti,hwmods = "l3_main";
l4_wkup: l4_wkup at 44c00000 {
- compatible = "ti,am3-l4-wkup", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x44c00000 0x280000>;
-
wkup_m3: wkup_m3 at 100000 {
compatible = "ti,am3352-wkup-m3";
reg = <0x100000 0x4000>,
@@ -180,73 +188,14 @@
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
-
- prcm: prcm at 200000 {
- compatible = "ti,am3-prcm", "simple-bus";
- reg = <0x200000 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x200000 0x4000>;
-
- prcm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prcm_clockdomains: clockdomains {
- };
- };
-
- scm: scm at 210000 {
- compatible = "ti,am3-scm", "simple-bus";
- reg = <0x210000 0x2000>;
- #address-cells = <1>;
- #size-cells = <1>;
- #pinctrl-cells = <1>;
- ranges = <0 0x210000 0x2000>;
-
- am33xx_pinmux: pinmux at 800 {
- compatible = "pinctrl-single";
- reg = <0x800 0x238>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x7f>;
- };
-
- scm_conf: scm_conf at 0 {
- compatible = "syscon", "simple-bus";
- reg = <0x0 0x800>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x800>;
-
- scm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- wkup_m3_ipc: wkup_m3_ipc at 1324 {
- compatible = "ti,am3352-wkup-m3-ipc";
- reg = <0x1324 0x24>;
- interrupts = <78>;
- ti,rproc = <&wkup_m3>;
- mboxes = <&mailbox &mbox_wkupm3>;
- };
-
- edma_xbar: dma-router at f90 {
- compatible = "ti,am335x-edma-crossbar";
- reg = <0xf90 0x40>;
- #dma-cells = <3>;
- dma-requests = <32>;
- dma-masters = <&edma>;
- };
-
- scm_clockdomains: clockdomains {
- };
- };
+ };
+ l4_per: interconnect at 48000000 {
+ };
+ l4_fw: interconnect at 47c00000 {
+ };
+ l4_fast: interconnect at 4a000000 {
+ };
+ l4_mpuss: interconnect at 4b140000 {
};
intc: interrupt-controller at 48200000 {
@@ -256,45 +205,100 @@
reg = <0x48200000 0x1000>;
};
- edma: edma at 49000000 {
- compatible = "ti,edma3-tpcc";
- ti,hwmods = "tpcc";
- reg = <0x49000000 0x10000>;
- reg-names = "edma3_cc";
- interrupts = <12 13 14>;
- interrupt-names = "edma3_ccint", "edma3_mperr",
- "edma3_ccerrint";
- dma-requests = <64>;
- #dma-cells = <2>;
-
- ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
- <&edma_tptc2 0>;
-
- ti,edma-memcpy-channels = <20 21>;
+ target-module at 49000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49000000 0x4>;
+ reg-names = "rev";
+ clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49000000 0x10000>;
+
+ edma: dma at 0 {
+ compatible = "ti,edma3-tpcc";
+ reg = <0 0x10000>;
+ reg-names = "edma3_cc";
+ interrupts = <12 13 14>;
+ interrupt-names = "edma3_ccint", "edma3_mperr",
+ "edma3_ccerrint";
+ dma-requests = <64>;
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
+ <&edma_tptc2 0>;
+
+ ti,edma-memcpy-channels = <20 21>;
+ };
};
- edma_tptc0: tptc at 49800000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc0";
- reg = <0x49800000 0x100000>;
- interrupts = <112>;
- interrupt-names = "edma3_tcerrint";
+ target-module at 49800000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49800000 0x4>,
+ <0x49800010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49800000 0x100000>;
+
+ edma_tptc0: dma at 0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <112>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
- edma_tptc1: tptc at 49900000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc1";
- reg = <0x49900000 0x100000>;
- interrupts = <113>;
- interrupt-names = "edma3_tcerrint";
+ target-module at 49900000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49900000 0x4>,
+ <0x49900010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49900000 0x100000>;
+
+ edma_tptc1: dma at 0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <113>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
- edma_tptc2: tptc at 49a00000 {
- compatible = "ti,edma3-tptc";
- ti,hwmods = "tptc2";
- reg = <0x49a00000 0x100000>;
- interrupts = <114>;
- interrupt-names = "edma3_tcerrint";
+ target-module at 49a00000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x49a00000 0x4>,
+ <0x49a00010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49a00000 0x100000>;
+
+ edma_tptc2: dma at 0 {
+ compatible = "ti,edma3-tptc";
+ reg = <0 0x100000>;
+ interrupts = <114>;
+ interrupt-names = "edma3_tcerrint";
+ };
};
gpio0: gpio at 44e07000 {
@@ -341,66 +345,6 @@
interrupts = <62>;
};
- uart0: serial at 44e09000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart1";
- clock-frequency = <48000000>;
- reg = <0x44e09000 0x2000>;
- interrupts = <72>;
- status = "disabled";
- dmas = <&edma 26 0>, <&edma 27 0>;
- dma-names = "tx", "rx";
- };
-
- uart1: serial at 48022000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart2";
- clock-frequency = <48000000>;
- reg = <0x48022000 0x2000>;
- interrupts = <73>;
- status = "disabled";
- dmas = <&edma 28 0>, <&edma 29 0>;
- dma-names = "tx", "rx";
- };
-
- uart2: serial at 48024000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart3";
- clock-frequency = <48000000>;
- reg = <0x48024000 0x2000>;
- interrupts = <74>;
- status = "disabled";
- dmas = <&edma 30 0>, <&edma 31 0>;
- dma-names = "tx", "rx";
- };
-
- uart3: serial at 481a6000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart4";
- clock-frequency = <48000000>;
- reg = <0x481a6000 0x2000>;
- interrupts = <44>;
- status = "disabled";
- };
-
- uart4: serial at 481a8000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart5";
- clock-frequency = <48000000>;
- reg = <0x481a8000 0x2000>;
- interrupts = <45>;
- status = "disabled";
- };
-
- uart5: serial at 481aa000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart6";
- clock-frequency = <48000000>;
- reg = <0x481aa000 0x2000>;
- interrupts = <46>;
- status = "disabled";
- };
-
i2c0: i2c at 44e0b000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
@@ -466,13 +410,6 @@
status = "disabled";
};
- hwspinlock: spinlock at 480ca000 {
- compatible = "ti,omap4-hwspinlock";
- reg = <0x480ca000 0x1000>;
- ti,hwmods = "spinlock";
- #hwlock-cells = <1>;
- };
-
wdt2: wdt at 44e35000 {
compatible = "ti,omap3-wdt";
ti,hwmods = "wd_timer2";
@@ -480,143 +417,6 @@
interrupts = <91>;
};
- dcan0: can at 481cc000 {
- compatible = "ti,am3352-d_can";
- ti,hwmods = "d_can0";
- reg = <0x481cc000 0x2000>;
- clocks = <&dcan0_fck>;
- clock-names = "fck";
- syscon-raminit = <&scm_conf 0x644 0>;
- interrupts = <52>;
- status = "disabled";
- };
-
- dcan1: can at 481d0000 {
- compatible = "ti,am3352-d_can";
- ti,hwmods = "d_can1";
- reg = <0x481d0000 0x2000>;
- clocks = <&dcan1_fck>;
- clock-names = "fck";
- syscon-raminit = <&scm_conf 0x644 1>;
- interrupts = <55>;
- status = "disabled";
- };
-
- mailbox: mailbox at 480c8000 {
- compatible = "ti,omap4-mailbox";
- reg = <0x480C8000 0x200>;
- interrupts = <77>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <8>;
- mbox_wkupm3: wkup_m3 {
- ti,mbox-send-noirq;
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <0 0 3>;
- };
- };
-
- timer1: timer at 44e31000 {
- compatible = "ti,am335x-timer-1ms";
- reg = <0x44e31000 0x400>;
- interrupts = <67>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
- clocks = <&timer1_fck>;
- clock-names = "fck";
- };
-
- timer2: timer at 48040000 {
- compatible = "ti,am335x-timer";
- reg = <0x48040000 0x400>;
- interrupts = <68>;
- ti,hwmods = "timer2";
- clocks = <&timer2_fck>;
- clock-names = "fck";
- };
-
- timer3: timer at 48042000 {
- compatible = "ti,am335x-timer";
- reg = <0x48042000 0x400>;
- interrupts = <69>;
- ti,hwmods = "timer3";
- };
-
- timer4: timer at 48044000 {
- compatible = "ti,am335x-timer";
- reg = <0x48044000 0x400>;
- interrupts = <92>;
- ti,hwmods = "timer4";
- ti,timer-pwm;
- };
-
- timer5: timer at 48046000 {
- compatible = "ti,am335x-timer";
- reg = <0x48046000 0x400>;
- interrupts = <93>;
- ti,hwmods = "timer5";
- ti,timer-pwm;
- };
-
- timer6: timer at 48048000 {
- compatible = "ti,am335x-timer";
- reg = <0x48048000 0x400>;
- interrupts = <94>;
- ti,hwmods = "timer6";
- ti,timer-pwm;
- };
-
- timer7: timer at 4804a000 {
- compatible = "ti,am335x-timer";
- reg = <0x4804a000 0x400>;
- interrupts = <95>;
- ti,hwmods = "timer7";
- ti,timer-pwm;
- };
-
- rtc: rtc at 44e3e000 {
- compatible = "ti,am3352-rtc", "ti,da830-rtc";
- reg = <0x44e3e000 0x1000>;
- interrupts = <75
- 76>;
- ti,hwmods = "rtc";
- clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
- clock-names = "int-clk";
- };
-
- spi0: spi at 48030000 {
- compatible = "ti,omap4-mcspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x48030000 0x400>;
- interrupts = <65>;
- ti,spi-num-cs = <2>;
- ti,hwmods = "spi0";
- dmas = <&edma 16 0
- &edma 17 0
- &edma 18 0
- &edma 19 0>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- status = "disabled";
- };
-
- spi1: spi at 481a0000 {
- compatible = "ti,omap4-mcspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x481a0000 0x400>;
- interrupts = <125>;
- ti,spi-num-cs = <2>;
- ti,hwmods = "spi1";
- dmas = <&edma 42 0
- &edma 43 0
- &edma 44 0
- &edma 45 0>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- status = "disabled";
- };
-
usb: usb at 47400000 {
compatible = "ti,am33xx-usb";
reg = <0x47400000 0x1000>;
@@ -731,121 +531,18 @@
"tx14", "tx15";
};
- cppi41dma: dma-controller at 47402000 {
+ cppi41dma: dma-controller at 2000 {
compatible = "ti,am3359-cppi41";
- reg = <0x47400000 0x1000
- 0x47402000 0x1000
- 0x47403000 0x1000
- 0x47404000 0x4000>;
+ reg = <0x0000 0x1000>,
+ <0x2000 0x1000>,
+ <0x3000 0x1000>,
+ <0x4000 0x4000>;
reg-names = "glue", "controller", "scheduler", "queuemgr";
interrupts = <17>;
interrupt-names = "glue";
#dma-cells = <2>;
#dma-channels = <30>;
#dma-requests = <256>;
- status = "disabled";
- };
- };
-
- epwmss0: epwmss at 48300000 {
- compatible = "ti,am33xx-pwmss";
- reg = <0x48300000 0x10>;
- ti,hwmods = "epwmss0";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
- ranges = <0x48300100 0x48300100 0x80 /* ECAP */
- 0x48300180 0x48300180 0x80 /* EQEP */
- 0x48300200 0x48300200 0x80>; /* EHRPWM */
-
- ecap0: ecap at 48300100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x48300100 0x80>;
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
- interrupts = <31>;
- interrupt-names = "ecap0";
- status = "disabled";
- };
-
- ehrpwm0: pwm at 48300200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48300200 0x80>;
- clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
- };
-
- epwmss1: epwmss at 48302000 {
- compatible = "ti,am33xx-pwmss";
- reg = <0x48302000 0x10>;
- ti,hwmods = "epwmss1";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
- ranges = <0x48302100 0x48302100 0x80 /* ECAP */
- 0x48302180 0x48302180 0x80 /* EQEP */
- 0x48302200 0x48302200 0x80>; /* EHRPWM */
-
- ecap1: ecap at 48302100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x48302100 0x80>;
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
- interrupts = <47>;
- interrupt-names = "ecap1";
- status = "disabled";
- };
-
- ehrpwm1: pwm at 48302200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48302200 0x80>;
- clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
- };
- };
-
- epwmss2: epwmss at 48304000 {
- compatible = "ti,am33xx-pwmss";
- reg = <0x48304000 0x10>;
- ti,hwmods = "epwmss2";
- #address-cells = <1>;
- #size-cells = <1>;
- status = "disabled";
- ranges = <0x48304100 0x48304100 0x80 /* ECAP */
- 0x48304180 0x48304180 0x80 /* EQEP */
- 0x48304200 0x48304200 0x80>; /* EHRPWM */
-
- ecap2: ecap at 48304100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x48304100 0x80>;
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
- interrupts = <61>;
- interrupt-names = "ecap2";
- status = "disabled";
- };
-
- ehrpwm2: pwm at 48304200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48304200 0x80>;
- clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- status = "disabled";
};
};
@@ -904,60 +601,26 @@
};
};
- ocmcram: ocmcram at 40300000 {
+ ocmcram: sram at 40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x10000>; /* 64k */
ranges = <0x0 0x40300000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
- pm_sram_code: pm-sram-code at 0 {
+ pm_sram_code: pm-code-sram at 0 {
compatible = "ti,sram";
reg = <0x0 0x1000>;
protect-exec;
};
- pm_sram_data: pm-sram-data at 1000 {
+ pm_sram_data: pm-data-sram at 1000 {
compatible = "ti,sram";
reg = <0x1000 0x1000>;
pool;
};
};
- elm: elm at 48080000 {
- compatible = "ti,am3352-elm";
- reg = <0x48080000 0x2000>;
- interrupts = <4>;
- ti,hwmods = "elm";
- status = "disabled";
- };
-
- lcdc: lcdc at 4830e000 {
- compatible = "ti,am33xx-tilcdc";
- reg = <0x4830e000 0x1000>;
- interrupts = <36>;
- ti,hwmods = "lcdc";
- status = "disabled";
- };
-
- tscadc: tscadc at 44e0d000 {
- compatible = "ti,am3359-tscadc";
- reg = <0x44e0d000 0x1000>;
- interrupts = <16>;
- ti,hwmods = "adc_tsc";
- status = "disabled";
- dmas = <&edma 53 0>, <&edma 57 0>;
- dma-names = "fifo0", "fifo1";
-
- tsc {
- compatible = "ti,am3359-tsc";
- };
- am335x_adc: adc {
- #io-channel-cells = <1>;
- compatible = "ti,am3359-adc";
- };
- };
-
emif: emif at 4c000000 {
compatible = "ti,emif-am3352";
reg = <0x4c000000 0x1000000>;
@@ -987,60 +650,116 @@
status = "disabled";
};
- sham: sham at 53100000 {
- compatible = "ti,omap4-sham";
- ti,hwmods = "sham";
- reg = <0x53100000 0x200>;
- interrupts = <109>;
- dmas = <&edma 36 0>;
- dma-names = "rx";
- };
-
- aes: aes at 53500000 {
- compatible = "ti,omap4-aes";
- ti,hwmods = "aes";
- reg = <0x53500000 0xa0>;
- interrupts = <103>;
- dmas = <&edma 6 0>,
- <&edma 5 0>;
- dma-names = "tx", "rx";
+ sham_target: target-module at 53100000 {
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
+ reg = <0x53100100 0x4>,
+ <0x53100110 0x4>,
+ <0x53100114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53100000 0x1000>;
+
+ sham: sham at 0 {
+ compatible = "ti,omap4-sham";
+ reg = <0 0x200>;
+ interrupts = <109>;
+ dmas = <&edma 36 0>;
+ dma-names = "rx";
+ };
};
- mcasp0: mcasp at 48038000 {
- compatible = "ti,am33xx-mcasp-audio";
- ti,hwmods = "mcasp0";
- reg = <0x48038000 0x2000>,
- <0x46000000 0x400000>;
- reg-names = "mpu", "dat";
- interrupts = <80>, <81>;
- interrupt-names = "tx", "rx";
- status = "disabled";
- dmas = <&edma 8 2>,
- <&edma 9 2>;
- dma-names = "tx", "rx";
+ aes_target: target-module at 53500000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x53500080 0x4>,
+ <0x53500084 0x4>,
+ <0x53500088 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,syss-mask = <1>;
+ /* Domains (P, C): per_pwrdm, l3_clkdm */
+ clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x53500000 0x1000>;
+
+ aes: aes at 0 {
+ compatible = "ti,omap4-aes";
+ reg = <0 0xa0>;
+ interrupts = <103>;
+ dmas = <&edma 6 0>,
+ <&edma 5 0>;
+ dma-names = "tx", "rx";
+ };
};
- mcasp1: mcasp at 4803c000 {
- compatible = "ti,am33xx-mcasp-audio";
- ti,hwmods = "mcasp1";
- reg = <0x4803C000 0x2000>,
- <0x46400000 0x400000>;
- reg-names = "mpu", "dat";
- interrupts = <82>, <83>;
- interrupt-names = "tx", "rx";
- status = "disabled";
- dmas = <&edma 10 2>,
- <&edma 11 2>;
- dma-names = "tx", "rx";
- };
+ target-module at 56000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x5600fe00 0x4>,
+ <0x5600fe10 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
+ clock-names = "fck";
+ resets = <&prm_gfx 0>;
+ reset-names = "rstctrl";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x56000000 0x1000000>;
- rng: rng at 48310000 {
- compatible = "ti,omap4-rng";
- ti,hwmods = "rng";
- reg = <0x48310000 0x2000>;
- interrupts = <111>;
+ /*
+ * Closed source PowerVR driver, no child device
+ * binding or driver in mainline
+ */
};
};
};
+#include "am33xx-l4.dtsi"
#include "am33xx-clocks.dtsi"
+
+&prcm {
+ prm_per: prm at c00 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0xc00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_wkup: prm at d00 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0xd00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_device: prm at f00 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0xf00 0x100>;
+ #reset-cells = <1>;
+ };
+
+ prm_gfx: prm at 1100 {
+ compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
+ reg = <0x1100 0x100>;
+ #reset-cells = <1>;
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 05/28] clk: add clk_round_rate()
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
` (3 preceding siblings ...)
2020-12-24 7:25 ` [PATCH v7 04/28] arm: dts: sync am33xx with Linux 5.9-rc7 Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 06/28] clk: ti: add mux clock driver Dario Binacchi
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
It returns the rate which will be set if you ask clk_set_rate() to set
that rate. It provides a way to query exactly what rate you'll get if
you call clk_set_rate() with that same argument.
So essentially, clk_round_rate() and clk_set_rate() are equivalent
except the former does not modify the clock hardware in any way.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
---
(no changes since v4)
Changes in v4:
- Update clk_round_rate description.
- Add Sean Anderson review.
arch/sandbox/include/asm/clk.h | 9 +++++++++
drivers/clk/clk-uclass.c | 15 +++++++++++++++
drivers/clk/clk_sandbox.c | 17 +++++++++++++++++
drivers/clk/clk_sandbox_test.c | 10 ++++++++++
include/clk-uclass.h | 8 ++++++++
include/clk.h | 28 ++++++++++++++++++++++++++++
test/dm/clk.c | 22 ++++++++++++++++++++++
7 files changed, 109 insertions(+)
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
index c184c4bffc..0294baee27 100644
--- a/arch/sandbox/include/asm/clk.h
+++ b/arch/sandbox/include/asm/clk.h
@@ -105,6 +105,15 @@ int sandbox_clk_test_get_bulk(struct udevice *dev);
* @return: The rate of the clock.
*/
ulong sandbox_clk_test_get_rate(struct udevice *dev, int id);
+/**
+ * sandbox_clk_test_round_rate - Ask the sandbox clock test device to round a
+ * clock's rate.
+ *
+ * @dev: The sandbox clock test (client) device.
+ * @id: The test device's clock ID to configure.
+ * @return: The rounded rate of the clock.
+ */
+ulong sandbox_clk_test_round_rate(struct udevice *dev, int id, ulong rate);
/**
* sandbox_clk_test_set_rate - Ask the sandbox clock test device to set a
* clock's rate.
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index ac954a34d2..3b8e27e4a5 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -523,6 +523,21 @@ long long clk_get_parent_rate(struct clk *clk)
return pclk->rate;
}
+ulong clk_round_rate(struct clk *clk, ulong rate)
+{
+ const struct clk_ops *ops;
+
+ debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
+ if (!clk_valid(clk))
+ return 0;
+
+ ops = clk_dev_ops(clk->dev);
+ if (!ops->round_rate)
+ return -ENOSYS;
+
+ return ops->round_rate(clk, rate);
+}
+
ulong clk_set_rate(struct clk *clk, ulong rate)
{
const struct clk_ops *ops;
diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c
index 0ff1b49633..0751e923e7 100644
--- a/drivers/clk/clk_sandbox.c
+++ b/drivers/clk/clk_sandbox.c
@@ -30,6 +30,22 @@ static ulong sandbox_clk_get_rate(struct clk *clk)
return priv->rate[clk->id];
}
+static ulong sandbox_clk_round_rate(struct clk *clk, ulong rate)
+{
+ struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (!priv->probed)
+ return -ENODEV;
+
+ if (clk->id >= SANDBOX_CLK_ID_COUNT)
+ return -EINVAL;
+
+ if (!rate)
+ return -EINVAL;
+
+ return rate;
+}
+
static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate)
{
struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
@@ -103,6 +119,7 @@ static int sandbox_clk_free(struct clk *clk)
}
static struct clk_ops sandbox_clk_ops = {
+ .round_rate = sandbox_clk_round_rate,
.get_rate = sandbox_clk_get_rate,
.set_rate = sandbox_clk_set_rate,
.enable = sandbox_clk_enable,
diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c
index 873383856f..f7b77aa674 100644
--- a/drivers/clk/clk_sandbox_test.c
+++ b/drivers/clk/clk_sandbox_test.c
@@ -86,6 +86,16 @@ ulong sandbox_clk_test_get_rate(struct udevice *dev, int id)
return clk_get_rate(sbct->clkps[id]);
}
+ulong sandbox_clk_test_round_rate(struct udevice *dev, int id, ulong rate)
+{
+ struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+ if (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)
+ return -EINVAL;
+
+ return clk_round_rate(sbct->clkps[id], rate);
+}
+
ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate)
{
struct sandbox_clk_test *sbct = dev_get_priv(dev);
diff --git a/include/clk-uclass.h b/include/clk-uclass.h
index dac42dab36..50e8681b55 100644
--- a/include/clk-uclass.h
+++ b/include/clk-uclass.h
@@ -61,6 +61,14 @@ struct clk_ops {
* @return 0 if OK, or a negative error code.
*/
int (*rfree)(struct clk *clock);
+ /**
+ * round_rate() - Adjust a rate to the exact rate a clock can provide.
+ *
+ * @clk: The clock to manipulate.
+ * @rate: Desidered clock rate in Hz.
+ * @return rounded rate in Hz, or -ve error code.
+ */
+ ulong (*round_rate)(struct clk *clk, ulong rate);
/**
* get_rate() - Get current clock rate.
*
diff --git a/include/clk.h b/include/clk.h
index a62e2efa2c..ca6b85fa6f 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -366,6 +366,29 @@ struct clk *clk_get_parent(struct clk *clk);
*/
long long clk_get_parent_rate(struct clk *clk);
+/**
+ * clk_round_rate() - Adjust a rate to the exact rate a clock can provide
+ *
+ * This answers the question "if I were to pass @rate to clk_set_rate(),
+ * what clock rate would I end up with?" without changing the hardware
+ * in any way. In other words:
+ *
+ * rate = clk_round_rate(clk, r);
+ *
+ * and:
+ *
+ * rate = clk_set_rate(clk, r);
+ *
+ * are equivalent except the former does not modify the clock hardware
+ * in any way.
+ *
+ * @clk: A clock struct that was previously successfully requested by
+ * clk_request/get_by_*().
+ * @rate: desired clock rate in Hz.
+ * @return rounded rate in Hz, or -ve error code.
+ */
+ulong clk_round_rate(struct clk *clk, ulong rate);
+
/**
* clk_set_rate() - Set current clock rate.
*
@@ -482,6 +505,11 @@ static inline long long clk_get_parent_rate(struct clk *clk)
return -ENOSYS;
}
+static inline ulong clk_round_rate(struct clk *clk, ulong rate)
+{
+ return -ENOSYS;
+}
+
static inline ulong clk_set_rate(struct clk *clk, ulong rate)
{
return -ENOSYS;
diff --git a/test/dm/clk.c b/test/dm/clk.c
index edca3b49f6..21997ed892 100644
--- a/test/dm/clk.c
+++ b/test/dm/clk.c
@@ -112,6 +112,28 @@ static int dm_test_clk(struct unit_test_state *uts)
rate = sandbox_clk_test_set_rate(dev_test, SANDBOX_CLK_TEST_ID_I2C, 0);
ut_assert(IS_ERR_VALUE(rate));
+ ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
+ SANDBOX_CLK_TEST_ID_SPI));
+ ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
+ SANDBOX_CLK_TEST_ID_I2C));
+
+ ut_asserteq(5000, sandbox_clk_test_round_rate(dev_test,
+ SANDBOX_CLK_TEST_ID_SPI,
+ 5000));
+ ut_asserteq(7000, sandbox_clk_test_round_rate(dev_test,
+ SANDBOX_CLK_TEST_ID_I2C,
+ 7000));
+
+ ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
+ SANDBOX_CLK_TEST_ID_SPI));
+ ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
+ SANDBOX_CLK_TEST_ID_I2C));
+
+ rate = sandbox_clk_test_round_rate(dev_test, SANDBOX_CLK_TEST_ID_SPI, 0);
+ ut_assert(IS_ERR_VALUE(rate));
+ rate = sandbox_clk_test_round_rate(dev_test, SANDBOX_CLK_TEST_ID_I2C, 0);
+ ut_assert(IS_ERR_VALUE(rate));
+
ut_asserteq(10000, sandbox_clk_test_get_rate(dev_test,
SANDBOX_CLK_TEST_ID_SPI));
ut_asserteq(20000, sandbox_clk_test_get_rate(dev_test,
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 06/28] clk: ti: add mux clock driver
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
` (4 preceding siblings ...)
2020-12-24 7:25 ` [PATCH v7 05/28] clk: add clk_round_rate() Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 07/28] arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macro Dario Binacchi
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
The driver manages a register-mapped multiplexer with multiple input
clock signals or parents, one of which can be selected as output. It
uses routines provided by the common clock framework (ccf).
The code is based on the drivers/clk/ti/mux.c driver of the Linux
kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/mux.txt
Signed-off-by: Dario Binacchi <dariobin@libero.it>
---
(no changes since v5)
Changes in v5:
- Create drivers/clk/ti directory.
- Move the clk-ti-mux.c file to drivers/clk/ti and rename it clk-mux.c
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
Changes in v3:
- Remove doc/device-tree-bindings/clock/clock-bindings.txt.
- Remove doc/device-tree-bindings/clock/ti,mux.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/ti/Kconfig | 10 ++
drivers/clk/ti/Makefile | 6 +
drivers/clk/ti/clk-mux.c | 276 +++++++++++++++++++++++++++++++++++++++
5 files changed, 294 insertions(+)
create mode 100644 drivers/clk/ti/Kconfig
create mode 100644 drivers/clk/ti/Makefile
create mode 100644 drivers/clk/ti/clk-mux.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4dfbad7986..9e54929039 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -179,6 +179,7 @@ source "drivers/clk/renesas/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sifive/Kconfig"
source "drivers/clk/tegra/Kconfig"
+source "drivers/clk/ti/Kconfig"
source "drivers/clk/uniphier/Kconfig"
config ICS8N3QV01
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d1e295ac7c..2581fe0a19 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
obj-y += analogbits/
obj-y += imx/
obj-y += tegra/
+obj-y += ti/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
new file mode 100644
index 0000000000..be4f26817f
--- /dev/null
+++ b/drivers/clk/ti/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+#
+
+config CLK_TI_MUX
+ bool "TI mux clock driver"
+ depends on CLK && OF_CONTROL && CLK_CCF
+ help
+ This enables the mux clock driver support on TI's SoCs.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
new file mode 100644
index 0000000000..5faf68d30e
--- /dev/null
+++ b/drivers/clk/ti/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+#
+
+obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
diff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c
new file mode 100644
index 0000000000..9720c84513
--- /dev/null
+++ b/drivers/clk/ti/clk-mux.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI multiplexer clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ *
+ * Based on Linux kernel drivers/clk/ti/mux.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <clk-uclass.h>
+#include <asm/io.h>
+#include <linux/clk-provider.h>
+
+struct clk_ti_mux_priv {
+ struct clk_bulk parents;
+ fdt_addr_t reg;
+ u32 flags;
+ u32 mux_flags;
+ u32 mask;
+ u32 shift;
+ s32 latch;
+};
+
+static void clk_ti_mux_rmw(u32 val, u32 mask, fdt_addr_t reg)
+{
+ u32 v;
+
+ v = readl(reg);
+ v &= ~mask;
+ v |= val;
+ writel(v, reg);
+}
+
+static void clk_ti_mux_latch(fdt_addr_t reg, s8 shift)
+{
+ u32 latch;
+
+ if (shift < 0)
+ return;
+
+ latch = 1 << shift;
+
+ clk_ti_mux_rmw(latch, latch, reg);
+ clk_ti_mux_rmw(0, latch, reg);
+ readl(reg); /* OCP barrier */
+}
+
+static struct clk *clk_ti_mux_get_parent_by_index(struct clk_bulk *parents,
+ int index)
+{
+ if (index < 0 || !parents)
+ return ERR_PTR(-EINVAL);
+
+ if (index >= parents->count)
+ return ERR_PTR(-ENODEV);
+
+ return &parents->clks[index];
+}
+
+static int clk_ti_mux_get_parent_index(struct clk_bulk *parents,
+ struct clk *parent)
+{
+ int i;
+
+ if (!parents || !parent)
+ return -EINVAL;
+
+ for (i = 0; i < parents->count; i++) {
+ if (parents->clks[i].dev == parent->dev)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+static int clk_ti_mux_get_index(struct clk *clk)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ u32 val;
+
+ val = readl(priv->reg);
+ val >>= priv->shift;
+ val &= priv->mask;
+
+ if (val && (priv->flags & CLK_MUX_INDEX_BIT))
+ val = ffs(val) - 1;
+
+ if (val && (priv->flags & CLK_MUX_INDEX_ONE))
+ val--;
+
+ if (val >= priv->parents.count)
+ return -EINVAL;
+
+ return val;
+}
+
+static int clk_ti_mux_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ int index;
+ u32 val;
+
+ index = clk_ti_mux_get_parent_index(&priv->parents, parent);
+ if (index < 0) {
+ dev_err(clk->dev, "failed to get parent clock\n");
+ return index;
+ }
+
+ index = clk_mux_index_to_val(NULL, priv->flags, index);
+
+ if (priv->flags & CLK_MUX_HIWORD_MASK) {
+ val = priv->mask << (priv->shift + 16);
+ } else {
+ val = readl(priv->reg);
+ val &= ~(priv->mask << priv->shift);
+ }
+
+ val |= index << priv->shift;
+ writel(val, priv->reg);
+ clk_ti_mux_latch(priv->reg, priv->latch);
+ return 0;
+}
+
+static ulong clk_ti_mux_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ struct clk *parent;
+ int index;
+
+ if ((clk->flags & CLK_SET_RATE_PARENT) == 0)
+ return -ENOSYS;
+
+ index = clk_ti_mux_get_index(clk);
+ parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
+ if (IS_ERR(parent))
+ return PTR_ERR(parent);
+
+ rate = clk_set_rate(parent, rate);
+ dev_dbg(clk->dev, "rate=%ld\n", rate);
+ return rate;
+}
+
+static ulong clk_ti_mux_get_rate(struct clk *clk)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ int index;
+ struct clk *parent;
+ ulong rate;
+
+ index = clk_ti_mux_get_index(clk);
+ parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
+ if (IS_ERR(parent))
+ return PTR_ERR(parent);
+
+ rate = clk_get_rate(parent);
+ dev_dbg(clk->dev, "rate=%ld\n", rate);
+ return rate;
+}
+
+static ulong clk_ti_mux_round_rate(struct clk *clk, ulong rate)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ struct clk *parent;
+ int index;
+
+ if ((clk->flags & CLK_SET_RATE_PARENT) == 0)
+ return -ENOSYS;
+
+ index = clk_ti_mux_get_index(clk);
+ parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
+ if (IS_ERR(parent))
+ return PTR_ERR(parent);
+
+ rate = clk_round_rate(parent, rate);
+ dev_dbg(clk->dev, "rate=%ld\n", rate);
+ return rate;
+}
+
+static int clk_ti_mux_request(struct clk *clk)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
+ struct clk *parent;
+ int index;
+
+ clk->flags = priv->flags;
+
+ index = clk_ti_mux_get_index(clk);
+ parent = clk_ti_mux_get_parent_by_index(&priv->parents, index);
+ if (IS_ERR(parent))
+ return PTR_ERR(parent);
+
+ return clk_ti_mux_set_parent(clk, parent);
+}
+
+static struct clk_ops clk_ti_mux_ops = {
+ .request = clk_ti_mux_request,
+ .round_rate = clk_ti_mux_round_rate,
+ .get_rate = clk_ti_mux_get_rate,
+ .set_rate = clk_ti_mux_set_rate,
+ .set_parent = clk_ti_mux_set_parent,
+};
+
+static int clk_ti_mux_remove(struct udevice *dev)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_release_all(priv->parents.clks, priv->parents.count);
+ if (err)
+ dev_dbg(dev, "could not release all parents' clocks\n");
+
+ return err;
+}
+
+static int clk_ti_mux_probe(struct udevice *dev)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_get_bulk(dev, &priv->parents);
+ if (err || priv->parents.count < 2) {
+ dev_err(dev, "mux-clock must have parents\n");
+ return err ? err : -EFAULT;
+ }
+
+ /* Generate bit-mask based on parents info */
+ priv->mask = priv->parents.count;
+ if (!(priv->mux_flags & CLK_MUX_INDEX_ONE))
+ priv->mask--;
+
+ priv->mask = (1 << fls(priv->mask)) - 1;
+ return 0;
+}
+
+static int clk_ti_mux_ofdata_to_platdata(struct udevice *dev)
+{
+ struct clk_ti_mux_priv *priv = dev_get_priv(dev);
+
+ priv->reg = dev_read_addr(dev);
+ if (priv->reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get register\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
+ priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
+ priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
+
+ priv->flags = CLK_SET_RATE_NO_REPARENT;
+ if (dev_read_bool(dev, "ti,set-rate-parent"))
+ priv->flags |= CLK_SET_RATE_PARENT;
+
+ if (dev_read_bool(dev, "ti,index-starts-at-one"))
+ priv->mux_flags |= CLK_MUX_INDEX_ONE;
+
+ return 0;
+}
+
+static const struct udevice_id clk_ti_mux_of_match[] = {
+ {.compatible = "ti,mux-clock"},
+ {},
+};
+
+U_BOOT_DRIVER(clk_ti_mux) = {
+ .name = "ti_mux_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_mux_of_match,
+ .ofdata_to_platdata = clk_ti_mux_ofdata_to_platdata,
+ .probe = clk_ti_mux_probe,
+ .remove = clk_ti_mux_remove,
+ .priv_auto_alloc_size = sizeof(struct clk_ti_mux_priv),
+ .ops = &clk_ti_mux_ops,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 07/28] arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macro
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
` (5 preceding siblings ...)
2020-12-24 7:25 ` [PATCH v7 06/28] clk: ti: add mux clock driver Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 08/28] clk: ti: am33xx: add DPLL clock drivers Dario Binacchi
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
Add missing DPLL_EN_FAST_RELOCK_BYPASS macro. Used to put the DPLL in
idle bypass fast relock mode.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
---
(no changes since v1)
arch/arm/include/asm/arch-am33xx/clock.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index dc7a9b188d..5d775902bb 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -66,6 +66,7 @@
#define DPLL_EN_STOP 1
#define DPLL_EN_MN_BYPASS 4
#define DPLL_EN_LOW_POWER_BYPASS 5
+#define DPLL_EN_FAST_RELOCK_BYPASS 6
#define DPLL_EN_LOCK 7
/* CM_IDLEST_DPLL fields */
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 08/28] clk: ti: am33xx: add DPLL clock drivers
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
` (6 preceding siblings ...)
2020-12-24 7:25 ` [PATCH v7 07/28] arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macro Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 09/28] clk: ti: add divider clock driver Dario Binacchi
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
The digital phase-locked loop (DPLL) provides all interface clocks and
functional clocks to the processor of the AM33xx device. The AM33xx
device integrates five different DPLLs:
* Core DPLL
* Per DPLL
* LCD DPLL
* DDR DPLL
* MPU DPLL
The patch adds support for the compatible strings:
* "ti,am3-dpll-core-clock"
* "ti,am3-dpll-no-gate-clock"
* "ti,am3-dpll-no-gate-j-type-clock"
* "ti,am3-dpll-x2-clock"
The code is loosely based on the drivers/clk/ti/dpll.c drivers of the
Linux kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/dpll.txt
Signed-off-by: Dario Binacchi <dariobin@libero.it>
---
(no changes since v5)
Changes in v5:
- Move the clk-ti-am3-dpll.c file to drivers/clk/ti with the name
clk-am3-dpll.c.
- Move the clk-ti-am3-dpll-x2.c file to drivers/clk/ti with the name
clk-am3-dpll-x2.c.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
- Fix compilation errors on the dev parameter of the dev_xx macros.
Changes in v3:
- Remove doc/device-tree-bindings/clock/ti,dpll.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
drivers/clk/ti/Kconfig | 7 +
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-am3-dpll-x2.c | 79 +++++++++
drivers/clk/ti/clk-am3-dpll.c | 268 +++++++++++++++++++++++++++++++
4 files changed, 355 insertions(+)
create mode 100644 drivers/clk/ti/clk-am3-dpll-x2.c
create mode 100644 drivers/clk/ti/clk-am3-dpll.c
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index be4f26817f..c430dd9b8a 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -3,6 +3,13 @@
# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
#
+config CLK_TI_AM3_DPLL
+ bool "TI AM33XX Digital Phase-Locked Loop (DPLL) clock drivers"
+ depends on CLK && OF_CONTROL
+ help
+ This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
+ provides all interface clocks and functional clocks to the processor.
+
config CLK_TI_MUX
bool "TI mux clock driver"
depends on CLK && OF_CONTROL && CLK_CCF
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 5faf68d30e..9e14b83cfe 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,4 +3,5 @@
# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
#
+obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
diff --git a/drivers/clk/ti/clk-am3-dpll-x2.c b/drivers/clk/ti/clk-am3-dpll-x2.c
new file mode 100644
index 0000000000..3aa35f0e6c
--- /dev/null
+++ b/drivers/clk/ti/clk-am3-dpll-x2.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI DPLL x2 clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/dpll.c
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <linux/clk-provider.h>
+
+struct clk_ti_am3_dpll_x2_priv {
+ struct clk parent;
+};
+
+static ulong clk_ti_am3_dpll_x2_get_rate(struct clk *clk)
+{
+ struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(clk->dev);
+ unsigned long rate;
+
+ rate = clk_get_rate(&priv->parent);
+ if (IS_ERR_VALUE(rate))
+ return rate;
+
+ rate *= 2;
+ dev_dbg(clk->dev, "rate=%ld\n", rate);
+ return rate;
+}
+
+const struct clk_ops clk_ti_am3_dpll_x2_ops = {
+ .get_rate = clk_ti_am3_dpll_x2_get_rate,
+};
+
+static int clk_ti_am3_dpll_x2_remove(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_release_all(&priv->parent, 1);
+ if (err) {
+ dev_err(dev, "failed to release parent clock\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int clk_ti_am3_dpll_x2_probe(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_x2_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_get_by_index(dev, 0, &priv->parent);
+ if (err) {
+ dev_err(dev, "%s: failed to get parent clock\n", __func__);
+ return err;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id clk_ti_am3_dpll_x2_of_match[] = {
+ {.compatible = "ti,am3-dpll-x2-clock"},
+ {}
+};
+
+U_BOOT_DRIVER(clk_ti_am3_dpll_x2) = {
+ .name = "ti_am3_dpll_x2_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_am3_dpll_x2_of_match,
+ .probe = clk_ti_am3_dpll_x2_probe,
+ .remove = clk_ti_am3_dpll_x2_remove,
+ .priv_auto_alloc_size = sizeof(struct clk_ti_am3_dpll_x2_priv),
+ .ops = &clk_ti_am3_dpll_x2_ops,
+};
diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c
new file mode 100644
index 0000000000..d50660aae2
--- /dev/null
+++ b/drivers/clk/ti/clk-am3-dpll.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI DPLL clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/dpll.c
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <hang.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+struct clk_ti_am3_dpll_drv_data {
+ ulong max_rate;
+};
+
+struct clk_ti_am3_dpll_priv {
+ fdt_addr_t clkmode_reg;
+ fdt_addr_t idlest_reg;
+ fdt_addr_t clksel_reg;
+ struct clk clk_bypass;
+ struct clk clk_ref;
+ u16 last_rounded_mult;
+ u8 last_rounded_div;
+ ulong max_rate;
+};
+
+static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+ ulong ret, ref_rate, r;
+ int m, d, err_min, err;
+ int mult = INT_MAX, div = INT_MAX;
+
+ if (priv->max_rate && rate > priv->max_rate) {
+ dev_warn(clk->dev, "%ld is to high a rate, lowered to %ld\n",
+ rate, priv->max_rate);
+ rate = priv->max_rate;
+ }
+
+ ret = -EFAULT;
+ err = rate;
+ err_min = rate;
+ ref_rate = clk_get_rate(&priv->clk_ref);
+ for (d = 1; err_min && d <= 128; d++) {
+ for (m = 2; m <= 2047; m++) {
+ r = (ref_rate * m) / d;
+ err = abs(r - rate);
+ if (err < err_min) {
+ err_min = err;
+ ret = r;
+ mult = m;
+ div = d;
+
+ if (err == 0)
+ break;
+ } else if (r > rate) {
+ break;
+ }
+ }
+ }
+
+ priv->last_rounded_mult = mult;
+ priv->last_rounded_div = div;
+ dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, mult=%d, div=%d\n", rate,
+ ret, mult, div);
+ return ret;
+}
+
+static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+ u32 v;
+ ulong round_rate;
+
+ round_rate = clk_ti_am3_dpll_round_rate(clk, rate);
+ if (IS_ERR_VALUE(round_rate))
+ return round_rate;
+
+ v = readl(priv->clksel_reg);
+
+ /* enter bypass mode */
+ clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
+
+ /* wait for bypass mode */
+ if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
+ (void *)priv->idlest_reg, LDELAY))
+ dev_err(clk->dev, "failed bypassing dpll\n");
+
+ /* set M & N */
+ v &= ~CM_CLKSEL_DPLL_M_MASK;
+ v |= (priv->last_rounded_mult << CM_CLKSEL_DPLL_M_SHIFT) &
+ CM_CLKSEL_DPLL_M_MASK;
+
+ v &= ~CM_CLKSEL_DPLL_N_MASK;
+ v |= ((priv->last_rounded_div - 1) << CM_CLKSEL_DPLL_N_SHIFT) &
+ CM_CLKSEL_DPLL_N_MASK;
+
+ writel(v, priv->clksel_reg);
+
+ /* lock dpll */
+ clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
+ DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+
+ /* wait till the dpll locks */
+ if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
+ (void *)priv->idlest_reg, LDELAY)) {
+ dev_err(clk->dev, "failed locking dpll\n");
+ hang();
+ }
+
+ return round_rate;
+}
+
+static ulong clk_ti_am3_dpll_get_rate(struct clk *clk)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+ u64 rate;
+ u32 m, n, v;
+
+ /* Return bypass rate if DPLL is bypassed */
+ v = readl(priv->clkmode_reg);
+ v &= CM_CLKMODE_DPLL_EN_MASK;
+ v >>= CM_CLKMODE_DPLL_EN_SHIFT;
+
+ switch (v) {
+ case DPLL_EN_MN_BYPASS:
+ case DPLL_EN_LOW_POWER_BYPASS:
+ case DPLL_EN_FAST_RELOCK_BYPASS:
+ rate = clk_get_rate(&priv->clk_bypass);
+ dev_dbg(clk->dev, "rate=%lld\n", rate);
+ return rate;
+ }
+
+ v = readl(priv->clksel_reg);
+ m = v & CM_CLKSEL_DPLL_M_MASK;
+ m >>= CM_CLKSEL_DPLL_M_SHIFT;
+ n = v & CM_CLKSEL_DPLL_N_MASK;
+ n >>= CM_CLKSEL_DPLL_N_SHIFT;
+
+ rate = clk_get_rate(&priv->clk_ref) * m;
+ do_div(rate, n + 1);
+ dev_dbg(clk->dev, "rate=%lld\n", rate);
+ return rate;
+}
+
+const struct clk_ops clk_ti_am3_dpll_ops = {
+ .round_rate = clk_ti_am3_dpll_round_rate,
+ .get_rate = clk_ti_am3_dpll_get_rate,
+ .set_rate = clk_ti_am3_dpll_set_rate,
+};
+
+static int clk_ti_am3_dpll_remove(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_release_all(&priv->clk_bypass, 1);
+ if (err) {
+ dev_err(dev, "failed to release bypass clock\n");
+ return err;
+ }
+
+ err = clk_release_all(&priv->clk_ref, 1);
+ if (err) {
+ dev_err(dev, "failed to release reference clock\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int clk_ti_am3_dpll_probe(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_get_by_index(dev, 0, &priv->clk_ref);
+ if (err) {
+ dev_err(dev, "failed to get reference clock\n");
+ return err;
+ }
+
+ err = clk_get_by_index(dev, 1, &priv->clk_bypass);
+ if (err) {
+ dev_err(dev, "failed to get bypass clock\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int clk_ti_am3_dpll_ofdata_to_platdata(struct udevice *dev)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
+ struct clk_ti_am3_dpll_drv_data *data =
+ (struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev);
+
+ priv->max_rate = data->max_rate;
+
+ priv->clkmode_reg = dev_read_addr_index(dev, 0);
+ if (priv->clkmode_reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get clkmode register\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "clkmode_reg=0x%08lx\n", priv->clkmode_reg);
+
+ priv->idlest_reg = dev_read_addr_index(dev, 1);
+ if (priv->idlest_reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get idlest register\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "idlest_reg=0x%08lx\n", priv->idlest_reg);
+
+ priv->clksel_reg = dev_read_addr_index(dev, 2);
+ if (priv->clksel_reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get clksel register\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "clksel_reg=0x%08lx\n", priv->clksel_reg);
+
+ return 0;
+}
+
+static const struct clk_ti_am3_dpll_drv_data dpll_no_gate_data = {
+ .max_rate = 1000000000
+};
+
+static const struct clk_ti_am3_dpll_drv_data dpll_no_gate_j_type_data = {
+ .max_rate = 2000000000
+};
+
+static const struct clk_ti_am3_dpll_drv_data dpll_core_data = {
+ .max_rate = 1000000000
+};
+
+static const struct udevice_id clk_ti_am3_dpll_of_match[] = {
+ {.compatible = "ti,am3-dpll-core-clock",
+ .data = (ulong)&dpll_core_data},
+ {.compatible = "ti,am3-dpll-no-gate-clock",
+ .data = (ulong)&dpll_no_gate_data},
+ {.compatible = "ti,am3-dpll-no-gate-j-type-clock",
+ .data = (ulong)&dpll_no_gate_j_type_data},
+ {}
+};
+
+U_BOOT_DRIVER(clk_ti_am3_dpll) = {
+ .name = "ti_am3_dpll_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_am3_dpll_of_match,
+ .ofdata_to_platdata = clk_ti_am3_dpll_ofdata_to_platdata,
+ .probe = clk_ti_am3_dpll_probe,
+ .remove = clk_ti_am3_dpll_remove,
+ .priv_auto_alloc_size = sizeof(struct clk_ti_am3_dpll_priv),
+ .ops = &clk_ti_am3_dpll_ops,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 09/28] clk: ti: add divider clock driver
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
` (7 preceding siblings ...)
2020-12-24 7:25 ` [PATCH v7 08/28] clk: ti: am33xx: add DPLL clock drivers Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 10/28] clk: ti: add gate " Dario Binacchi
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
The patch adds support for TI divider clock binding. The driver uses
routines provided by the common clock framework (ccf).
The code is based on the drivers/clk/ti/divider.c driver of the Linux
kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/divider.txt
Signed-off-by: Dario Binacchi <dariobin@libero.it>
---
(no changes since v5)
Changes in v5:
- Move the clk-ti.c file to drivers/clk/ti with the name clk.c.
- Move the clk-ti.h file to drivers/clk/ti with the name clk.h.
- Move the clk-ti-divider.c file to drivers/clk/ti with the name
clk-divider.c.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
- Fix compilation errors on the dev parameter of the dev_xx macros.
Changes in v3:
- Remove doc/device-tree-bindings/clock/ti,autoidle.txt.
- Remove doc/device-tree-bindings/clock/ti,divider.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
Changes in v2:
- Merged to patch [09/31] clk: ti: refactor mux and divider clock
drivers.
drivers/clk/ti/Kconfig | 6 +
drivers/clk/ti/Makefile | 3 +
drivers/clk/ti/clk-divider.c | 381 +++++++++++++++++++++++++++++++++++
drivers/clk/ti/clk-mux.c | 27 +--
drivers/clk/ti/clk.c | 34 ++++
drivers/clk/ti/clk.h | 13 ++
6 files changed, 439 insertions(+), 25 deletions(-)
create mode 100644 drivers/clk/ti/clk-divider.c
create mode 100644 drivers/clk/ti/clk.c
create mode 100644 drivers/clk/ti/clk.h
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index c430dd9b8a..87eea86c6f 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -10,6 +10,12 @@ config CLK_TI_AM3_DPLL
This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
provides all interface clocks and functional clocks to the processor.
+config CLK_TI_DIVIDER
+ bool "TI divider clock driver"
+ depends on CLK && OF_CONTROL && CLK_CCF
+ help
+ This enables the divider clock driver support on TI's SoCs.
+
config CLK_TI_MUX
bool "TI mux clock driver"
depends on CLK && OF_CONTROL && CLK_CCF
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 9e14b83cfe..fd7094cff0 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -3,5 +3,8 @@
# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
#
+obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o
+
obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
+obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
diff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c
new file mode 100644
index 0000000000..d448197b1f
--- /dev/null
+++ b/drivers/clk/ti/clk-divider.c
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI divider clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/divider.c
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <asm/io.h>
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/log2.h>
+#include "clk.h"
+
+/*
+ * The reverse of DIV_ROUND_UP: The maximum number which
+ * divided by m is r
+ */
+#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
+
+struct clk_ti_divider_priv {
+ struct clk parent;
+ fdt_addr_t reg;
+ const struct clk_div_table *table;
+ u8 shift;
+ u8 flags;
+ u8 div_flags;
+ s8 latch;
+ u16 min;
+ u16 max;
+ u16 mask;
+};
+
+static unsigned int _get_div(const struct clk_div_table *table, ulong flags,
+ unsigned int val)
+{
+ if (flags & CLK_DIVIDER_ONE_BASED)
+ return val;
+
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return 1 << val;
+
+ if (table)
+ return clk_divider_get_table_div(table, val);
+
+ return val + 1;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table, ulong flags,
+ unsigned int div)
+{
+ if (flags & CLK_DIVIDER_ONE_BASED)
+ return div;
+
+ if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ return __ffs(div);
+
+ if (table)
+ return clk_divider_get_table_val(table, div);
+
+ return div - 1;
+}
+
+static int _div_round_up(const struct clk_div_table *table, ulong parent_rate,
+ ulong rate)
+{
+ const struct clk_div_table *clkt;
+ int up = INT_MAX;
+ int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+ for (clkt = table; clkt->div; clkt++) {
+ if (clkt->div == div)
+ return clkt->div;
+ else if (clkt->div < div)
+ continue;
+
+ if ((clkt->div - div) < (up - div))
+ up = clkt->div;
+ }
+
+ return up;
+}
+
+static int _div_round(const struct clk_div_table *table, ulong parent_rate,
+ ulong rate)
+{
+ if (table)
+ return _div_round_up(table, parent_rate, rate);
+
+ return DIV_ROUND_UP(parent_rate, rate);
+}
+
+static int clk_ti_divider_best_div(struct clk *clk, ulong rate,
+ ulong *best_parent_rate)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+ ulong parent_rate, parent_round_rate, max_div;
+ ulong best_rate, r;
+ int i, best_div = 0;
+
+ parent_rate = clk_get_rate(&priv->parent);
+ if (IS_ERR_VALUE(parent_rate))
+ return parent_rate;
+
+ if (!rate)
+ rate = 1;
+
+ if (!(clk->flags & CLK_SET_RATE_PARENT)) {
+ best_div = _div_round(priv->table, parent_rate, rate);
+ if (best_div == 0)
+ best_div = 1;
+
+ if (best_div > priv->max)
+ best_div = priv->max;
+
+ *best_parent_rate = parent_rate;
+ return best_div;
+ }
+
+ max_div = min(ULONG_MAX / rate, (ulong)priv->max);
+ for (best_rate = 0, i = 1; i <= max_div; i++) {
+ if (!clk_divider_is_valid_div(priv->table, priv->div_flags, i))
+ continue;
+
+ /*
+ * It's the most ideal case if the requested rate can be
+ * divided from parent clock without needing to change
+ * parent rate, so return the divider immediately.
+ */
+ if ((rate * i) == parent_rate) {
+ *best_parent_rate = parent_rate;
+ dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, div=%d\n",
+ rate, rate, i);
+ return i;
+ }
+
+ parent_round_rate = clk_round_rate(&priv->parent,
+ MULT_ROUND_UP(rate, i));
+ if (IS_ERR_VALUE(parent_round_rate))
+ continue;
+
+ r = DIV_ROUND_UP(parent_round_rate, i);
+ if (r <= rate && r > best_rate) {
+ best_div = i;
+ best_rate = r;
+ *best_parent_rate = parent_round_rate;
+ if (best_rate == rate)
+ break;
+ }
+ }
+
+ if (best_div == 0) {
+ best_div = priv->max;
+ parent_round_rate = clk_round_rate(&priv->parent, 1);
+ if (IS_ERR_VALUE(parent_round_rate))
+ return parent_round_rate;
+ }
+
+ dev_dbg(clk->dev, "rate=%ld, best_rate=%ld, div=%d\n", rate, best_rate,
+ best_div);
+
+ return best_div;
+}
+
+static ulong clk_ti_divider_round_rate(struct clk *clk, ulong rate)
+{
+ ulong parent_rate;
+ int div;
+
+ div = clk_ti_divider_best_div(clk, rate, &parent_rate);
+ if (div < 0)
+ return div;
+
+ return DIV_ROUND_UP(parent_rate, div);
+}
+
+static ulong clk_ti_divider_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+ ulong parent_rate;
+ int div;
+ u32 val, v;
+
+ div = clk_ti_divider_best_div(clk, rate, &parent_rate);
+ if (div < 0)
+ return div;
+
+ if (clk->flags & CLK_SET_RATE_PARENT) {
+ parent_rate = clk_set_rate(&priv->parent, parent_rate);
+ if (IS_ERR_VALUE(parent_rate))
+ return parent_rate;
+ }
+
+ val = _get_val(priv->table, priv->div_flags, div);
+
+ v = readl(priv->reg);
+ v &= ~(priv->mask << priv->shift);
+ v |= val << priv->shift;
+ writel(v, priv->reg);
+ clk_ti_latch(priv->reg, priv->latch);
+
+ return clk_get_rate(clk);
+}
+
+static ulong clk_ti_divider_get_rate(struct clk *clk)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+ ulong rate, parent_rate;
+ unsigned int div;
+ u32 v;
+
+ parent_rate = clk_get_rate(&priv->parent);
+ if (IS_ERR_VALUE(parent_rate))
+ return parent_rate;
+
+ v = readl(priv->reg) >> priv->shift;
+ v &= priv->mask;
+
+ div = _get_div(priv->table, priv->div_flags, v);
+ if (!div) {
+ if (!(priv->div_flags & CLK_DIVIDER_ALLOW_ZERO))
+ dev_warn(clk->dev,
+ "zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n");
+ return parent_rate;
+ }
+
+ rate = DIV_ROUND_UP(parent_rate, div);
+ dev_dbg(clk->dev, "rate=%ld\n", rate);
+ return rate;
+}
+
+static int clk_ti_divider_request(struct clk *clk)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);
+
+ clk->flags = priv->flags;
+ return 0;
+}
+
+const struct clk_ops clk_ti_divider_ops = {
+ .request = clk_ti_divider_request,
+ .round_rate = clk_ti_divider_round_rate,
+ .get_rate = clk_ti_divider_get_rate,
+ .set_rate = clk_ti_divider_set_rate
+};
+
+static int clk_ti_divider_remove(struct udevice *dev)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_release_all(&priv->parent, 1);
+ if (err) {
+ dev_err(dev, "failed to release parent clock\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int clk_ti_divider_probe(struct udevice *dev)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(dev);
+ int err;
+
+ err = clk_get_by_index(dev, 0, &priv->parent);
+ if (err) {
+ dev_err(dev, "failed to get parent clock\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int clk_ti_divider_ofdata_to_platdata(struct udevice *dev)
+{
+ struct clk_ti_divider_priv *priv = dev_get_priv(dev);
+ struct clk_div_table *table = NULL;
+ u32 val, valid_div;
+ u32 min_div = 0;
+ u32 max_val, max_div = 0;
+ u16 mask;
+ int i, div_num;
+
+ priv->reg = dev_read_addr(dev);
+ dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
+ priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
+ priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
+ if (dev_read_bool(dev, "ti,index-starts-at-one"))
+ priv->div_flags |= CLK_DIVIDER_ONE_BASED;
+
+ if (dev_read_bool(dev, "ti,index-power-of-two"))
+ priv->div_flags |= CLK_DIVIDER_POWER_OF_TWO;
+
+ if (dev_read_bool(dev, "ti,set-rate-parent"))
+ priv->flags |= CLK_SET_RATE_PARENT;
+
+ if (dev_read_prop(dev, "ti,dividers", &div_num)) {
+ div_num /= sizeof(u32);
+
+ /* Determine required size for divider table */
+ for (i = 0, valid_div = 0; i < div_num; i++) {
+ dev_read_u32_index(dev, "ti,dividers", i, &val);
+ if (val)
+ valid_div++;
+ }
+
+ if (!valid_div) {
+ dev_err(dev, "no valid dividers\n");
+ return -EINVAL;
+ }
+
+ table = calloc(valid_div + 1, sizeof(*table));
+ if (!table)
+ return -ENOMEM;
+
+ for (i = 0, valid_div = 0; i < div_num; i++) {
+ dev_read_u32_index(dev, "ti,dividers", i, &val);
+ if (!val)
+ continue;
+
+ table[valid_div].div = val;
+ table[valid_div].val = i;
+ valid_div++;
+ if (val > max_div)
+ max_div = val;
+
+ if (!min_div || val < min_div)
+ min_div = val;
+ }
+
+ max_val = max_div;
+ } else {
+ /* Divider table not provided, determine min/max divs */
+ min_div = dev_read_u32_default(dev, "ti,min-div", 1);
+ if (dev_read_u32(dev, "ti,max-div", &max_div)) {
+ dev_err(dev, "missing 'max-div' property\n");
+ return -EFAULT;
+ }
+
+ max_val = max_div;
+ if (!(priv->div_flags & CLK_DIVIDER_ONE_BASED) &&
+ !(priv->div_flags & CLK_DIVIDER_POWER_OF_TWO))
+ max_val--;
+ }
+
+ priv->table = table;
+ priv->min = min_div;
+ priv->max = max_div;
+
+ if (priv->div_flags & CLK_DIVIDER_POWER_OF_TWO)
+ mask = fls(max_val) - 1;
+ else
+ mask = max_val;
+
+ priv->mask = (1 << fls(mask)) - 1;
+ return 0;
+}
+
+static const struct udevice_id clk_ti_divider_of_match[] = {
+ {.compatible = "ti,divider-clock"},
+ {}
+};
+
+U_BOOT_DRIVER(clk_ti_divider) = {
+ .name = "ti_divider_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_divider_of_match,
+ .ofdata_to_platdata = clk_ti_divider_ofdata_to_platdata,
+ .probe = clk_ti_divider_probe,
+ .remove = clk_ti_divider_remove,
+ .priv_auto_alloc_size = sizeof(struct clk_ti_divider_priv),
+ .ops = &clk_ti_divider_ops,
+};
diff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c
index 9720c84513..35470255af 100644
--- a/drivers/clk/ti/clk-mux.c
+++ b/drivers/clk/ti/clk-mux.c
@@ -13,6 +13,7 @@
#include <clk-uclass.h>
#include <asm/io.h>
#include <linux/clk-provider.h>
+#include "clk.h"
struct clk_ti_mux_priv {
struct clk_bulk parents;
@@ -24,30 +25,6 @@ struct clk_ti_mux_priv {
s32 latch;
};
-static void clk_ti_mux_rmw(u32 val, u32 mask, fdt_addr_t reg)
-{
- u32 v;
-
- v = readl(reg);
- v &= ~mask;
- v |= val;
- writel(v, reg);
-}
-
-static void clk_ti_mux_latch(fdt_addr_t reg, s8 shift)
-{
- u32 latch;
-
- if (shift < 0)
- return;
-
- latch = 1 << shift;
-
- clk_ti_mux_rmw(latch, latch, reg);
- clk_ti_mux_rmw(0, latch, reg);
- readl(reg); /* OCP barrier */
-}
-
static struct clk *clk_ti_mux_get_parent_by_index(struct clk_bulk *parents,
int index)
{
@@ -120,7 +97,7 @@ static int clk_ti_mux_set_parent(struct clk *clk, struct clk *parent)
val |= index << priv->shift;
writel(val, priv->reg);
- clk_ti_mux_latch(priv->reg, priv->latch);
+ clk_ti_latch(priv->reg, priv->latch);
return 0;
}
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
new file mode 100644
index 0000000000..e44b90ad6a
--- /dev/null
+++ b/drivers/clk/ti/clk.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI clock utilities
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include "clk.h"
+
+static void clk_ti_rmw(u32 val, u32 mask, fdt_addr_t reg)
+{
+ u32 v;
+
+ v = readl(reg);
+ v &= ~mask;
+ v |= val;
+ writel(v, reg);
+}
+
+void clk_ti_latch(fdt_addr_t reg, s8 shift)
+{
+ u32 latch;
+
+ if (shift < 0)
+ return;
+
+ latch = 1 << shift;
+
+ clk_ti_rmw(latch, latch, reg);
+ clk_ti_rmw(0, latch, reg);
+ readl(reg); /* OCP barrier */
+}
diff --git a/drivers/clk/ti/clk.h b/drivers/clk/ti/clk.h
new file mode 100644
index 0000000000..601c3823f7
--- /dev/null
+++ b/drivers/clk/ti/clk.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * TI clock utilities header
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ */
+
+#ifndef _CLK_TI_H
+#define _CLK_TI_H
+
+void clk_ti_latch(fdt_addr_t reg, s8 shift);
+
+#endif /* #ifndef _CLK_TI_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 10/28] clk: ti: add gate clock driver
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
` (8 preceding siblings ...)
2020-12-24 7:25 ` [PATCH v7 09/28] clk: ti: add divider clock driver Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 11/28] arm: dts: am335x: include am33xx-u-boot.dtsi Dario Binacchi
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
The patch adds support for TI gate clock binding. The code is based on
the drivers/clk/ti/gate.c driver of the Linux kernel version 5.9-rc7.
For DT binding details see:
- Documentation/devicetree/bindings/clock/ti/gate.txt
Signed-off-by: Dario Binacchi <dariobin@libero.it>
---
(no changes since v5)
Changes in v5:
- Move the clk-ti-gate.c file to drivers/clk/ti with the name
clk-gate.c.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
Changes in v3:
- Remove doc/device-tree-bindings/clock/gpio-gate-clock.txt.
- Remove doc/device-tree-bindings/clock/ti,clockdomain.txt.
- Remove doc/device-tree-bindings/clock/ti,gate.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
drivers/clk/ti/Kconfig | 6 +++
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-gate.c | 93 +++++++++++++++++++++++++++++++++++++++
3 files changed, 100 insertions(+)
create mode 100644 drivers/clk/ti/clk-gate.c
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 87eea86c6f..30959a316a 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -16,6 +16,12 @@ config CLK_TI_DIVIDER
help
This enables the divider clock driver support on TI's SoCs.
+config CLK_TI_GATE
+ bool "TI gate clock driver"
+ depends on CLK && OF_CONTROL
+ help
+ This enables the gate clock driver support on TI's SoCs.
+
config CLK_TI_MUX
bool "TI mux clock driver"
depends on CLK && OF_CONTROL && CLK_CCF
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index fd7094cff0..f8aa735c83 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -7,4 +7,5 @@ obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o
obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
+obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
diff --git a/drivers/clk/ti/clk-gate.c b/drivers/clk/ti/clk-gate.c
new file mode 100644
index 0000000000..6c5432c823
--- /dev/null
+++ b/drivers/clk/ti/clk-gate.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * TI gate clock support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ *
+ * Loosely based on Linux kernel drivers/clk/ti/gate.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <clk-uclass.h>
+#include <asm/io.h>
+#include <linux/clk-provider.h>
+
+struct clk_ti_gate_priv {
+ fdt_addr_t reg;
+ u8 enable_bit;
+ u32 flags;
+ bool invert_enable;
+};
+
+static int clk_ti_gate_disable(struct clk *clk)
+{
+ struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
+ u32 v;
+
+ v = readl(priv->reg);
+ if (priv->invert_enable)
+ v |= (1 << priv->enable_bit);
+ else
+ v &= ~(1 << priv->enable_bit);
+
+ writel(v, priv->reg);
+ /* No OCP barrier needed here since it is a disable operation */
+ return 0;
+}
+
+static int clk_ti_gate_enable(struct clk *clk)
+{
+ struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
+ u32 v;
+
+ v = readl(priv->reg);
+ if (priv->invert_enable)
+ v &= ~(1 << priv->enable_bit);
+ else
+ v |= (1 << priv->enable_bit);
+
+ writel(v, priv->reg);
+ /* OCP barrier */
+ v = readl(priv->reg);
+ return 0;
+}
+
+static int clk_ti_gate_ofdata_to_platdata(struct udevice *dev)
+{
+ struct clk_ti_gate_priv *priv = dev_get_priv(dev);
+
+ priv->reg = dev_read_addr(dev);
+ if (priv->reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get control register\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
+ priv->enable_bit = dev_read_u32_default(dev, "ti,bit-shift", 0);
+ if (dev_read_bool(dev, "ti,set-rate-parent"))
+ priv->flags |= CLK_SET_RATE_PARENT;
+
+ priv->invert_enable = dev_read_bool(dev, "ti,set-bit-to-disable");
+ return 0;
+}
+
+static struct clk_ops clk_ti_gate_ops = {
+ .enable = clk_ti_gate_enable,
+ .disable = clk_ti_gate_disable,
+};
+
+static const struct udevice_id clk_ti_gate_of_match[] = {
+ { .compatible = "ti,gate-clock" },
+ { },
+};
+
+U_BOOT_DRIVER(clk_ti_gate) = {
+ .name = "ti_gate_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_gate_of_match,
+ .ofdata_to_platdata = clk_ti_gate_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct clk_ti_gate_priv),
+ .ops = &clk_ti_gate_ops,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 11/28] arm: dts: am335x: include am33xx-u-boot.dtsi
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
` (9 preceding siblings ...)
2020-12-24 7:25 ` [PATCH v7 10/28] clk: ti: add gate " Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 12/28] ti: am33xx: fix do_enable_clocks() to accept NULL parameters Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 13/28] clk: ti: add support for clkctrl clocks Dario Binacchi
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
Include the SoC U-boot DTS in each am335x-<board>-u-boot.dtsi.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
---
(no changes since v1)
arch/arm/dts/am335x-chiliboard-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-evm-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-evmsk-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-guardian-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-icev2-u-boot.dtsi | 3 +++
arch/arm/dts/am335x-pdu001-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-pxm50-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-regor-rdk-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-rut-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-shc-u-boot.dtsi | 2 ++
arch/arm/dts/am335x-wega-rdk-u-boot.dtsi | 2 ++
11 files changed, 23 insertions(+)
diff --git a/arch/arm/dts/am335x-chiliboard-u-boot.dtsi b/arch/arm/dts/am335x-chiliboard-u-boot.dtsi
index 4f9d308039..06a13872ee 100644
--- a/arch/arm/dts/am335x-chiliboard-u-boot.dtsi
+++ b/arch/arm/dts/am335x-chiliboard-u-boot.dtsi
@@ -4,6 +4,8 @@
* Author: Marcin Niestroj <m.niestroj@grinn-global.com>
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
chosen {
stdout-path = &uart0;
diff --git a/arch/arm/dts/am335x-evm-u-boot.dtsi b/arch/arm/dts/am335x-evm-u-boot.dtsi
index d7b049ef20..400a1d2cec 100644
--- a/arch/arm/dts/am335x-evm-u-boot.dtsi
+++ b/arch/arm/dts/am335x-evm-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
panel {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-evmsk-u-boot.dtsi b/arch/arm/dts/am335x-evmsk-u-boot.dtsi
index 599fb377e6..96798330b1 100644
--- a/arch/arm/dts/am335x-evmsk-u-boot.dtsi
+++ b/arch/arm/dts/am335x-evmsk-u-boot.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
panel {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-guardian-u-boot.dtsi b/arch/arm/dts/am335x-guardian-u-boot.dtsi
index eae027c541..c866ce83f3 100644
--- a/arch/arm/dts/am335x-guardian-u-boot.dtsi
+++ b/arch/arm/dts/am335x-guardian-u-boot.dtsi
@@ -4,6 +4,8 @@
* Copyright (C) 2018 Robert Bosch Power Tools GmbH
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
ocp {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-icev2-u-boot.dtsi b/arch/arm/dts/am335x-icev2-u-boot.dtsi
index cc9569af03..67bfac916e 100644
--- a/arch/arm/dts/am335x-icev2-u-boot.dtsi
+++ b/arch/arm/dts/am335x-icev2-u-boot.dtsi
@@ -2,6 +2,9 @@
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
*/
+
+#include "am33xx-u-boot.dtsi"
+
/ {
xtal25mhz: xtal25mhz {
compatible = "fixed-clock";
diff --git a/arch/arm/dts/am335x-pdu001-u-boot.dtsi b/arch/arm/dts/am335x-pdu001-u-boot.dtsi
index a799fe9bc3..4f4fc411f9 100644
--- a/arch/arm/dts/am335x-pdu001-u-boot.dtsi
+++ b/arch/arm/dts/am335x-pdu001-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
ocp {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-pxm50-u-boot.dtsi b/arch/arm/dts/am335x-pxm50-u-boot.dtsi
index 77dfe6e262..65ed948c58 100644
--- a/arch/arm/dts/am335x-pxm50-u-boot.dtsi
+++ b/arch/arm/dts/am335x-pxm50-u-boot.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
panel {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
index 1ddd715875..4052d0ee21 100644
--- a/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
+++ b/arch/arm/dts/am335x-regor-rdk-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2020 Linumiz
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
chosen {
#address-cells = <1>;
diff --git a/arch/arm/dts/am335x-rut-u-boot.dtsi b/arch/arm/dts/am335x-rut-u-boot.dtsi
index b2b4aa596a..b16f75a764 100644
--- a/arch/arm/dts/am335x-rut-u-boot.dtsi
+++ b/arch/arm/dts/am335x-rut-u-boot.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
panel {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-shc-u-boot.dtsi b/arch/arm/dts/am335x-shc-u-boot.dtsi
index 2975839ea7..359ae05209 100644
--- a/arch/arm/dts/am335x-shc-u-boot.dtsi
+++ b/arch/arm/dts/am335x-shc-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
ocp {
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
index 634f1b0712..28fd62e231 100644
--- a/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
+++ b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright (C) 2019 DENX Software Engineering GmbH
*/
+#include "am33xx-u-boot.dtsi"
+
/ {
chosen {
#address-cells = <1>;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 12/28] ti: am33xx: fix do_enable_clocks() to accept NULL parameters
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
` (10 preceding siblings ...)
2020-12-24 7:25 ` [PATCH v7 11/28] arm: dts: am335x: include am33xx-u-boot.dtsi Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 13/28] clk: ti: add support for clkctrl clocks Dario Binacchi
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
Up till this commit passing NULL as input parameter was allowed, but not
handled properly. When a NULL parameter was passed to the function a data
abort was raised.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/arm/mach-omap2/am33xx/clock.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-omap2/am33xx/clock.c b/arch/arm/mach-omap2/am33xx/clock.c
index 8819062aaa..130ee6c6e3 100644
--- a/arch/arm/mach-omap2/am33xx/clock.c
+++ b/arch/arm/mach-omap2/am33xx/clock.c
@@ -194,13 +194,14 @@ void do_enable_clocks(u32 *const *clk_domains,
u32 i, max = 100;
/* Put the clock domains in SW_WKUP mode */
- for (i = 0; (i < max) && clk_domains[i]; i++) {
+ for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++) {
enable_clock_domain(clk_domains[i],
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
}
/* Clock modules that need to be put in SW_EXPLICIT_EN mode */
- for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
+ for (i = 0; (i < max) && clk_modules_explicit_en &&
+ clk_modules_explicit_en[i]; i++) {
enable_clock_module(clk_modules_explicit_en[i],
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
wait_for_enable);
@@ -215,12 +216,13 @@ void do_disable_clocks(u32 *const *clk_domains,
/* Clock modules that need to be put in SW_DISABLE */
- for (i = 0; (i < max) && clk_modules_disable[i]; i++)
+ for (i = 0; (i < max) && clk_modules_disable && clk_modules_disable[i];
+ i++)
disable_clock_module(clk_modules_disable[i],
wait_for_disable);
/* Put the clock domains in SW_SLEEP mode */
- for (i = 0; (i < max) && clk_domains[i]; i++)
+ for (i = 0; (i < max) && clk_domains && clk_domains[i]; i++)
disable_clock_domain(clk_domains[i]);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v7 13/28] clk: ti: add support for clkctrl clocks
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
` (11 preceding siblings ...)
2020-12-24 7:25 ` [PATCH v7 12/28] ti: am33xx: fix do_enable_clocks() to accept NULL parameters Dario Binacchi
@ 2020-12-24 7:25 ` Dario Binacchi
12 siblings, 0 replies; 14+ messages in thread
From: Dario Binacchi @ 2020-12-24 7:25 UTC (permalink / raw)
To: u-boot
Until now the clkctrl clocks have been enabled/disabled through platform
routines. Thanks to this patch they can be enabled and configured directly
by the probed devices that need to use them.
For DT binding details see Linux doc:
- Documentation/devicetree/bindings/clock/ti-clkctrl.txt
Signed-off-by: Dario Binacchi <dariobin@libero.it>
---
(no changes since v5)
Changes in v5:
- Move the clk-ti-ctrl.c file to drivers/clk/ti with the name
clk-ctrl.c.
Changes in v4:
- Include device_compat.h header for dev_xxx macros.
- Fix compilation errors on the dev parameter of the dev_xx macros.
Changes in v3:
- Fix access to registers listed by device tree following resync of
am33xx-clock.dtsi with Linux 5.9-rc7.
- Remove doc/device-tree-bindings/clock/ti,clkctrl.txt.
- Add to commit message the references to linux kernel dt binding
documentation.
drivers/clk/ti/Kconfig | 6 ++
drivers/clk/ti/Makefile | 1 +
drivers/clk/ti/clk-ctrl.c | 154 ++++++++++++++++++++++++++++++++++++++
3 files changed, 161 insertions(+)
create mode 100644 drivers/clk/ti/clk-ctrl.c
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 30959a316a..9e257a2eb7 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -10,6 +10,12 @@ config CLK_TI_AM3_DPLL
This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL
provides all interface clocks and functional clocks to the processor.
+config CLK_TI_CTRL
+ bool "TI OMAP4 clock controller"
+ depends on CLK && OF_CONTROL
+ help
+ This enables the clock controller driver support on TI's SoCs.
+
config CLK_TI_DIVIDER
bool "TI divider clock driver"
depends on CLK && OF_CONTROL && CLK_CCF
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index f8aa735c83..ed45f18311 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o
obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
+obj-$(CONFIG_CLK_TI_CTRL) += clk-ctrl.o
obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
diff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c
new file mode 100644
index 0000000000..74271aaf56
--- /dev/null
+++ b/drivers/clk/ti/clk-ctrl.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OMAP clock controller support
+ *
+ * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <clk-uclass.h>
+#include <asm/arch-am33xx/clock.h>
+
+struct clk_ti_ctrl_offs {
+ fdt_addr_t start;
+ fdt_size_t end;
+};
+
+struct clk_ti_ctrl_priv {
+ int offs_num;
+ struct clk_ti_ctrl_offs *offs;
+};
+
+static int clk_ti_ctrl_check_offs(struct clk *clk, fdt_addr_t offs)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ int i;
+
+ for (i = 0; i < priv->offs_num; i++) {
+ if (offs >= priv->offs[i].start && offs <= priv->offs[i].end)
+ return 0;
+ }
+
+ return -EFAULT;
+}
+
+static int clk_ti_ctrl_disable(struct clk *clk)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ u32 *clk_modules[2] = { };
+ fdt_addr_t offs;
+ int err;
+
+ offs = priv->offs[0].start + clk->id;
+ err = clk_ti_ctrl_check_offs(clk, offs);
+ if (err) {
+ dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+ return err;
+ }
+
+ clk_modules[0] = (u32 *)(offs);
+ dev_dbg(clk->dev, "module address=%p\n", clk_modules[0]);
+ do_disable_clocks(NULL, clk_modules, 1);
+ return 0;
+}
+
+static int clk_ti_ctrl_enable(struct clk *clk)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
+ u32 *clk_modules[2] = { };
+ fdt_addr_t offs;
+ int err;
+
+ offs = priv->offs[0].start + clk->id;
+ err = clk_ti_ctrl_check_offs(clk, offs);
+ if (err) {
+ dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
+ return err;
+ }
+
+ clk_modules[0] = (u32 *)(offs);
+ dev_dbg(clk->dev, "module address=%p\n", clk_modules[0]);
+ do_enable_clocks(NULL, clk_modules, 1);
+ return 0;
+}
+
+static ulong clk_ti_ctrl_get_rate(struct clk *clk)
+{
+ return 0;
+}
+
+static int clk_ti_ctrl_of_xlate(struct clk *clk,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 2) {
+ dev_err(clk->dev, "invaild args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (args->args_count)
+ clk->id = args->args[0];
+ else
+ clk->id = 0;
+
+ dev_dbg(clk->dev, "name=%s, id=%ld\n", clk->dev->name, clk->id);
+ return 0;
+}
+
+static int clk_ti_ctrl_ofdata_to_platdata(struct udevice *dev)
+{
+ struct clk_ti_ctrl_priv *priv = dev_get_priv(dev);
+ fdt_size_t fdt_size;
+ int i, size;
+
+ size = dev_read_size(dev, "reg");
+ if (size < 0) {
+ dev_err(dev, "failed to get 'reg' size\n");
+ return size;
+ }
+
+ priv->offs_num = size / 2 / sizeof(u32);
+ dev_dbg(dev, "size=%d, regs_num=%d\n", size, priv->offs_num);
+
+ priv->offs = kmalloc_array(priv->offs_num, sizeof(*priv->offs),
+ GFP_KERNEL);
+ if (!priv->offs)
+ return -ENOMEM;
+
+ for (i = 0; i < priv->offs_num; i++) {
+ priv->offs[i].start =
+ dev_read_addr_size_index(dev, i, &fdt_size);
+ if (priv->offs[i].start == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get offset %d\n", i);
+ return -EINVAL;
+ }
+
+ priv->offs[i].end = priv->offs[i].start + fdt_size;
+ dev_dbg(dev, "start=0x%08lx, end=0x%08lx\n",
+ priv->offs[i].start, priv->offs[i].end);
+ }
+
+ return 0;
+}
+
+static struct clk_ops clk_ti_ctrl_ops = {
+ .of_xlate = clk_ti_ctrl_of_xlate,
+ .enable = clk_ti_ctrl_enable,
+ .disable = clk_ti_ctrl_disable,
+ .get_rate = clk_ti_ctrl_get_rate,
+};
+
+static const struct udevice_id clk_ti_ctrl_ids[] = {
+ {.compatible = "ti,clkctrl"},
+ {},
+};
+
+U_BOOT_DRIVER(clk_ti_ctrl) = {
+ .name = "ti_ctrl_clk",
+ .id = UCLASS_CLK,
+ .of_match = clk_ti_ctrl_ids,
+ .ofdata_to_platdata = clk_ti_ctrl_ofdata_to_platdata,
+ .ops = &clk_ti_ctrl_ops,
+ .priv_auto_alloc_size = sizeof(struct clk_ti_ctrl_priv),
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-12-24 7:25 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-24 7:25 [PATCH v7 00/28] Add DM support for omap PWM backlight Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 01/28] clk: export generic routines Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 02/28] dt-bindings: bus: ti-sysc: resync with Linux 5.9-rc7 Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 03/28] bus: ti: add minimal sysc interconnect target driver Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 04/28] arm: dts: sync am33xx with Linux 5.9-rc7 Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 05/28] clk: add clk_round_rate() Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 06/28] clk: ti: add mux clock driver Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 07/28] arm: ti: am33xx: add DPLL_EN_FAST_RELOCK_BYPASS macro Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 08/28] clk: ti: am33xx: add DPLL clock drivers Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 09/28] clk: ti: add divider clock driver Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 10/28] clk: ti: add gate " Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 11/28] arm: dts: am335x: include am33xx-u-boot.dtsi Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 12/28] ti: am33xx: fix do_enable_clocks() to accept NULL parameters Dario Binacchi
2020-12-24 7:25 ` [PATCH v7 13/28] clk: ti: add support for clkctrl clocks Dario Binacchi
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