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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec
Date: Thu, 24 Dec 2020 14:45:13 -0800	[thread overview]
Message-ID: <20201224224514.626561-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20201224224514.626561-1-richard.henderson@linaro.org>

Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-conset.h |  1 +
 tcg/arm/tcg-target.opc.h    |  1 +
 tcg/arm/tcg-target.c.inc    | 15 +++++++++++++++
 3 files changed, 17 insertions(+)

diff --git a/tcg/arm/tcg-target-conset.h b/tcg/arm/tcg-target-conset.h
index 30a5953621..efb63396de 100644
--- a/tcg/arm/tcg-target-conset.h
+++ b/tcg/arm/tcg-target-conset.h
@@ -25,6 +25,7 @@ C_O1_I2(r, r, rIK)
 C_O1_I2(r, r, rIN)
 C_O1_I2(r, r, ri)
 C_O1_I2(r, rZ, rZ)
+C_O1_I2(w, 0, w)
 C_O1_I2(w, w, w)
 C_O1_I2(w, w, wO)
 C_O1_I2(w, w, wV)
diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
index d19153dcb9..d38af9a808 100644
--- a/tcg/arm/tcg-target.opc.h
+++ b/tcg/arm/tcg-target.opc.h
@@ -11,5 +11,6 @@
  * consider these to be UNSPEC with names.
  */
 
+DEF(arm_sli_vec, 1, 2, 1, IMPLVEC)
 DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
 DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 2a664a750d..5cae6b2749 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -215,6 +215,7 @@ typedef enum {
     INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
     INSN_VSARI     = 0xf2800010,  /* VSHR.S */
     INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
+    INSN_VSLI      = 0xf3800510,
     INSN_VSHL_S    = 0xf2000400,  /* VSHL.S (register) */
     INSN_VSHL_U    = 0xf3000400,  /* VSHL.U (register) */
 
@@ -2400,6 +2401,8 @@ static int tcg_target_op_def(TCGOpcode op)
     case INDEX_op_arm_sshl_vec:
     case INDEX_op_arm_ushl_vec:
         return C_O1_I2(w, w, w);
+    case INDEX_op_arm_sli_vec:
+        return C_O1_I2(w, 0, w);
     case INDEX_op_or_vec:
     case INDEX_op_andc_vec:
         return C_O1_I2(w, w, wO);
@@ -2815,6 +2818,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_sari_vec:
         tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
         return;
+    case INDEX_op_arm_sli_vec:
+        tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece));
+        return;
 
     case INDEX_op_andc_vec:
         if (!const_args[2]) {
@@ -2943,6 +2949,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_shlv_vec:
     case INDEX_op_shrv_vec:
     case INDEX_op_sarv_vec:
+    case INDEX_op_rotli_vec:
         return -1;
     default:
         return 0;
@@ -2988,6 +2995,14 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
         tcg_temp_free_vec(t1);
         break;
 
+    case INDEX_op_rotli_vec:
+        t1 = tcg_temp_new_vec(type);
+        tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));
+        vec_gen_4(INDEX_op_arm_sli_vec, type, vece,
+                  tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
+        tcg_temp_free_vec(t1);
+        break;
+
     default:
         g_assert_not_reached();
     }
-- 
2.25.1



  parent reply	other threads:[~2020-12-24 22:57 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-24 22:44 [PATCH 00/15] tcg/arm: host neon support Richard Henderson
2020-12-24 22:45 ` [PATCH 01/15] tcg/arm: Add host vector framework Richard Henderson
2020-12-24 22:45 ` [PATCH 02/15] tcg/arm: Implement tcg_out_ld/st for vector types Richard Henderson
2020-12-24 22:45 ` [PATCH 03/15] tcg/arm: Implement tcg_out_mov " Richard Henderson
2020-12-24 22:45 ` [PATCH 04/15] tcg/arm: Implement tcg_out_dup*_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 05/15] tcg: Change parameters for tcg_target_const_match Richard Henderson
2020-12-24 22:45 ` [PATCH 06/15] tcg/arm: Implement minimal vector operations Richard Henderson
2020-12-24 22:45 ` [PATCH 07/15] tcg/arm: Implement andc, orc, abs, neg, not " Richard Henderson
2020-12-24 22:45 ` [PATCH 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec Richard Henderson
2020-12-24 22:45 ` [PATCH 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec Richard Henderson
2020-12-24 22:45 ` Richard Henderson [this message]
2020-12-24 22:45 ` [PATCH 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec Richard Henderson

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