[PATCH 0/5] v3u: add support for RAVB

[PATCH 0/5] v3u: add support for RAVB

[Wolfram Sang]

Here is the series to enable RAVB on V3U. I took the DTS patches
from the BSP, the rest was developed on mainline tree. Note that only
RAVB0 could be tested because the other ones did not have PHYs attached.

Also, the last patch is a workaround. 'reset-gpios' cannot be obtained
currently which makes the driver fail. The problem is that
pinctrl_ready_for_gpio_range() returns EPROBE-DEFER. I hope Geert has an
idea because I got lost in the GPIO and V3U pinctrl details there. It
seems more of a PFC/CPG/GPIO problem to me.

Without the reset-gpio, the driver binds to avb0 and I can ping the host
successfully. So, I think at least the first three patches are ready.

Let me know your thoughts!

All the best,

   Wolfram


Tho Vu (2):
  arm64: dts: renesas: r8a779a0: Add Ethernet-AVB support
  arm64: dts: renesas: falcon: Add Ethernet-AVB support

Wolfram Sang (3):
  dt-bindings: net: renesas,etheravb: Add r8a779a0 support
  clk: renesas: r8a779a0: add clocks for RAVB
  arm64: dts: r8a779a0: WIP disable reset-gpios for AVB

 .../bindings/net/renesas,etheravb.yaml        |   1 +
 .../boot/dts/renesas/r8a779a0-falcon.dts      | 195 +++++++++++++
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi     | 270 ++++++++++++++++++
 drivers/clk/renesas/r8a779a0-cpg-mssr.c       |   6 +
 4 files changed, 472 insertions(+)

-- 
2.29.2

[PATCH 1/5] dt-bindings: net: renesas,etheravb: Add r8a779a0 support

[Wolfram Sang]

Document the compatible value for the RAVB block in the Renesas R-Car
V3U (R8A779A0) SoC. This variant has no stream buffer, so we only need
to add the new compatible.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 Documentation/devicetree/bindings/net/renesas,etheravb.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
index 244befb6402a..6e57e4f157f0 100644
--- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
@@ -40,6 +40,7 @@ properties:
               - renesas,etheravb-r8a77980     # R-Car V3H
               - renesas,etheravb-r8a77990     # R-Car E3
               - renesas,etheravb-r8a77995     # R-Car D3
+              - renesas,etheravb-r8a779a0     # R-Car V3U
           - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
 
   reg: true
-- 
2.29.2

[PATCH 2/5] clk: renesas: r8a779a0: add clocks for RAVB

[Wolfram Sang]

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 04514140e615..5be70a6a7904 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -148,6 +148,12 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
+	DEF_MOD("avb0",		211,	R8A779A0_CLK_S3D1),
+	DEF_MOD("avb1",		212,	R8A779A0_CLK_S3D1),
+	DEF_MOD("avb2",		213,	R8A779A0_CLK_S3D1),
+	DEF_MOD("avb3",		214,	R8A779A0_CLK_S3D1),
+	DEF_MOD("avb4",		215,	R8A779A0_CLK_S3D1),
+	DEF_MOD("avb5",		216,	R8A779A0_CLK_S3D1),
 	DEF_MOD("csi40",	331,	R8A779A0_CLK_CSI0),
 	DEF_MOD("csi41",	400,	R8A779A0_CLK_CSI0),
 	DEF_MOD("csi42",	401,	R8A779A0_CLK_CSI0),
-- 
2.29.2

[PATCH 3/5] arm64: dts: renesas: r8a779a0: Add Ethernet-AVB support

[Wolfram Sang]

From: Tho Vu <tho.vu.wh@renesas.com>

Define the generic parts of Ethernet-AVB device nodes. Only AVB0 was
tested because it was the only port with a PHY on current hardware.

Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
[wsa: double checked & rebased]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 270 ++++++++++++++++++++++
 1 file changed, 270 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 16c64ec548df..324deeed9078 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -377,6 +377,276 @@ i2c6: i2c@e66e8000 {
 			status = "disabled";
 		};
 
+		avb0: ethernet@e6800000 {
+			compatible = "renesas,etheravb-r8a779a0",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6800000 0 0x800>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "ch22", "ch23",
+					  "ch24";
+			clocks = <&cpg CPG_MOD 211>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets = <&cpg 211>;
+			phy-mode = "rgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		avb1: ethernet@e6810000 {
+			compatible = "renesas,etheravb-r8a779a0",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6810000 0 0x800>;
+			interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "ch16", "ch17", "ch18", "ch19",
+					  "ch20", "ch21", "ch22", "ch23",
+					  "ch24";
+			clocks = <&cpg CPG_MOD 212>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets = <&cpg 212>;
+			phy-mode = "rgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		avb2: ethernet@e6820000 {
+			compatible = "renesas,etheravb-r8a779a0",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6820000 0 0x1000>;
+			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15",
+					"ch16", "ch17", "ch18", "ch19",
+					"ch20", "ch21", "ch22", "ch23",
+					"ch24";
+			clocks = <&cpg CPG_MOD 213>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets = <&cpg 213>;
+			phy-mode = "rgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		avb3: ethernet@e6830000 {
+			compatible = "renesas,etheravb-r8a779a0",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6830000 0 0x1000>;
+			interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15",
+					"ch16", "ch17", "ch18", "ch19",
+					"ch20", "ch21", "ch22", "ch23",
+					"ch24";
+			clocks = <&cpg CPG_MOD 214>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets = <&cpg 214>;
+			phy-mode = "rgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		avb4: ethernet@e6840000 {
+			compatible = "renesas,etheravb-r8a779a0",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6840000 0 0x1000>;
+			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15",
+					"ch16", "ch17", "ch18", "ch19",
+					"ch20", "ch21", "ch22", "ch23",
+					"ch24";
+			clocks = <&cpg CPG_MOD 215>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets = <&cpg 215>;
+			phy-mode = "rgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		avb5: ethernet@e6850000 {
+			compatible = "renesas,etheravb-r8a779a0",
+				     "renesas,etheravb-rcar-gen3";
+			reg = <0 0xe6850000 0 0x1000>;
+			interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					"ch4", "ch5", "ch6", "ch7",
+					"ch8", "ch9", "ch10", "ch11",
+					"ch12", "ch13", "ch14", "ch15",
+					"ch16", "ch17", "ch18", "ch19",
+					"ch20", "ch21", "ch22", "ch23",
+					"ch24";
+			clocks = <&cpg CPG_MOD 216>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets = <&cpg 216>;
+			phy-mode = "rgmii";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		scif0: serial@e6e60000 {
 			compatible = "renesas,scif-r8a779a0",
 				     "renesas,rcar-gen3-scif", "renesas,scif";
-- 
2.29.2

[PATCH 4/5] arm64: dts: renesas: falcon: Add Ethernet-AVB support

[Wolfram Sang]

From: Tho Vu <tho.vu.wh@renesas.com>

Define the Falcon board dependent part of the Ethernet-AVB device nodes.
Only AVB0 was tested because it was the only port with a PHY on current
hardware.

Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
[wsa: rebased]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 .../boot/dts/renesas/r8a779a0-falcon.dts      | 195 ++++++++++++++++++
 1 file changed, 195 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
index f7f62fc40429..f5f27dece6ee 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 #include "r8a779a0-falcon-cpu.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
@@ -21,6 +22,97 @@ chosen {
 	};
 };
 
+&avb0 {
+	pinctrl-0 = <&avb0_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&phy0>;
+	phy-mode = "rgmii-txid";
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&avb1 {
+	pinctrl-0 = <&avb1_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&phy1>;
+	phy-mode = "rgmii-txid";
+
+	phy1: ethernet-phy@1 {
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&avb2 {
+	pinctrl-0 = <&avb2_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&phy2>;
+	phy-mode = "rgmii-txid";
+
+	phy2: ethernet-phy@2 {
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&avb3 {
+	pinctrl-0 = <&avb3_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&phy3>;
+	phy-mode = "rgmii-txid";
+
+	phy3: ethernet-phy@3{
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupt-parent = <&gpio7>;
+		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&avb4 {
+	pinctrl-0 = <&avb4_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&phy4>;
+	phy-mode = "rgmii-txid";
+
+	phy4: ethernet-phy@4 {
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupt-parent = <&gpio8>;
+		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio8 15 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&avb5 {
+	pinctrl-0 = <&avb5_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&phy5>;
+	phy-mode = "rgmii-txid";
+
+	phy5: ethernet-phy@5 {
+		rxc-skew-ps = <1500>;
+		reg = <0>;
+		interrupt-parent = <&gpio9>;
+		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpios = <&gpio9 15 GPIO_ACTIVE_LOW>;
+	};
+};
+
 &i2c0 {
 	pinctrl-0 = <&i2c0_pins>;
 	pinctrl-names = "default";
@@ -78,6 +170,109 @@ &i2c6 {
 };
 
 &pfc {
+	avb0_pins: avb0 {
+		mux {
+			groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
+			function = "avb0";
+		};
+
+		pins_mdio {
+			groups = "avb0_mdio";
+			drive-strength = <21>;
+		};
+
+		pins_mii_tx {
+			groups = "avb0_rgmii";
+			drive-strength = <21>;
+		};
+
+	};
+
+	avb1_pins: avb1 {
+		mux {
+			groups = "avb1_link", "avb1_mdio", "avb1_rgmii", "avb1_txcrefclk";
+			function = "avb1";
+		};
+
+		pins_mdio {
+			groups = "avb1_mdio";
+			drive-strength = <21>;
+		};
+
+		pins_mii_tx {
+			groups = "avb1_rgmii";
+			drive-strength = <21>;
+		};
+	};
+
+	avb2_pins: avb2 {
+		mux {
+			groups = "avb2_link", "avb2_mdio", "avb2_rgmii", "avb2_txcrefclk";
+			function = "avb2";
+		};
+
+		pins_mdio {
+			groups = "avb2_mdio";
+			drive-strength = <21>;
+		};
+
+		pins_mii_tx {
+			groups = "avb2_rgmii";
+			drive-strength = <21>;
+		};
+	};
+
+	avb3_pins: avb3 {
+		mux {
+			groups = "avb3_link", "avb3_mdio", "avb3_rgmii", "avb3_txcrefclk";
+			function = "avb3";
+		};
+
+		pins_mdio {
+			groups = "avb3_mdio";
+			drive-strength = <21>;
+		};
+
+		pins_mii_tx {
+			groups = "avb3_rgmii";
+			drive-strength = <21>;
+		};
+	};
+
+	avb4_pins: avb4 {
+		mux {
+			groups = "avb4_link", "avb4_mdio", "avb4_rgmii", "avb4_txcrefclk";
+			function = "avb4";
+		};
+
+		pins_mdio {
+			groups = "avb4_mdio";
+			drive-strength = <21>;
+		};
+
+		pins_mii_tx {
+			groups = "avb4_rgmii";
+			drive-strength = <21>;
+		};
+	};
+
+	avb5_pins: avb5 {
+		mux {
+			groups = "avb5_link", "avb5_mdio", "avb5_rgmii", "avb5_txcrefclk";
+			function = "avb5";
+		};
+
+		pins_mdio {
+			groups = "avb5_mdio";
+			drive-strength = <21>;
+		};
+
+		pins_mii_tx {
+			groups = "avb5_rgmii";
+			drive-strength = <21>;
+		};
+	};
+
 	i2c0_pins: i2c0 {
 		groups = "i2c0";
 		function = "i2c0";
-- 
2.29.2

[PATCH 5/5] arm64: dts: r8a779a0: WIP disable reset-gpios for AVB

[Wolfram Sang]

Retrieving a GPIO currently fails, so probing the whole driver fails
then. Remove them for now to get a working AVB device for testing.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
index f5f27dece6ee..48801f2bdbe5 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
@@ -34,7 +34,7 @@ phy0: ethernet-phy@0 {
 		reg = <0>;
 		interrupt-parent = <&gpio4>;
 		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
+		//reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -49,7 +49,7 @@ phy1: ethernet-phy@1 {
 		reg = <0>;
 		interrupt-parent = <&gpio5>;
 		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
+		//reset-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -64,7 +64,7 @@ phy2: ethernet-phy@2 {
 		reg = <0>;
 		interrupt-parent = <&gpio6>;
 		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
+		//reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -79,7 +79,7 @@ phy3: ethernet-phy@3{
 		reg = <0>;
 		interrupt-parent = <&gpio7>;
 		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
+		//reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -94,7 +94,7 @@ phy4: ethernet-phy@4 {
 		reg = <0>;
 		interrupt-parent = <&gpio8>;
 		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio8 15 GPIO_ACTIVE_LOW>;
+		//reset-gpios = <&gpio8 15 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -109,7 +109,7 @@ phy5: ethernet-phy@5 {
 		reg = <0>;
 		interrupt-parent = <&gpio9>;
 		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
-		reset-gpios = <&gpio9 15 GPIO_ACTIVE_LOW>;
+		//reset-gpios = <&gpio9 15 GPIO_ACTIVE_LOW>;
 	};
 };
 
-- 
2.29.2

Re: [PATCH 5/5] arm64: dts: r8a779a0: WIP disable reset-gpios for AVB

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 491 bytes --]

On Sun, Dec 27, 2020 at 02:04:06PM +0100, Wolfram Sang wrote:
> Retrieving a GPIO currently fails, so probing the whole driver fails
> then. Remove them for now to get a working AVB device for testing.
> 
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

I just pushed out another version of this branch. There, in the
depending gpio branch, a fix for the GPIO DTS addition has been applied,
so 'reset-gpios' work now as expected. So, this patch has been dropped.


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Re: [PATCH 1/5] dt-bindings: net: renesas,etheravb: Add r8a779a0 support

[Geert Uytterhoeven]

Hi Wolfram,

On Sun, Dec 27, 2020 at 2:06 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Document the compatible value for the RAVB block in the Renesas R-Car
> V3U (R8A779A0) SoC. This variant has no stream buffer, so we only need
> to add the new compatible.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
> +++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
> @@ -40,6 +40,7 @@ properties:
>                - renesas,etheravb-r8a77980     # R-Car V3H
>                - renesas,etheravb-r8a77990     # R-Car E3
>                - renesas,etheravb-r8a77995     # R-Car D3
> +              - renesas,etheravb-r8a779a0     # R-Car V3U
>            - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
>
>    reg: true

EtherAVB on R-Car V3U does have the Tx clock internal Delay Mode
bit in the APSR register, so its compatible value should be added to
the list of SoCs where tx-internal-delay-ps is required.

With that fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

The various Counter Registers starting at offset 0x700 are limited to
16-bit values, like on R-Car Gen2, while they support 32-bit values on
other R-Car Gen3 variants. The driver uses only the Transmit Retry Over
Counter Register (TROCR), for statistics, so we can just ignore that
difference.

V3U also has a new block of registers related to UDP/IP support (offset
0x800 and up).  I guess we can just ignore them too, for now.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/5] clk: renesas: r8a779a0: add clocks for RAVB

[Geert Uytterhoeven]

Hi Wolfram,

On Sun, Dec 27, 2020 at 2:04 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> @@ -148,6 +148,12 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
>  };
>
>  static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
> +       DEF_MOD("avb0",         211,    R8A779A0_CLK_S3D1),
> +       DEF_MOD("avb1",         212,    R8A779A0_CLK_S3D1),
> +       DEF_MOD("avb2",         213,    R8A779A0_CLK_S3D1),
> +       DEF_MOD("avb3",         214,    R8A779A0_CLK_S3D1),
> +       DEF_MOD("avb4",         215,    R8A779A0_CLK_S3D1),
> +       DEF_MOD("avb5",         216,    R8A779A0_CLK_S3D1),

For all other SoCs, we used the HP clock (S3D2 on R-Car V3U) instead
of the ZS clock as the parent clock of the EtherAVB module clocks.
Hence I think we should be consequent and use S3D2 here.

>         DEF_MOD("csi40",        331,    R8A779A0_CLK_CSI0),
>         DEF_MOD("csi41",        400,    R8A779A0_CLK_CSI0),
>         DEF_MOD("csi42",        401,    R8A779A0_CLK_CSI0),

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/5] arm64: dts: renesas: r8a779a0: Add Ethernet-AVB support

[Geert Uytterhoeven]

Hi Wolfram,

On Sun, Dec 27, 2020 at 2:04 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> From: Tho Vu <tho.vu.wh@renesas.com>
>
> Define the generic parts of Ethernet-AVB device nodes. Only AVB0 was
> tested because it was the only port with a PHY on current hardware.
>
> Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
> [wsa: double checked & rebased]
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -377,6 +377,276 @@ i2c6: i2c@e66e8000 {
>                         status = "disabled";
>                 };
>
> +               avb0: ethernet@e6800000 {
> +                       compatible = "renesas,etheravb-r8a779a0",
> +                                    "renesas,etheravb-rcar-gen3";
> +                       reg = <0 0xe6800000 0 0x800>;
> +                       interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "ch0", "ch1", "ch2", "ch3",
> +                                         "ch4", "ch5", "ch6", "ch7",
> +                                         "ch8", "ch9", "ch10", "ch11",
> +                                         "ch12", "ch13", "ch14", "ch15",
> +                                         "ch16", "ch17", "ch18", "ch19",
> +                                         "ch20", "ch21", "ch22", "ch23",
> +                                         "ch24";
> +                       clocks = <&cpg CPG_MOD 211>;
> +                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> +                       resets = <&cpg 211>;
> +                       phy-mode = "rgmii";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       status = "disabled";

$ make dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/renesas,etheravb.yaml
arch/arm64/boot/dts/renesas/r8a779a0-falcon.dt.yaml:
ethernet@e6800000: 'rx-internal-delay-ps' is a required property

Similarly, "tx-internal-delay-ps" should be added to all instances, too.

The rest looks good to me, so with the above fixed:

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/5] arm64: dts: renesas: falcon: Add Ethernet-AVB support

[Geert Uytterhoeven]

Hi Wolfram,

Thanks for your patch!

On Sun, Dec 27, 2020 at 2:04 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> From: Tho Vu <tho.vu.wh@renesas.com>
>
> Define the Falcon board dependent part of the Ethernet-AVB device nodes.
> Only AVB0 was tested because it was the only port with a PHY on current
> hardware.

I'm a bit confused: according to the schematics, AVB0 is wired by
default to a KSZ9031 PHY connected to an RJ45 connector on the
breakout-board, while AVB1-5 are wired to 88Q2110 PHYs connected to a
5port MATEnet connector on the Ethernet sub board.  So all PHYs are
present?

(The alternative wiring for AVB0 is to a 88Q2110 PHY connected to a
1000Base-T1/TE MATEnet connector on the Ethernet sub board)

>
> Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
> [wsa: rebased]
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

> --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
> @@ -7,6 +7,7 @@
>
>  /dts-v1/;
>  #include "r8a779a0-falcon-cpu.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
>
>  / {
>         model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";

Missing ethernet0 alias, preventing U-Boot from finding the device-node
and adding an appropriate "local-mac-address" property.

> @@ -21,6 +22,97 @@ chosen {
>         };
>  };
>
> +&avb0 {
> +       pinctrl-0 = <&avb0_pins>;
> +       pinctrl-names = "default";
> +       phy-handle = <&phy0>;
> +       phy-mode = "rgmii-txid";

As the default wiring of AVB0 is similar to Salvator-XS, I think the
default phy-mode of "rgmii" in the base .dtsi should be fine, but
"tx-internal-delay-ps" should be overridden to <2000>.

> +       status = "okay";
> +
> +       phy0: ethernet-phy@0 {
> +               rxc-skew-ps = <1500>;
> +               reg = <0>;
> +               interrupt-parent = <&gpio4>;
> +               interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
> +               reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
> +       };
> +};
> +
> +&avb1 {
> +       pinctrl-0 = <&avb1_pins>;
> +       pinctrl-names = "default";
> +       phy-handle = <&phy1>;
> +       phy-mode = "rgmii-txid";
> +
> +       phy1: ethernet-phy@1 {

Why not @0?
As the PHYs are present, why not set "status" to "okay"?

> +               rxc-skew-ps = <1500>;

This property is only supported by the Micrel PHY driver, not by
the Marvell PHY driver.

> +               reg = <0>;
> +               interrupt-parent = <&gpio5>;
> +               interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
> +               reset-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
> +       };
> +};

Same questions and comments for all instances below.
Perhaps we should postpone adding avb1-5 until they can be tested?

> @@ -78,6 +170,109 @@ &i2c6 {
>  };
>
>  &pfc {
> +       avb0_pins: avb0 {
> +               mux {
> +                       groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
> +                       function = "avb0";
> +               };
> +
> +               pins_mdio {
> +                       groups = "avb0_mdio";
> +                       drive-strength = <21>;
> +               };
> +
> +               pins_mii_tx {

Strange node name, as the "avb0_rgmii" group includes rx pins.

> +                       groups = "avb0_rgmii";
> +                       drive-strength = <21>;

I can't comment on the drive-strength values.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/5] arm64: dts: renesas: falcon: Add Ethernet-AVB support

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 458 bytes --]

Hi Geert,

thank you for the reviews!

> breakout-board, while AVB1-5 are wired to 88Q2110 PHYs connected to a
> 5port MATEnet connector on the Ethernet sub board.  So all PHYs are
> present?

I was under the assumption that we don't have the ethernet sub board in
the lab. Sorry if I was wrong. Then I was probably just missing the
correct Marvell driver for the phys when I tried to fire the interface
up. I will retry (with your other suggestions, too).


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Re: [PATCH 1/5] dt-bindings: net: renesas,etheravb: Add r8a779a0 support

[Rob Herring]

On Sun, 27 Dec 2020 14:04:02 +0100, Wolfram Sang wrote:
> Document the compatible value for the RAVB block in the Renesas R-Car
> V3U (R8A779A0) SoC. This variant has no stream buffer, so we only need
> to add the new compatible.
> 
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>  Documentation/devicetree/bindings/net/renesas,etheravb.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 4/5] arm64: dts: renesas: falcon: Add Ethernet-AVB support

[Geert Uytterhoeven]

Hi Wolfram,

On Tue, Jan 5, 2021 at 5:27 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> > breakout-board, while AVB1-5 are wired to 88Q2110 PHYs connected to a
> > 5port MATEnet connector on the Ethernet sub board.  So all PHYs are
> > present?
>
> I was under the assumption that we don't have the ethernet sub board in
> the lab. Sorry if I was wrong. Then I was probably just missing the
> correct Marvell driver for the phys when I tried to fire the interface
> up. I will retry (with your other suggestions, too).

Actually I don't know if the Ethernet sub board is present or not :-)

Which reminds me that the avb0 extensions should be added to
r8a779a0-falcon-cpu.dtsi instead of r8a779a0-falcon.dts

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds