From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BB05C433DB for ; Tue, 29 Dec 2020 06:32:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 24CB121D7F for ; Tue, 29 Dec 2020 06:32:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726517AbgL2Gcd (ORCPT ); Tue, 29 Dec 2020 01:32:33 -0500 Received: from twspam01.aspeedtech.com ([211.20.114.71]:22588 "EHLO twspam01.aspeedtech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725767AbgL2Gcd (ORCPT ); Tue, 29 Dec 2020 01:32:33 -0500 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 0BT6RTSM012593; Tue, 29 Dec 2020 14:27:29 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 29 Dec 2020 14:31:35 +0800 From: "Chia-Wei, Wang" To: , , , , , , , , , , CC: , , , Subject: [PATCH v4 0/5] Remove LPC register partitioning Date: Tue, 29 Dec 2020 14:31:52 +0800 Message-ID: <20201229063157.3587-1-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 0BT6RTSM012593 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The LPC controller has no concept of the BMC and the Host partitions. The incorrect partitioning can impose unnecessary range restrictions on register access through the syscon regmap interface. For instance, HICRB contains the I/O port address configuration of KCS channel 1/2. However, the KCS#1/#2 drivers cannot access HICRB as it is located at the other LPC partition. In addition, to be backward compatible, the newly added HW control bits could be located at any reserved bits over the LPC addressing space. Thereby, this patch series aims to remove the LPC partitioning for better driver development and maintenance. This requires the change to both the device tree and the driver implementation. To ensure both sides are synchronously updated, a v2 binding check is added. Chagnes since v3: - Revise binding check as suggested by Haiyue Wang Changes since v2: - Add v2 binding check to ensure the synchronization between the device tree change and the driver register offset fix. Changes since v1: - Add the fix to the aspeed-lpc binding documentation. Chia-Wei, Wang (5): dt-bindings: aspeed-lpc: Remove LPC partitioning ARM: dts: Remove LPC BMC and Host partitions ipmi: kcs: aspeed: Adapt to new LPC DTS layout pinctrl: aspeed-g5: Adapt to new LPC device tree layout soc: aspeed: Adapt to new LPC device tree layout .../devicetree/bindings/mfd/aspeed-lpc.txt | 99 +++---------- arch/arm/boot/dts/aspeed-g4.dtsi | 74 ++++------ arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++---------- arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++---------- drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ++-- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 ++- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++- drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +-- 8 files changed, 225 insertions(+), 305 deletions(-) -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13C32C433E0 for ; Tue, 29 Dec 2020 06:38:04 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6CF1A207AB for ; Tue, 29 Dec 2020 06:38:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6CF1A207AB Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4D4l9358JnzDqGp for ; Tue, 29 Dec 2020 17:37:59 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; spf=fail (SPF fail - not authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.71; helo=twspam01.aspeedtech.com; envelope-from=chiawei_wang@aspeedtech.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=aspeedtech.com Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4D4l3p12VhzDqFw; Tue, 29 Dec 2020 17:33:23 +1100 (AEDT) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 0BT6RTSM012593; Tue, 29 Dec 2020 14:27:29 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 29 Dec 2020 14:31:35 +0800 From: "Chia-Wei, Wang" To: , , , , , , , , , , Subject: [PATCH v4 0/5] Remove LPC register partitioning Date: Tue, 29 Dec 2020 14:31:52 +0800 Message-ID: <20201229063157.3587-1-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 0BT6RTSM012593 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: BMC-SW@aspeedtech.com, cyrilbur@gmail.com, haiyue.wang@linux.intel.com Errors-To: openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Sender: "openbmc" The LPC controller has no concept of the BMC and the Host partitions. The incorrect partitioning can impose unnecessary range restrictions on register access through the syscon regmap interface. For instance, HICRB contains the I/O port address configuration of KCS channel 1/2. However, the KCS#1/#2 drivers cannot access HICRB as it is located at the other LPC partition. In addition, to be backward compatible, the newly added HW control bits could be located at any reserved bits over the LPC addressing space. Thereby, this patch series aims to remove the LPC partitioning for better driver development and maintenance. This requires the change to both the device tree and the driver implementation. To ensure both sides are synchronously updated, a v2 binding check is added. Chagnes since v3: - Revise binding check as suggested by Haiyue Wang Changes since v2: - Add v2 binding check to ensure the synchronization between the device tree change and the driver register offset fix. Changes since v1: - Add the fix to the aspeed-lpc binding documentation. Chia-Wei, Wang (5): dt-bindings: aspeed-lpc: Remove LPC partitioning ARM: dts: Remove LPC BMC and Host partitions ipmi: kcs: aspeed: Adapt to new LPC DTS layout pinctrl: aspeed-g5: Adapt to new LPC device tree layout soc: aspeed: Adapt to new LPC device tree layout .../devicetree/bindings/mfd/aspeed-lpc.txt | 99 +++---------- arch/arm/boot/dts/aspeed-g4.dtsi | 74 ++++------ arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++---------- arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++---------- drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ++-- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 ++- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++- drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +-- 8 files changed, 225 insertions(+), 305 deletions(-) -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26561C433E0 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The LPC controller has no concept of the BMC and the Host partitions. The incorrect partitioning can impose unnecessary range restrictions on register access through the syscon regmap interface. For instance, HICRB contains the I/O port address configuration of KCS channel 1/2. However, the KCS#1/#2 drivers cannot access HICRB as it is located at the other LPC partition. In addition, to be backward compatible, the newly added HW control bits could be located at any reserved bits over the LPC addressing space. Thereby, this patch series aims to remove the LPC partitioning for better driver development and maintenance. This requires the change to both the device tree and the driver implementation. To ensure both sides are synchronously updated, a v2 binding check is added. Chagnes since v3: - Revise binding check as suggested by Haiyue Wang Changes since v2: - Add v2 binding check to ensure the synchronization between the device tree change and the driver register offset fix. Changes since v1: - Add the fix to the aspeed-lpc binding documentation. Chia-Wei, Wang (5): dt-bindings: aspeed-lpc: Remove LPC partitioning ARM: dts: Remove LPC BMC and Host partitions ipmi: kcs: aspeed: Adapt to new LPC DTS layout pinctrl: aspeed-g5: Adapt to new LPC device tree layout soc: aspeed: Adapt to new LPC device tree layout .../devicetree/bindings/mfd/aspeed-lpc.txt | 99 +++---------- arch/arm/boot/dts/aspeed-g4.dtsi | 74 ++++------ arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++---------- arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++---------- drivers/char/ipmi/kcs_bmc_aspeed.c | 27 ++-- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 17 ++- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 20 ++- drivers/soc/aspeed/aspeed-lpc-snoop.c | 23 +-- 8 files changed, 225 insertions(+), 305 deletions(-) -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel