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[79.178.32.166]) by smtp.gmail.com with ESMTPSA id c16sm45237501wrx.51.2020.12.30.13.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Dec 2020 13:17:18 -0800 (PST) Date: Wed, 30 Dec 2020 16:17:14 -0500 From: "Michael S. Tsirkin" To: Igor Mammedov Subject: Re: [PATCH v3 5/8] acpi/gpex: Append pxb devs in ascending order Message-ID: <20201230160814-mutt-send-email-mst@kernel.org> References: <20201223090836.9075-1-cenjiahui@huawei.com> <20201223090836.9075-6-cenjiahui@huawei.com> <20201229144735.42faddad@redhat.com> MIME-Version: 1.0 In-Reply-To: <20201229144735.42faddad@redhat.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=216.205.24.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Jiahui Cen , Eduardo Habkost , Ard Biesheuvel , Richard Henderson , qemu-devel@nongnu.org, Paolo Bonzini , Laszlo Ersek , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Dec 29, 2020 at 02:47:35PM +0100, Igor Mammedov wrote: > On Wed, 23 Dec 2020 17:08:33 +0800 > Jiahui Cen wrote: > > > The overlap check of IO resource window would fail when Linux kernel > > registers an IO resource [b, c) earlier than another resource [a, b). > > Though this incorrect check could be fixed by [1], it would be better to > > append pxb devs into DSDT table in ascending order. > > > > [1]: https://lore.kernel.org/lkml/20201218062335.5320-1-cenjiahui@huawei.com/ > > considering there is acceptable fix for kernel I'd rather avoid > workarounds on QEMU side. So I suggest dropping this patch. Well there's something to be said for a defined order of things. And patch is from Dec 2020 will take ages for guests to be fixed, and changing pci core on stable kernels is risky and needs a ton of testing, not done eaily ... Which guests are affected by the bug? There are also some issues with the patch see below. > it also should reduce noise in [8/8] masking other changes. > > > Signed-off-by: Jiahui Cen > > --- > > hw/pci-host/gpex-acpi.c | 11 +++++++++-- > > 1 file changed, 9 insertions(+), 2 deletions(-) > > > > diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c > > index 4bf1e94309..95a7a0f12b 100644 > > --- a/hw/pci-host/gpex-acpi.c > > +++ b/hw/pci-host/gpex-acpi.c > > @@ -141,7 +141,7 @@ static void acpi_dsdt_add_pci_osc(Aml *dev) > > void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) > > { > > int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; > > - Aml *method, *crs, *dev, *rbuf; > > + Aml *method, *crs, *dev, *rbuf, *pxb_devs[nr_pcie_buses]; dynamically sized array on stack poses security issues > > PCIBus *bus = cfg->bus; > > CrsRangeSet crs_range_set; > > CrsRangeEntry *entry; > > @@ -149,6 +149,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) > > > > /* start to construct the tables for pxb */ > > crs_range_set_init(&crs_range_set); > > + memset(pxb_devs, 0, sizeof(pxb_devs)); > > if (bus) { > > QLIST_FOREACH(bus, &bus->child, sibling) { > > uint8_t bus_num = pci_bus_num(bus); > > @@ -190,7 +191,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) > > > > acpi_dsdt_add_pci_osc(dev); > > > > - aml_append(scope, dev); > > + pxb_devs[bus_num] = dev; If bus numbers intersect this will overwrite old one. I'd rather not worry about it, just have an array of structs with bus numbers and sort it. > > } > > } > > > > @@ -278,5 +279,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) > > aml_append(dev, dev_res0); > > aml_append(scope, dev); > > > > + for (i = 0; i < ARRAY_SIZE(pxb_devs); i++) { > > + if (pxb_devs[i]) { > > + aml_append(scope, pxb_devs[i]); > > + } > > + } so this sorts them by bus number not by io address. Probably happens to help since bios numbers them in the same order ... Is there a way to address this more robustly in case bios changes? E.g. I see the bug is only in PIO so sort by that address maybe? Also pls add a code comment explaining why we are doing all this with link to patch, which guests are affected etc. > > + > > crs_range_set_free(&crs_range_set); > > }