From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E166DC433E6 for ; Thu, 31 Dec 2020 07:55:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B04192222D for ; Thu, 31 Dec 2020 07:55:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726323AbgLaHz0 (ORCPT ); Thu, 31 Dec 2020 02:55:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726130AbgLaHz0 (ORCPT ); Thu, 31 Dec 2020 02:55:26 -0500 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 356A2C061799 for ; Wed, 30 Dec 2020 23:54:46 -0800 (PST) Received: by mail-pl1-x630.google.com with SMTP id q4so9736270plr.7 for ; Wed, 30 Dec 2020 23:54:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=LjRECRtXIzwtRi7U4uWbCOAACvteq5kQEsUibs961Aw=; b=eRyeXnAgxzHv2sIST/aF1FE0S5bB0fG5s3OFAU9Mig/dUKdY5CLYRbIz7fOmO+Q4+d o6eeuqqNT8nzu5n82t3N+VgJhnvemmvg2xzLahiXRVHWSB8im9hJw5x51ytnFpTzBxAc PqgXoXWPGBSpxcM7OVvbkzxbQ+sGszr8pMr1ciwHU2WCDPSg6k4Nw4jqan4UjA0l6i2z TwfOii3APxx1q2r7/pAUVdyyH5PmQkBFV0drfCZedZbmTKDrzOMWWU3t7ol0I+UZAldX WJCpif5reqZ3/IpIqFraKYhl0F8sWyD7GukX1qS6Ba0nGbupRe4gUvHqRV5QLNvKGSnp mx2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=LjRECRtXIzwtRi7U4uWbCOAACvteq5kQEsUibs961Aw=; b=nh8jUDePkzW8036vhI0qwTS2TqrmmGF0sHU1NcQlEDo/gMY/b7aTaPjgD0dO+hCeTx UMFGLr9HFGrSmUfIYXR4B3yD3+SGjEmD4Grue6l79wGWHpa8JXvD/ZSF1PtwfhVtCHJX nDk9Iih5dizMwc6a5SGNMvr7JdJEZ2S49Tx8LJdLWZcaLbsgYFocxwGPHZ75H1m+jhGE wX8GMpWBNeqLkMIrsLOXpTibRwaxbBBT9ldkj1p0IF6Ssnyoz97twZcglyAzbs+C6V5r S+RVo1/8FsXrrtFka4vid6+ovL5IhR5TqIbM7TH+exOCgLnGvxfU9rbIrKWbKh6LPAzP cX0g== X-Gm-Message-State: AOAM531diTQFRFEYUZ8SSFptApozsE76bBmvtpbWcHY3hodW/nu0jtk8 amxdZ8ZRmqWjvVQ06UAtY5cY X-Google-Smtp-Source: ABdhPJy5P7AJ+WidqF/ZjXD1Won5mShdQwBoju/Dg6zwADGelOsHTdEdZSA8RHSVZHyR1QuZyCNbZg== X-Received: by 2002:a17:90a:348f:: with SMTP id p15mr12316040pjb.125.1609401284765; Wed, 30 Dec 2020 23:54:44 -0800 (PST) Received: from thinkpad ([2409:4072:6d1f:be3b:71a9:d2bf:a32d:897d]) by smtp.gmail.com with ESMTPSA id z28sm46534047pfr.140.2020.12.30.23.54.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Dec 2020 23:54:43 -0800 (PST) Date: Thu, 31 Dec 2020 13:24:35 +0530 From: Manivannan Sadhasivam To: Cristian Ciocaltea Cc: Rob Herring , Andreas =?iso-8859-1?Q?F=E4rber?= , Vinod Koul , Dan Williams , Wolfram Sang , Ulf Hansson , Peter Korsgaard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-i2c@vger.kernel.org, linux-mmc@vger.kernel.org Subject: Re: [PATCH v3 00/13] Add CMU/RMU/DMA/MMC/I2C support for Actions Semi Message-ID: <20201231075435.GG7345@thinkpad> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On Tue, Dec 29, 2020 at 11:17:15PM +0200, Cristian Ciocaltea wrote: > Hi, > > This patchset brings a series of improvements for the Actions Semi S500 > SoCs family, by adding support for Clock & Reset Management Units, DMA, > MMC, I2C & SIRQ controllers. > > Please note the patches consist mostly of DTS and bindings/compatibles > changes, since all the work they depend on has been already merged, > i.e. clock fixes/additions, pinctrl driver, sirq driver. > > For the moment, I have only enabled the features I could test on > RoseapplePi SBC. > Applied all patches except the 2 dmaengine patches for v5.12. Andreas, please let me know if you want to do the PR this time. Else I'll proceed. Thanks, Mani > Thanks, > Cristi > > Changes in v3: > - Squashed 'arm: dts: owl-s500-roseapplepi: Use UART clock from CMU' with > 'arm: dts: owl-s500: Set CMU clocks for UARTs', according to Mani's review > - Rebased series on v5.11-rc1 and dropped the already merged patches: > * dt-bindings: mmc: owl: Add compatible string for Actions Semi S500 SoC > * dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema > * MAINTAINERS: Update entry for Actions Semi Owl I2C binding > * i2c: owl: Add compatible for the Actions Semi S500 I2C controller > > Changes in v2: > - Added new bindings/compatibles for S500 DMA, MMC & I2C controllers > - Added support for the SIRQ controller > - Added new entries in MAINTAINERS > - Updated naming of some patches in v1 > > Cristian Ciocaltea (13): > arm: dts: owl-s500: Add Clock Management Unit > arm: dts: owl-s500: Set CMU clocks for UARTs > arm: dts: owl-s500: Add Reset controller > dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC > dmaengine: owl: Add compatible for the Actions Semi S500 DMA > controller > arm: dts: owl-s500: Add DMA controller > arm: dts: owl-s500: Add pinctrl & GPIO support > arm: dts: owl-s500: Add MMC support > arm: dts: owl-s500: Add I2C support > arm: dts: owl-s500: Add SIRQ controller > arm: dts: owl-s500-roseapplepi: Add uSD support > arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration > MAINTAINERS: Add linux-actions ML for Actions Semi Arch > > .../devicetree/bindings/dma/owl-dma.yaml | 7 +- > MAINTAINERS | 1 + > arch/arm/boot/dts/owl-s500-cubieboard6.dts | 7 - > .../arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 - > .../arm/boot/dts/owl-s500-labrador-base-m.dts | 7 - > arch/arm/boot/dts/owl-s500-roseapplepi.dts | 97 +++++++++++- > arch/arm/boot/dts/owl-s500-sparky.dts | 7 - > arch/arm/boot/dts/owl-s500.dtsi | 140 ++++++++++++++++++ > drivers/dma/owl-dma.c | 3 +- > 9 files changed, 239 insertions(+), 37 deletions(-) > > -- > 2.30.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87F68C433DB for ; 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Wed, 30 Dec 2020 23:54:44 -0800 (PST) Received: from thinkpad ([2409:4072:6d1f:be3b:71a9:d2bf:a32d:897d]) by smtp.gmail.com with ESMTPSA id z28sm46534047pfr.140.2020.12.30.23.54.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Dec 2020 23:54:43 -0800 (PST) Date: Thu, 31 Dec 2020 13:24:35 +0530 From: Manivannan Sadhasivam To: Cristian Ciocaltea Subject: Re: [PATCH v3 00/13] Add CMU/RMU/DMA/MMC/I2C support for Actions Semi Message-ID: <20201231075435.GG7345@thinkpad> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201231_025447_682713_8FAC9EF9 X-CRM114-Status: GOOD ( 22.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Ulf Hansson , linux-mmc@vger.kernel.org, linux-actions@lists.infradead.org, Peter Korsgaard , linux-kernel@vger.kernel.org, Wolfram Sang , Vinod Koul , Rob Herring , linux-i2c@vger.kernel.org, dmaengine@vger.kernel.org, Dan Williams , Andreas =?iso-8859-1?Q?F=E4rber?= , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 29, 2020 at 11:17:15PM +0200, Cristian Ciocaltea wrote: > Hi, > > This patchset brings a series of improvements for the Actions Semi S500 > SoCs family, by adding support for Clock & Reset Management Units, DMA, > MMC, I2C & SIRQ controllers. > > Please note the patches consist mostly of DTS and bindings/compatibles > changes, since all the work they depend on has been already merged, > i.e. clock fixes/additions, pinctrl driver, sirq driver. > > For the moment, I have only enabled the features I could test on > RoseapplePi SBC. > Applied all patches except the 2 dmaengine patches for v5.12. Andreas, please let me know if you want to do the PR this time. Else I'll proceed. Thanks, Mani > Thanks, > Cristi > > Changes in v3: > - Squashed 'arm: dts: owl-s500-roseapplepi: Use UART clock from CMU' with > 'arm: dts: owl-s500: Set CMU clocks for UARTs', according to Mani's review > - Rebased series on v5.11-rc1 and dropped the already merged patches: > * dt-bindings: mmc: owl: Add compatible string for Actions Semi S500 SoC > * dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema > * MAINTAINERS: Update entry for Actions Semi Owl I2C binding > * i2c: owl: Add compatible for the Actions Semi S500 I2C controller > > Changes in v2: > - Added new bindings/compatibles for S500 DMA, MMC & I2C controllers > - Added support for the SIRQ controller > - Added new entries in MAINTAINERS > - Updated naming of some patches in v1 > > Cristian Ciocaltea (13): > arm: dts: owl-s500: Add Clock Management Unit > arm: dts: owl-s500: Set CMU clocks for UARTs > arm: dts: owl-s500: Add Reset controller > dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC > dmaengine: owl: Add compatible for the Actions Semi S500 DMA > controller > arm: dts: owl-s500: Add DMA controller > arm: dts: owl-s500: Add pinctrl & GPIO support > arm: dts: owl-s500: Add MMC support > arm: dts: owl-s500: Add I2C support > arm: dts: owl-s500: Add SIRQ controller > arm: dts: owl-s500-roseapplepi: Add uSD support > arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration > MAINTAINERS: Add linux-actions ML for Actions Semi Arch > > .../devicetree/bindings/dma/owl-dma.yaml | 7 +- > MAINTAINERS | 1 + > arch/arm/boot/dts/owl-s500-cubieboard6.dts | 7 - > .../arm/boot/dts/owl-s500-guitar-bb-rev-b.dts | 7 - > .../arm/boot/dts/owl-s500-labrador-base-m.dts | 7 - > arch/arm/boot/dts/owl-s500-roseapplepi.dts | 97 +++++++++++- > arch/arm/boot/dts/owl-s500-sparky.dts | 7 - > arch/arm/boot/dts/owl-s500.dtsi | 140 ++++++++++++++++++ > drivers/dma/owl-dma.c | 3 +- > 9 files changed, 239 insertions(+), 37 deletions(-) > > -- > 2.30.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel