From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35F18C433DB for ; Tue, 5 Jan 2021 13:06:49 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E720722AAC for ; Tue, 5 Jan 2021 13:06:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E720722AAC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=TL8GXcmd1Usm5c/98nbun76DvEuy0MqqN2PgmWg6l9k=; b=RZeusmyaJCvyum2Eo0BfI4I3E 2ffj/fE57CJGlxtr4NNNH1Z3MeACfJqn3+6KbDu3tmGulzmiPyDqIJ1OC7O8/4AJRMhvdeCb9oQFF ZD8me1g3jKp17mMbubJx3PZI3APnzbCPL3xVrInA5zpX4RRW3exU6ThKJcURuoPRrDKJUxi7tUJj/ SkqY2Y6gcNKS4pVzFrOYr5x4/OFiOGnatkZoZrDdu+dAAQCBV7NhEPHLzGoxj1jz+aux4+O/IAqk9 E3HV17x4tOiryQhfTWicbmANzuRc+qJ/DqFFMlSHSKwk29VWKGjbLSvT2w5T9//EJahaW7TTRVk9W 4Q8ktV28A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kwm1M-0001r8-Of; Tue, 05 Jan 2021 13:05:08 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kwm1J-0001qF-Jk for linux-arm-kernel@lists.infradead.org; Tue, 05 Jan 2021 13:05:06 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 1F3D622240; Tue, 5 Jan 2021 13:05:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1609851904; bh=ecAslWQ6B5/J70Zk/sQRf9wb8OWGumYxLhSFQeps2yg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=t5OUpmLL3CQBRciwQZ9jJ3AS//j7ilUb7E/S6WXwp2LSnjSCkf7eg6jM7XLsdGOGK LBDUNtCxXuVBHFTQjFnHuAGUOV5owEThc/ZWhneOCZ4h0f/44KYiFbkDvkevZbVdSa B1dmHuSClf8v5hKnbiqH98wvuWVoxEP3I8MpWxh35VdFqPAmi+ijwOZ7BoxlSy19tW cdEzSuPEnBAX2MG3ShZ1fBpdwzE2OJhLMGlQyJMmBQQuKN1UIEiiJV76UyCJl0p+wL Wg+Awld/73fYQxHcNxQeOTt/GfPV9HjExvnGTll84c4fGN0SN04KqOfWTjzpJ2anqV uF1f4RruQLrRQ== Date: Tue, 5 Jan 2021 13:04:58 +0000 From: Will Deacon To: Alex Deucher Subject: Re: [PATCH] drm/amd/display: Revert "add DCN support for aarch64" Message-ID: <20210105130458.GA11108@willie-the-truck> References: <20201214175225.38975-1-ardb@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210105_080505_806585_5F15E846 X-CRM114-Status: GOOD ( 32.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leo Li , Catalin Marinas , amd-gfx list , Christian =?iso-8859-1?Q?K=F6nig?= , David Airlie , Maling list - DRI developers , Daniel Vetter , Daniel Kolesa , Alex Deucher , Ard Biesheuvel , linux-arm-kernel , Dave Martin Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jan 04, 2021 at 11:27:24AM -0500, Alex Deucher wrote: > On Tue, Dec 29, 2020 at 8:17 AM Ard Biesheuvel wrote: > > > > On Wed, 16 Dec 2020 at 23:26, Ard Biesheuvel wrote: > > > > > > On Wed, 16 Dec 2020 at 19:00, Alex Deucher wr= ote: > > > > > > > > On Mon, Dec 14, 2020 at 12:53 PM Ard Biesheuvel w= rote: > > > > > > > > > > This reverts commit c38d444e44badc557cf29fdfdfb823604890ccfa. > > > > > > > > > > Simply disabling -mgeneral-regs-only left and right is risky, giv= en that > > > > > the standard AArch64 ABI permits the use of FP/SIMD registers any= where, > > > > > and GCC is known to use SIMD registers for spilling, and may inve= nt > > > > > other uses of the FP/SIMD register file that have nothing to do w= ith the > > > > > floating point code in question. Note that putting kernel_neon_be= gin() > > > > > and kernel_neon_end() around the code that does use FP is not suf= ficient > > > > > here, the problem is in all the other code that may be emitted wi= th > > > > > references to SIMD registers in it. > > > > > > > > > > So the only way to do this properly is to put all floating point = code in > > > > > a separate compilation unit, and only compile that unit with > > > > > -mgeneral-regs-only. But perhaps the use of floating point here is > > > > > something that should be reconsidered entirely. > > > > > > > > > > Cc: Catalin Marinas > > > > > Cc: Will Deacon > > > > > Cc: Dave Martin > > > > > Cc: Rob Herring > > > > > Cc: Leo Li > > > > > Cc: Alex Deucher > > > > > Cc: "Christian K=F6nig" > > > > > Cc: David Airlie > > > > > Cc: Daniel Vetter > > > > > Cc: Daniel Kolesa > > > > > Cc: amd-gfx@lists.freedesktop.org > > > > > Cc: dri-devel@lists.freedesktop.org > > > > > Signed-off-by: Ard Biesheuvel > > > > > > > > Can rebase this on Linus' master branch? There were a number of new > > > > asics added which copy pasted the ARM64 support. > > > > > > > > > > Not sure what you are asking me here. Reverting commit c38d444e44badc5 > > > on top of mainline is not going to fix the other code that was added. > > > Or are you asking me to go and find the patches (how many?) that added > > > new ASICs and fix them for arm64? > > > > > > Note that this code is critically broken, as it may corrupt user > > > process state arbitrarily. So if new code was added that contains the > > > same bug, it should be reverted so that the respective authors can fix > > > it and resubmit. > > > > > > > Is this simply about dropping the newly added references to > > $(dml_rcflags) from the Makefile? Because that is quite trivial ... > = > Yes, I was thinking something like the attached patch. > = > Alex > From fbc93ca7d7739861ce63f6b483cf23d7cf1d69fb Mon Sep 17 00:00:00 2001 > From: Alex Deucher > Date: Mon, 4 Jan 2021 11:24:20 -0500 > Subject: [PATCH] drm/amdgpu/display: drop DCN support for aarch64 > = > From Ard: > = > "Simply disabling -mgeneral-regs-only left and right is risky, given that > the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, > and GCC is known to use SIMD registers for spilling, and may invent > other uses of the FP/SIMD register file that have nothing to do with the > floating point code in question. Note that putting kernel_neon_begin() > and kernel_neon_end() around the code that does use FP is not sufficient > here, the problem is in all the other code that may be emitted with > references to SIMD registers in it. > = > So the only way to do this properly is to put all floating point code in > a separate compilation unit, and only compile that unit with > -mgeneral-regs-only." > = > Disable support until the code can be properly refactored to support this > properly on aarch64. > = > Reported-by: Ard Biesheuvel > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/display/Kconfig | 2 +- > drivers/gpu/drm/amd/display/dc/calcs/Makefile | 4 ---- > .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 21 ------------------- > drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 7 ------- > .../drm/amd/display/dc/dcn10/dcn10_resource.c | 7 ------- > drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 5 ----- > .../gpu/drm/amd/display/dc/dcn301/Makefile | 4 ---- > .../gpu/drm/amd/display/dc/dcn302/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dsc/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/os_types.h | 4 ---- > 13 files changed, 1 insertion(+), 73 deletions(-) Acked-by: Will Deacon Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A008FC433E0 for ; Tue, 5 Jan 2021 13:05:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6036B22AAC for ; Tue, 5 Jan 2021 13:05:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6036B22AAC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 28D4F89AB6; Tue, 5 Jan 2021 13:05:06 +0000 (UTC) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id 93E0489AB3; Tue, 5 Jan 2021 13:05:04 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 1F3D622240; Tue, 5 Jan 2021 13:05:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1609851904; bh=ecAslWQ6B5/J70Zk/sQRf9wb8OWGumYxLhSFQeps2yg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=t5OUpmLL3CQBRciwQZ9jJ3AS//j7ilUb7E/S6WXwp2LSnjSCkf7eg6jM7XLsdGOGK LBDUNtCxXuVBHFTQjFnHuAGUOV5owEThc/ZWhneOCZ4h0f/44KYiFbkDvkevZbVdSa B1dmHuSClf8v5hKnbiqH98wvuWVoxEP3I8MpWxh35VdFqPAmi+ijwOZ7BoxlSy19tW cdEzSuPEnBAX2MG3ShZ1fBpdwzE2OJhLMGlQyJMmBQQuKN1UIEiiJV76UyCJl0p+wL Wg+Awld/73fYQxHcNxQeOTt/GfPV9HjExvnGTll84c4fGN0SN04KqOfWTjzpJ2anqV uF1f4RruQLrRQ== Date: Tue, 5 Jan 2021 13:04:58 +0000 From: Will Deacon To: Alex Deucher Subject: Re: [PATCH] drm/amd/display: Revert "add DCN support for aarch64" Message-ID: <20210105130458.GA11108@willie-the-truck> References: <20201214175225.38975-1-ardb@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leo Li , Catalin Marinas , amd-gfx list , Christian =?iso-8859-1?Q?K=F6nig?= , David Airlie , Maling list - DRI developers , Daniel Kolesa , Alex Deucher , Ard Biesheuvel , linux-arm-kernel , Dave Martin Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, Jan 04, 2021 at 11:27:24AM -0500, Alex Deucher wrote: > On Tue, Dec 29, 2020 at 8:17 AM Ard Biesheuvel wrote: > > > > On Wed, 16 Dec 2020 at 23:26, Ard Biesheuvel wrote: > > > > > > On Wed, 16 Dec 2020 at 19:00, Alex Deucher wr= ote: > > > > > > > > On Mon, Dec 14, 2020 at 12:53 PM Ard Biesheuvel w= rote: > > > > > > > > > > This reverts commit c38d444e44badc557cf29fdfdfb823604890ccfa. > > > > > > > > > > Simply disabling -mgeneral-regs-only left and right is risky, giv= en that > > > > > the standard AArch64 ABI permits the use of FP/SIMD registers any= where, > > > > > and GCC is known to use SIMD registers for spilling, and may inve= nt > > > > > other uses of the FP/SIMD register file that have nothing to do w= ith the > > > > > floating point code in question. Note that putting kernel_neon_be= gin() > > > > > and kernel_neon_end() around the code that does use FP is not suf= ficient > > > > > here, the problem is in all the other code that may be emitted wi= th > > > > > references to SIMD registers in it. > > > > > > > > > > So the only way to do this properly is to put all floating point = code in > > > > > a separate compilation unit, and only compile that unit with > > > > > -mgeneral-regs-only. But perhaps the use of floating point here is > > > > > something that should be reconsidered entirely. > > > > > > > > > > Cc: Catalin Marinas > > > > > Cc: Will Deacon > > > > > Cc: Dave Martin > > > > > Cc: Rob Herring > > > > > Cc: Leo Li > > > > > Cc: Alex Deucher > > > > > Cc: "Christian K=F6nig" > > > > > Cc: David Airlie > > > > > Cc: Daniel Vetter > > > > > Cc: Daniel Kolesa > > > > > Cc: amd-gfx@lists.freedesktop.org > > > > > Cc: dri-devel@lists.freedesktop.org > > > > > Signed-off-by: Ard Biesheuvel > > > > > > > > Can rebase this on Linus' master branch? There were a number of new > > > > asics added which copy pasted the ARM64 support. > > > > > > > > > > Not sure what you are asking me here. Reverting commit c38d444e44badc5 > > > on top of mainline is not going to fix the other code that was added. > > > Or are you asking me to go and find the patches (how many?) that added > > > new ASICs and fix them for arm64? > > > > > > Note that this code is critically broken, as it may corrupt user > > > process state arbitrarily. So if new code was added that contains the > > > same bug, it should be reverted so that the respective authors can fix > > > it and resubmit. > > > > > > > Is this simply about dropping the newly added references to > > $(dml_rcflags) from the Makefile? Because that is quite trivial ... > = > Yes, I was thinking something like the attached patch. > = > Alex > From fbc93ca7d7739861ce63f6b483cf23d7cf1d69fb Mon Sep 17 00:00:00 2001 > From: Alex Deucher > Date: Mon, 4 Jan 2021 11:24:20 -0500 > Subject: [PATCH] drm/amdgpu/display: drop DCN support for aarch64 > = > From Ard: > = > "Simply disabling -mgeneral-regs-only left and right is risky, given that > the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, > and GCC is known to use SIMD registers for spilling, and may invent > other uses of the FP/SIMD register file that have nothing to do with the > floating point code in question. Note that putting kernel_neon_begin() > and kernel_neon_end() around the code that does use FP is not sufficient > here, the problem is in all the other code that may be emitted with > references to SIMD registers in it. > = > So the only way to do this properly is to put all floating point code in > a separate compilation unit, and only compile that unit with > -mgeneral-regs-only." > = > Disable support until the code can be properly refactored to support this > properly on aarch64. > = > Reported-by: Ard Biesheuvel > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/display/Kconfig | 2 +- > drivers/gpu/drm/amd/display/dc/calcs/Makefile | 4 ---- > .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 21 ------------------- > drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 7 ------- > .../drm/amd/display/dc/dcn10/dcn10_resource.c | 7 ------- > drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 5 ----- > .../gpu/drm/amd/display/dc/dcn301/Makefile | 4 ---- > .../gpu/drm/amd/display/dc/dcn302/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dsc/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/os_types.h | 4 ---- > 13 files changed, 1 insertion(+), 73 deletions(-) Acked-by: Will Deacon Will _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61ABCC433E6 for ; Tue, 5 Jan 2021 13:05:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 27EB322AAC for ; Tue, 5 Jan 2021 13:05:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 27EB322AAC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=amd-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE5B589AB3; Tue, 5 Jan 2021 13:05:05 +0000 (UTC) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id 93E0489AB3; Tue, 5 Jan 2021 13:05:04 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 1F3D622240; Tue, 5 Jan 2021 13:05:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1609851904; bh=ecAslWQ6B5/J70Zk/sQRf9wb8OWGumYxLhSFQeps2yg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=t5OUpmLL3CQBRciwQZ9jJ3AS//j7ilUb7E/S6WXwp2LSnjSCkf7eg6jM7XLsdGOGK LBDUNtCxXuVBHFTQjFnHuAGUOV5owEThc/ZWhneOCZ4h0f/44KYiFbkDvkevZbVdSa B1dmHuSClf8v5hKnbiqH98wvuWVoxEP3I8MpWxh35VdFqPAmi+ijwOZ7BoxlSy19tW cdEzSuPEnBAX2MG3ShZ1fBpdwzE2OJhLMGlQyJMmBQQuKN1UIEiiJV76UyCJl0p+wL Wg+Awld/73fYQxHcNxQeOTt/GfPV9HjExvnGTll84c4fGN0SN04KqOfWTjzpJ2anqV uF1f4RruQLrRQ== Date: Tue, 5 Jan 2021 13:04:58 +0000 From: Will Deacon To: Alex Deucher Subject: Re: [PATCH] drm/amd/display: Revert "add DCN support for aarch64" Message-ID: <20210105130458.GA11108@willie-the-truck> References: <20201214175225.38975-1-ardb@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Leo Li , Catalin Marinas , amd-gfx list , Christian =?iso-8859-1?Q?K=F6nig?= , David Airlie , Maling list - DRI developers , Daniel Vetter , Daniel Kolesa , Alex Deucher , Ard Biesheuvel , linux-arm-kernel , Dave Martin Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Mon, Jan 04, 2021 at 11:27:24AM -0500, Alex Deucher wrote: > On Tue, Dec 29, 2020 at 8:17 AM Ard Biesheuvel wrote: > > > > On Wed, 16 Dec 2020 at 23:26, Ard Biesheuvel wrote: > > > > > > On Wed, 16 Dec 2020 at 19:00, Alex Deucher wr= ote: > > > > > > > > On Mon, Dec 14, 2020 at 12:53 PM Ard Biesheuvel w= rote: > > > > > > > > > > This reverts commit c38d444e44badc557cf29fdfdfb823604890ccfa. > > > > > > > > > > Simply disabling -mgeneral-regs-only left and right is risky, giv= en that > > > > > the standard AArch64 ABI permits the use of FP/SIMD registers any= where, > > > > > and GCC is known to use SIMD registers for spilling, and may inve= nt > > > > > other uses of the FP/SIMD register file that have nothing to do w= ith the > > > > > floating point code in question. Note that putting kernel_neon_be= gin() > > > > > and kernel_neon_end() around the code that does use FP is not suf= ficient > > > > > here, the problem is in all the other code that may be emitted wi= th > > > > > references to SIMD registers in it. > > > > > > > > > > So the only way to do this properly is to put all floating point = code in > > > > > a separate compilation unit, and only compile that unit with > > > > > -mgeneral-regs-only. But perhaps the use of floating point here is > > > > > something that should be reconsidered entirely. > > > > > > > > > > Cc: Catalin Marinas > > > > > Cc: Will Deacon > > > > > Cc: Dave Martin > > > > > Cc: Rob Herring > > > > > Cc: Leo Li > > > > > Cc: Alex Deucher > > > > > Cc: "Christian K=F6nig" > > > > > Cc: David Airlie > > > > > Cc: Daniel Vetter > > > > > Cc: Daniel Kolesa > > > > > Cc: amd-gfx@lists.freedesktop.org > > > > > Cc: dri-devel@lists.freedesktop.org > > > > > Signed-off-by: Ard Biesheuvel > > > > > > > > Can rebase this on Linus' master branch? There were a number of new > > > > asics added which copy pasted the ARM64 support. > > > > > > > > > > Not sure what you are asking me here. Reverting commit c38d444e44badc5 > > > on top of mainline is not going to fix the other code that was added. > > > Or are you asking me to go and find the patches (how many?) that added > > > new ASICs and fix them for arm64? > > > > > > Note that this code is critically broken, as it may corrupt user > > > process state arbitrarily. So if new code was added that contains the > > > same bug, it should be reverted so that the respective authors can fix > > > it and resubmit. > > > > > > > Is this simply about dropping the newly added references to > > $(dml_rcflags) from the Makefile? Because that is quite trivial ... > = > Yes, I was thinking something like the attached patch. > = > Alex > From fbc93ca7d7739861ce63f6b483cf23d7cf1d69fb Mon Sep 17 00:00:00 2001 > From: Alex Deucher > Date: Mon, 4 Jan 2021 11:24:20 -0500 > Subject: [PATCH] drm/amdgpu/display: drop DCN support for aarch64 > = > From Ard: > = > "Simply disabling -mgeneral-regs-only left and right is risky, given that > the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, > and GCC is known to use SIMD registers for spilling, and may invent > other uses of the FP/SIMD register file that have nothing to do with the > floating point code in question. Note that putting kernel_neon_begin() > and kernel_neon_end() around the code that does use FP is not sufficient > here, the problem is in all the other code that may be emitted with > references to SIMD registers in it. > = > So the only way to do this properly is to put all floating point code in > a separate compilation unit, and only compile that unit with > -mgeneral-regs-only." > = > Disable support until the code can be properly refactored to support this > properly on aarch64. > = > Reported-by: Ard Biesheuvel > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/display/Kconfig | 2 +- > drivers/gpu/drm/amd/display/dc/calcs/Makefile | 4 ---- > .../gpu/drm/amd/display/dc/clk_mgr/Makefile | 21 ------------------- > drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 7 ------- > .../drm/amd/display/dc/dcn10/dcn10_resource.c | 7 ------- > drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dcn30/Makefile | 5 ----- > .../gpu/drm/amd/display/dc/dcn301/Makefile | 4 ---- > .../gpu/drm/amd/display/dc/dcn302/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/dsc/Makefile | 4 ---- > drivers/gpu/drm/amd/display/dc/os_types.h | 4 ---- > 13 files changed, 1 insertion(+), 73 deletions(-) Acked-by: Will Deacon Will _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx