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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v5 33/43] tcg/s390: Support split-wx code generation
Date: Tue,  5 Jan 2021 07:19:40 -1000	[thread overview]
Message-ID: <20210105171950.415486-34-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210105171950.415486-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390/tcg-target.h     |  2 +-
 tcg/s390/tcg-target.c.inc | 69 +++++++++++++++++----------------------
 2 files changed, 31 insertions(+), 40 deletions(-)

diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index b8f4296e4b..4edcb06044 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -159,6 +159,6 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
 #define TCG_TARGET_NEED_LDST_LABELS
 #endif
 #define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_SUPPORT_MIRROR       0
+#define TCG_TARGET_SUPPORT_MIRROR       1
 
 #endif
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index e4c61fc014..582a8ef941 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -363,36 +363,37 @@ static void * const qemu_st_helpers[16] = {
 };
 #endif
 
-static tcg_insn_unit *tb_ret_addr;
+static const tcg_insn_unit *tb_ret_addr;
 uint64_t s390_facilities;
 
-static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+static bool patch_reloc(tcg_insn_unit *src_rw, int type,
                         intptr_t value, intptr_t addend)
 {
+    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
     intptr_t pcrel2;
     uint32_t old;
 
     value += addend;
-    pcrel2 = (tcg_insn_unit *)value - code_ptr;
+    pcrel2 = (tcg_insn_unit *)value - src_rx;
 
     switch (type) {
     case R_390_PC16DBL:
         if (pcrel2 == (int16_t)pcrel2) {
-            tcg_patch16(code_ptr, pcrel2);
+            tcg_patch16(src_rw, pcrel2);
             return true;
         }
         break;
     case R_390_PC32DBL:
         if (pcrel2 == (int32_t)pcrel2) {
-            tcg_patch32(code_ptr, pcrel2);
+            tcg_patch32(src_rw, pcrel2);
             return true;
         }
         break;
     case R_390_20:
         if (value == sextract64(value, 0, 20)) {
-            old = *(uint32_t *)code_ptr & 0xf00000ff;
+            old = *(uint32_t *)src_rw & 0xf00000ff;
             old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4);
-            tcg_patch32(code_ptr, old);
+            tcg_patch32(src_rw, old);
             return true;
         }
         break;
@@ -730,7 +731,8 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
 }
 
 /* load data from an absolute host address */
-static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs)
+static void tcg_out_ld_abs(TCGContext *s, TCGType type,
+                           TCGReg dest, const void *abs)
 {
     intptr_t addr = (intptr_t)abs;
 
@@ -1304,7 +1306,7 @@ static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
 
 static void tgen_gotoi(TCGContext *s, int cc, const tcg_insn_unit *dest)
 {
-    ptrdiff_t off = dest - s->code_ptr;
+    ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1;
     if (off == (int16_t)off) {
         tcg_out_insn(s, RI, BRC, cc, off);
     } else if (off == (int32_t)off) {
@@ -1333,34 +1335,18 @@ static void tgen_branch(TCGContext *s, int cc, TCGLabel *l)
 static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc,
                                 TCGReg r1, TCGReg r2, TCGLabel *l)
 {
-    intptr_t off = 0;
-
-    if (l->has_value) {
-        off = l->u.value_ptr - s->code_ptr;
-        tcg_debug_assert(off == (int16_t)off);
-    } else {
-        tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
-    }
-
+    tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
     tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2);
-    tcg_out16(s, off);
+    tcg_out16(s, 0);
     tcg_out16(s, cc << 12 | (opc & 0xff));
 }
 
 static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc,
                                     TCGReg r1, int i2, TCGLabel *l)
 {
-    tcg_target_long off = 0;
-
-    if (l->has_value) {
-        off = l->u.value_ptr - s->code_ptr;
-        tcg_debug_assert(off == (int16_t)off);
-    } else {
-        tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
-    }
-
+    tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
     tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc);
-    tcg_out16(s, off);
+    tcg_out16(s, 0);
     tcg_out16(s, (i2 << 8) | (opc & 0xff));
 }
 
@@ -1417,7 +1403,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
 
 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest)
 {
-    ptrdiff_t off = dest - s->code_ptr;
+    ptrdiff_t off = tcg_pcrel_diff(s, dest) >> 1;
     if (off == (int32_t)off) {
         tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off);
     } else {
@@ -1601,7 +1587,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
     label->oi = oi;
     label->datalo_reg = data;
     label->addrlo_reg = addr;
-    label->raddr = raddr;
+    /* TODO: Cast goes away when all hosts converted */
+    label->raddr = (void *)tcg_splitwx_to_rx(raddr);
     label->label_ptr[0] = label_ptr;
 }
 
@@ -1613,7 +1600,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
     MemOp opc = get_memop(oi);
 
     if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
-                     (intptr_t)s->code_ptr, 2)) {
+                     (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) {
         return false;
     }
 
@@ -1638,7 +1625,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
     MemOp opc = get_memop(oi);
 
     if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
-                     (intptr_t)s->code_ptr, 2)) {
+                     (intptr_t)tcg_splitwx_to_rx(s->code_ptr), 2)) {
         return false;
     }
 
@@ -1766,7 +1753,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_goto_tb:
         a0 = args[0];
         if (s->tb_jmp_insn_offset) {
-            /* branch displacement must be aligned for atomic patching;
+            /*
+             * branch displacement must be aligned for atomic patching;
              * see if we need to add extra nop before branch
              */
             if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) {
@@ -1779,7 +1767,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         } else {
             /* load address stored at s->tb_jmp_target_addr + a0 */
             tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB,
-                           s->tb_jmp_target_addr + a0);
+                           tcg_splitwx_to_rx(s->tb_jmp_target_addr + a0));
             /* and go there */
             tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB);
         }
@@ -1789,8 +1777,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
            TCG_REG_TB to the beginning of this TB.  */
         if (USE_REG_TB) {
             int ofs = -tcg_current_code_size(s);
-            assert(ofs == (int16_t)ofs);
-            tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs);
+            /* All TB are restricted to 64KiB by unwind info. */
+            tcg_debug_assert(ofs == sextract64(ofs, 0, 20));
+            tcg_out_insn(s, RXY, LAY, TCG_REG_TB,
+                         TCG_REG_TB, TCG_REG_NONE, ofs);
         }
         break;
 
@@ -2561,11 +2551,12 @@ static void tcg_target_qemu_prologue(TCGContext *s)
      * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
      * and fall through to the rest of the epilogue.
      */
-    tcg_code_gen_epilogue = s->code_ptr;
+    /* TODO: Cast goes away when all hosts converted */
+    tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr);
     tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0);
 
     /* TB epilogue */
-    tb_ret_addr = s->code_ptr;
+    tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
 
     /* lmg %r6,%r15,fs+48(%r15) (restore registers) */
     tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15,
-- 
2.25.1



  parent reply	other threads:[~2021-01-05 17:48 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-05 17:19 [PATCH v5 00/43] Mirror map JIT memory for TCG Richard Henderson
2021-01-05 17:19 ` [PATCH v5 01/43] tcg: Do not flush icache for interpreter Richard Henderson
2021-01-05 17:19 ` [PATCH v5 02/43] util: Extract flush_icache_range to cacheflush.c Richard Henderson
2021-01-05 17:19 ` [PATCH v5 03/43] util: Enhance flush_icache_range with separate data pointer Richard Henderson
2021-01-05 17:19 ` [PATCH v5 04/43] util: Specialize flush_idcache_range for aarch64 Richard Henderson
2021-01-05 17:19 ` [PATCH v5 05/43] tcg: Move tcg prologue pointer out of TCGContext Richard Henderson
2021-01-05 17:19 ` [PATCH v5 06/43] tcg: Move tcg epilogue " Richard Henderson
2021-01-05 17:19 ` [PATCH v5 07/43] tcg: Add in_code_gen_buffer Richard Henderson
2021-01-05 17:19 ` [PATCH v5 08/43] tcg: Introduce tcg_splitwx_to_{rx,rw} Richard Henderson
2021-01-05 17:19 ` [PATCH v5 09/43] tcg: Adjust TCGLabel for const Richard Henderson
2021-01-05 17:19 ` [PATCH v5 10/43] tcg: Adjust tcg_out_call " Richard Henderson
2021-01-05 17:19 ` [PATCH v5 11/43] tcg: Adjust tcg_out_label " Richard Henderson
2021-01-05 17:19 ` [PATCH v5 12/43] tcg: Adjust tcg_register_jit " Richard Henderson
2021-01-05 17:19 ` [PATCH v5 13/43] tcg: Adjust tb_target_set_jmp_target for split-wx Richard Henderson
2021-01-05 17:19 ` [PATCH v5 14/43] tcg: Make DisasContextBase.tb const Richard Henderson
2021-01-05 17:19 ` [PATCH v5 15/43] tcg: Make tb arg to synchronize_from_tb const Richard Henderson
2021-01-05 17:19 ` [PATCH v5 16/43] tcg: Use Error with alloc_code_gen_buffer Richard Henderson
2021-01-05 18:55   ` Philippe Mathieu-Daudé
2021-01-05 17:19 ` [PATCH v5 17/43] tcg: Add --accel tcg,split-wx property Richard Henderson
2021-01-05 20:30   ` Joelle van Dyne
2021-01-05 17:19 ` [PATCH v5 18/43] accel/tcg: Support split-wx for linux with memfd Richard Henderson
2021-01-05 17:19 ` [PATCH v5 19/43] accel/tcg: Support split-wx for darwin/iOS with vm_remap Richard Henderson
2021-01-05 17:19 ` [PATCH v5 20/43] tcg: Return the TB pointer from the rx region from exit_tb Richard Henderson
2021-01-05 17:19 ` [PATCH v5 21/43] tcg/i386: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 22/43] tcg/aarch64: Use B not BL for tcg_out_goto_long Richard Henderson
2021-01-05 17:19 ` [PATCH v5 23/43] tcg/aarch64: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 24/43] disas: Push const down through host disassembly Richard Henderson
2021-01-05 17:19 ` [PATCH v5 25/43] tcg/tci: Push const down through bytecode reading Richard Henderson
2021-01-05 18:51   ` Philippe Mathieu-Daudé
2021-01-05 17:19 ` [PATCH v5 26/43] tcg: Introduce tcg_tbrel_diff Richard Henderson
2021-01-05 17:19 ` [PATCH v5 27/43] tcg/ppc: Use tcg_tbrel_diff Richard Henderson
2021-01-05 17:19 ` [PATCH v5 28/43] tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TB Richard Henderson
2021-01-05 17:19 ` [PATCH v5 29/43] tcg/ppc: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 30/43] tcg/sparc: Use tcg_tbrel_diff Richard Henderson
2021-01-05 17:19 ` [PATCH v5 31/43] tcg/sparc: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 32/43] tcg/s390: Use tcg_tbrel_diff Richard Henderson
2021-01-05 17:19 ` Richard Henderson [this message]
2021-01-05 17:19 ` [PATCH v5 34/43] tcg/riscv: Fix branch range checks Richard Henderson
2021-01-05 17:19 ` [PATCH v5 35/43] tcg/riscv: Remove branch-over-branch fallback Richard Henderson
2021-01-05 17:19 ` [PATCH v5 36/43] tcg/riscv: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 37/43] accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfd Richard Henderson
2021-01-05 17:19 ` [PATCH v5 38/43] tcg/mips: Do not assert on relocation overflow Richard Henderson
2021-01-05 17:19 ` [PATCH v5 39/43] tcg/mips: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 40/43] tcg/arm: " Richard Henderson
2021-01-05 17:19 ` [PATCH v5 41/43] tcg: Remove TCG_TARGET_SUPPORT_MIRROR Richard Henderson
2021-01-05 17:19 ` [PATCH v5 42/43] tcg: Constify tcg_code_gen_epilogue Richard Henderson
2021-01-05 18:47   ` Philippe Mathieu-Daudé
2021-01-05 17:19 ` [PATCH v5 43/43] tcg: Constify TCGLabelQemuLdst.raddr Richard Henderson
2021-01-05 18:47   ` Philippe Mathieu-Daudé
2021-01-05 18:12 ` [PATCH v5 00/43] Mirror map JIT memory for TCG no-reply

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