Re: [PATCH mlx5-next 1/4] PCI: Configure number of MSI-X vectors for SR-IOV VFs

[Leon Romanovsky <leon@kernel.org>]

On Thu, Jan 07, 2021 at 10:54:38PM -0500, Don Dutile wrote:
> On 1/7/21 7:57 PM, Bjorn Helgaas wrote:
> > [+cc Alex, Don]

<...>

> > Help me connect the dots here.  Is this required because of something
> > peculiar to mlx5, or is something like this required for all SR-IOV
> > devices because of the way the PCIe spec is written?
> So, overall, I'm guessing the mlx5 device can have 1000's of MSIX -- say, one per send/receive/completion queue.
> This device capability may exceed the max number MSIX a VM can have/support (depending on guestos).
> So, a sysfs tunable is used to set the max MSIX available, and thus, the device puts >1 send/rcv/completion queue intr on a given MSIX.
>
> ok, time for Leon to better state what this patch does,
> and why it's needed on mlx5 (and may be applicable to other/future high-MSIX devices assigned to VMs (NVME?)).
> Hmmm, now that I said it, why is it SRIOV-centric and not pci-device centric (can pass a PF w/high number of MSIX to a VM).

Thanks Don and Bjorn,

I will answer on all comments a little bit later when I will return
to the office (Sunday).

However it is important for me to present the use case.

Our mlx5 SR-IOV devices were always capable to drive many MSI-X (upto 2K,
don't catch me on exact number), however when user created VFs, the FW has
no knowledge of how those VFs will be used. So FW had no choice but statically
and equally assign same amount of MSI-X to all VFs.

After SR-IOV VF creation, user will bind those new VFs to the VMs, but
the VMs have different number of CPUs and despite HW being able to deliver
all needed number of vectors (in mlx5 netdev world, number of channels == number
of CPUs == number of vectors), we will be limited by already set low number
of vectors.

So it is not for vector reduction, but more for vector re-partition.

As an example, imagine mlx5 with two VFs. One VF is bounded to VM with 200 CPUs
and another is bounded to VM with 1 CPU. They need different amount of MSI-X vectors.

Hope that I succeeded to explain :).

Regarding why it is SR-IOV and not PCI, the amount of MSI-X vectors is
read-only field in the PCI, so we can't write from pci/core toward
PF device and expect HW update it. It means that if we really need it,
we will need to do it after driver already loaded on that PF, so driver
will forward to HW and lspci will work correctly. This will require
reload of whole PCI device initialization sequence, because MSI-X table
size pre-calculated very early in the init flow.

Thanks

>
> -Don