[PATCH 0/7] implement the processor fine grain feature for vangogh

[PATCH 0/7] implement the processor fine grain feature for vangogh

[Huang Rui]

These series are to implement the processor fine grain feature which is similar
with the gfx fine grain on vangogh. Please take a look.

Thanks,
Ray

Huang Rui (7):
  drm/amd/pm: remove vcn/jpeg powergating feature checking for vangogh
  drm/amd/pm: enhance the real response for smu message
  drm/amd/pm: clean up get_allowed_feature_mask function
  drm/amd/pm: initial feature_enabled/feature_support bitmap for vangogh
  drm/amd/pm: don't mark all apu as true on feature mask
  drm/amd/pm: implement the processor clocks which read by metric
  drm/amd/pm: implement processor fine grain feature for vangogh

 .../gpu/drm/amd/include/kgd_pp_interface.h    |   2 +
 drivers/gpu/drm/amd/pm/amdgpu_pm.c            |  28 +++
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h       |   8 +
 drivers/gpu/drm/amd/pm/inc/smu_types.h        |   1 +
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     |  14 ++
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 190 +++++++++++-------
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c        |   8 +-
 7 files changed, 181 insertions(+), 70 deletions(-)

-- 
2.25.1

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[PATCH 1/7] drm/amd/pm: remove vcn/jpeg powergating feature checking for vangogh

[Huang Rui]

VCN/JPEG PG won't be a feature mask bit which exposed by vangogh smu
firmware. So remove it.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 32 +++++++------------
 1 file changed, 12 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index d0417eb93d05..fc091091eaed 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -330,17 +330,13 @@ static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 
 	if (enable) {
 		/* vcn dpm on is a prerequisite for vcn power gate messages */
-		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
-			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
-			if (ret)
-				return ret;
-		}
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
+		if (ret)
+			return ret;
 	} else {
-		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
-			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
-			if (ret)
-				return ret;
-		}
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
+		if (ret)
+			return ret;
 	}
 
 	return ret;
@@ -351,17 +347,13 @@ static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 	int ret = 0;
 
 	if (enable) {
-		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
-			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
-			if (ret)
-				return ret;
-		}
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
+		if (ret)
+			return ret;
 	} else {
-		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
-			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
-			if (ret)
-				return ret;
-		}
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
+		if (ret)
+			return ret;
 	}
 
 	return ret;
-- 
2.25.1

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[PATCH 2/7] drm/amd/pm: enhance the real response for smu message

[Huang Rui]

The user prefers to know the real response value from C2PMSG 90 register
which is written by firmware not -EIO.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index f8260769061c..42b125701436 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -111,6 +111,7 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
 {
 	struct amdgpu_device *adev = smu->adev;
 	int ret = 0, index = 0;
+	int response;
 
 	if (smu->adev->in_pci_err_recovery)
 		return 0;
@@ -137,8 +138,9 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
 
 	ret = smu_cmn_wait_for_response(smu);
 	if (ret) {
+		response = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90);
 		dev_err(adev->dev, "failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
-		       smu_get_message_name(smu, msg), index, param, ret);
+		       smu_get_message_name(smu, msg), index, param, response);
 		goto out;
 	}
 
-- 
2.25.1

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[PATCH 3/7] drm/amd/pm: clean up get_allowed_feature_mask function

[Huang Rui]

The get_allowed_feature_mask is superfluous on vangogh.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 43 -------------------
 1 file changed, 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index fc091091eaed..3687cd1dc24f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -359,48 +359,6 @@ static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 	return ret;
 }
 
-static int vangogh_get_allowed_feature_mask(struct smu_context *smu,
-					    uint32_t *feature_mask,
-					    uint32_t num)
-{
-	struct amdgpu_device *adev = smu->adev;
-
-	if (num > 2)
-		return -EINVAL;
-
-	memset(feature_mask, 0, sizeof(uint32_t) * num);
-
-	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DPM_BIT)
-				| FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)
-				| FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)
-				| FEATURE_MASK(FEATURE_VCN_DPM_BIT)
-				| FEATURE_MASK(FEATURE_FCLK_DPM_BIT)
-				| FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)
-				| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
-				| FEATURE_MASK(FEATURE_PPT_BIT)
-				| FEATURE_MASK(FEATURE_TDC_BIT)
-				| FEATURE_MASK(FEATURE_FAN_CONTROLLER_BIT)
-				| FEATURE_MASK(FEATURE_DS_LCLK_BIT)
-				| FEATURE_MASK(FEATURE_DS_DCFCLK_BIT);
-
-	if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
-		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT);
-
-	if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
-		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT);
-
-	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
-		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FCLK_DPM_BIT);
-
-	if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
-		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DPM_BIT);
-
-	if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
-		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
-
-	return 0;
-}
-
 static bool vangogh_is_dpm_running(struct smu_context *smu)
 {
 	int ret = 0;
@@ -1464,7 +1422,6 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
 	.init_power = smu_v11_0_init_power,
 	.fini_power = smu_v11_0_fini_power,
 	.register_irq_handler = smu_v11_0_register_irq_handler,
-	.get_allowed_feature_mask = vangogh_get_allowed_feature_mask,
 	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
 	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
 	.send_smc_msg = smu_cmn_send_smc_msg,
-- 
2.25.1

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[PATCH 4/7] drm/amd/pm: initial feature_enabled/feature_support bitmap for vangogh

[Huang Rui]

VanGogh supports feature mask checking which exposed by smu firmware. It
has to initial at first, otherwise, all SMU_FEATURE_xxx masks are
invalid.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 26 ++++++++++++++++---
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 3687cd1dc24f..233c6e4ddd01 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -1373,12 +1373,30 @@ static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clock
 static int vangogh_system_features_control(struct smu_context *smu, bool en)
 {
 	struct amdgpu_device *adev = smu->adev;
+	struct smu_feature *feature = &smu->smu_feature;
+	uint32_t feature_mask[2];
+	int ret = 0;
 
 	if (adev->pm.fw_version >= 0x43f1700)
-		return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
-						en ? RLC_STATUS_NORMAL : RLC_STATUS_OFF, NULL);
-	else
-		return 0;
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
+						      en ? RLC_STATUS_NORMAL : RLC_STATUS_OFF, NULL);
+
+	bitmap_zero(feature->enabled, feature->feature_num);
+	bitmap_zero(feature->supported, feature->feature_num);
+
+	if (!en)
+		return ret;
+
+	ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+	if (ret)
+		return ret;
+
+	bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
+		    feature->feature_num);
+	bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
+		    feature->feature_num);
+
+	return 0;
 }
 
 static int vangogh_post_smu_init(struct smu_context *smu)
-- 
2.25.1

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[PATCH 5/7] drm/amd/pm: don't mark all apu as true on feature mask

[Huang Rui]

VHG based APU will support feature mask checking.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 42b125701436..540dd4ddf09b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -271,11 +271,13 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu,
 			       enum smu_feature_mask mask)
 {
 	struct smu_feature *feature = &smu->smu_feature;
+	struct amdgpu_device *adev = smu->adev;
 	int feature_id;
 	int ret = 0;
 
-	if (smu->is_apu)
+	if (smu->is_apu && adev->family < AMDGPU_FAMILY_VGH)
 		return 1;
+
 	feature_id = smu_cmn_to_asic_specific_index(smu,
 						    CMN2ASIC_MAPPING_FEATURE,
 						    mask);
-- 
2.25.1

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[PATCH 6/7] drm/amd/pm: implement the processor clocks which read by metric

[Huang Rui]

The core processor clocks will be stored in smu metric table, then we
add this runtime information into amdgpu_pm_info interface.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 .../gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
 drivers/gpu/drm/amd/pm/amdgpu_pm.c            | 25 +++++++++++++++++++
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h       |  2 ++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     | 14 +++++++++++
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 11 ++++++++
 5 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 270f8db5115a..57b24c4c205b 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -103,6 +103,7 @@ enum pp_clock_type {
 
 enum amd_pp_sensors {
 	AMDGPU_PP_SENSOR_GFX_SCLK = 0,
+	AMDGPU_PP_SENSOR_CPU_CLK,
 	AMDGPU_PP_SENSOR_VDDNB,
 	AMDGPU_PP_SENSOR_VDDGFX,
 	AMDGPU_PP_SENSOR_UVD_VCLK,
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 97c669dd4cac..a5be03aa384b 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -36,6 +36,7 @@
 #include <linux/hwmon-sysfs.h>
 #include <linux/nospec.h>
 #include <linux/pm_runtime.h>
+#include <asm/processor.h>
 #include "hwmgr.h"
 
 static const struct cg_flag_name clocks[] = {
@@ -3621,6 +3622,27 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
  */
 #if defined(CONFIG_DEBUG_FS)
 
+static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
+					   struct amdgpu_device *adev) {
+	uint16_t *p_val;
+	uint32_t size;
+	int i;
+
+	if (is_support_cclk_dpm(adev)) {
+		p_val = kcalloc(boot_cpu_data.x86_max_cores, sizeof(uint16_t),
+				GFP_KERNEL);
+
+		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
+					    (void *)p_val, &size)) {
+			for (i = 0; i < boot_cpu_data.x86_max_cores; i++)
+				seq_printf(m, "\t%u MHz (CPU%d)\n",
+					   *(p_val + i), i);
+		}
+
+		kfree(p_val);
+	}
+}
+
 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
 {
 	uint32_t value;
@@ -3631,6 +3653,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
 	/* GPU Clocks */
 	size = sizeof(value);
 	seq_printf(m, "GFX Clocks and Power:\n");
+
+	amdgpu_debugfs_prints_cpu_info(m, adev);
+
 	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
 		seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
 	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index a9622b5e9c7b..97d788451624 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1122,6 +1122,7 @@ typedef enum {
 	METRICS_CURR_DCLK1,
 	METRICS_CURR_FCLK,
 	METRICS_CURR_DCEFCLK,
+	METRICS_AVERAGE_CPUCLK,
 	METRICS_AVERAGE_GFXCLK,
 	METRICS_AVERAGE_SOCCLK,
 	METRICS_AVERAGE_FCLK,
@@ -1250,6 +1251,7 @@ extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
 
 bool is_support_sw_smu(struct amdgpu_device *adev);
+bool is_support_cclk_dpm(struct amdgpu_device *adev);
 int smu_reset(struct smu_context *smu);
 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index d80f7f8efdcd..22868ad87628 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -288,6 +288,20 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
 	return false;
 }
 
+bool is_support_cclk_dpm(struct amdgpu_device *adev)
+{
+	struct smu_context *smu = &adev->smu;
+
+	if (!is_support_sw_smu(adev))
+		return false;
+
+	if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
+		return false;
+
+	return true;
+}
+
+
 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 233c6e4ddd01..63be82386964 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -34,6 +34,7 @@
 #include "soc15_common.h"
 #include "asic_reg/gc/gc_10_3_0_offset.h"
 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
+#include <asm/processor.h>
 
 /*
  * DO NOT use these for err/warn/info/debug messages.
@@ -285,6 +286,10 @@ static int vangogh_get_smu_metrics_data(struct smu_context *smu,
 	case METRICS_VOLTAGE_VDDSOC:
 		*value = metrics->Voltage[1];
 		break;
+	case METRICS_AVERAGE_CPUCLK:
+		memcpy(value, &metrics->CoreFrequency[0],
+		       boot_cpu_data.x86_max_cores * sizeof(uint16_t));
+		break;
 	default:
 		*value = UINT_MAX;
 		break;
@@ -1113,6 +1118,12 @@ static int vangogh_read_sensor(struct smu_context *smu,
 						   (uint32_t *)data);
 		*size = 4;
 		break;
+	case AMDGPU_PP_SENSOR_CPU_CLK:
+		ret = vangogh_get_smu_metrics_data(smu,
+						   METRICS_AVERAGE_CPUCLK,
+						   (uint32_t *)data);
+		*size = boot_cpu_data.x86_max_cores * sizeof(uint16_t);
+		break;
 	default:
 		ret = -EOPNOTSUPP;
 		break;
-- 
2.25.1

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[PATCH 7/7] drm/amd/pm: implement processor fine grain feature for vangogh

[Huang Rui]

This patch is to implement the processor fine grain feature for vangogh.
It's similar with gfx clock, the only difference is below:

echo "p core_id level value" > pp_od_clk_voltage

1. "p" - set the cclk (processor) frequency
2. "core_id" - 0/1/2/3, represents which cpu core you want to select
2. "level" - 0 or 1, "0" represents the min value,  "1" represents the
   max value
3. "value" - the target value of cclk frequency, it should be limited in
   the safe range

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 .../gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
 drivers/gpu/drm/amd/pm/amdgpu_pm.c            |  3 +
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h       |  6 ++
 drivers/gpu/drm/amd/pm/inc/smu_types.h        |  1 +
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 78 ++++++++++++++++++-
 5 files changed, 88 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 57b24c4c205b..a41875ac5dfb 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -156,6 +156,7 @@ enum {
 enum PP_OD_DPM_TABLE_COMMAND {
 	PP_OD_EDIT_SCLK_VDDC_TABLE,
 	PP_OD_EDIT_MCLK_VDDC_TABLE,
+	PP_OD_EDIT_CCLK_VDDC_TABLE,
 	PP_OD_EDIT_VDDC_CURVE,
 	PP_OD_RESTORE_DEFAULT_TABLE,
 	PP_OD_COMMIT_DPM_TABLE,
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index a5be03aa384b..298784f73705 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -800,6 +800,8 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 
 	if (*buf == 's')
 		type = PP_OD_EDIT_SCLK_VDDC_TABLE;
+	if (*buf == 'p')
+		type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 	else if (*buf == 'm')
 		type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 	else if(*buf == 'r')
@@ -916,6 +918,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 		size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 		size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDGFX_OFFSET, buf+size);
 		size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
+		size += smu_print_clk_levels(&adev->smu, SMU_OD_CCLK, buf+size);
 	} else if (adev->powerplay.pp_funcs->print_clock_levels) {
 		size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 		size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 97d788451624..5f781a27cfb7 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -465,6 +465,12 @@ struct smu_context
 	uint32_t gfx_default_soft_max_freq;
 	uint32_t gfx_actual_hard_min_freq;
 	uint32_t gfx_actual_soft_max_freq;
+
+	uint32_t cpu_default_hard_min_freq;
+	uint32_t cpu_default_soft_max_freq;
+	uint32_t cpu_actual_hard_min_freq;
+	uint32_t cpu_actual_soft_max_freq;
+	uint32_t cpu_core_id_select;
 };
 
 struct i2c_adapter;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index 8e428c728e0e..b76270e8767c 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -237,6 +237,7 @@ enum smu_clk_type {
 	SMU_SCLK,
 	SMU_MCLK,
 	SMU_PCIE,
+	SMU_OD_CCLK,
 	SMU_OD_SCLK,
 	SMU_OD_MCLK,
 	SMU_OD_VDDC_CURVE,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 63be82386964..4d02177cf9b0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -449,6 +449,15 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
 			(smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
 		}
 		break;
+	case SMU_OD_CCLK:
+		if (smu->od_enabled) {
+			size = sprintf(buf, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
+			size += sprintf(buf + size, "0: %10uMhz\n",
+			(smu->cpu_actual_hard_min_freq > 0) ? smu->cpu_actual_hard_min_freq : smu->cpu_default_hard_min_freq);
+			size += sprintf(buf + size, "1: %10uMhz\n",
+			(smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
+		}
+		break;
 	case SMU_OD_RANGE:
 		if (smu->od_enabled) {
 			size = sprintf(buf, "%s:\n", "OD_RANGE");
@@ -1245,7 +1254,7 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
 }
 
 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
-							long input[], uint32_t size)
+					long input[], uint32_t size)
 {
 	int ret = 0;
 
@@ -1255,6 +1264,34 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
 	}
 
 	switch (type) {
+	case PP_OD_EDIT_CCLK_VDDC_TABLE:
+		if (size != 3) {
+			dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
+			return -EINVAL;
+		}
+		if (input[0] >= boot_cpu_data.x86_max_cores) {
+			dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
+				boot_cpu_data.x86_max_cores);
+		}
+		smu->cpu_core_id_select = input[0];
+		if (input[1] == 0) {
+			if (input[2] < smu->cpu_default_hard_min_freq) {
+				dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
+					input[2], smu->cpu_default_hard_min_freq);
+				return -EINVAL;
+			}
+			smu->cpu_actual_hard_min_freq = input[2];
+		} else if (input[1] == 1) {
+			if (input[2] > smu->cpu_default_soft_max_freq) {
+				dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
+					input[2], smu->cpu_default_soft_max_freq);
+				return -EINVAL;
+			}
+			smu->cpu_actual_soft_max_freq = input[2];
+		} else {
+			return -EINVAL;
+		}
+		break;
 	case PP_OD_EDIT_SCLK_VDDC_TABLE:
 		if (size != 2) {
 			dev_err(smu->adev->dev, "Input parameter number not correct\n");
@@ -1286,6 +1323,8 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
 		} else {
 			smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 			smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+			smu->cpu_actual_hard_min_freq = smu->cpu_default_hard_min_freq;
+			smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
 
 			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
 									smu->gfx_actual_hard_min_freq, NULL);
@@ -1300,6 +1339,20 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
 				dev_err(smu->adev->dev, "Restore the default soft max sclk failed!");
 				return ret;
 			}
+
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
+							      smu->cpu_actual_hard_min_freq, NULL);
+			if (ret) {
+				dev_err(smu->adev->dev, "Set hard min cclk failed!");
+				return ret;
+			}
+
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
+							      smu->cpu_actual_soft_max_freq, NULL);
+			if (ret) {
+				dev_err(smu->adev->dev, "Set soft max cclk failed!");
+				return ret;
+			}
 		}
 		break;
 	case PP_OD_COMMIT_DPM_TABLE:
@@ -1326,6 +1379,24 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
 				dev_err(smu->adev->dev, "Set soft max sclk failed!");
 				return ret;
 			}
+
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
+							      ((smu->cpu_core_id_select << 20)
+							       | smu->cpu_actual_hard_min_freq),
+							      NULL);
+			if (ret) {
+				dev_err(smu->adev->dev, "Set hard min cclk failed!");
+				return ret;
+			}
+
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
+							      ((smu->cpu_core_id_select << 20)
+							       | smu->cpu_actual_soft_max_freq),
+							      NULL);
+			if (ret) {
+				dev_err(smu->adev->dev, "Set soft max cclk failed!");
+				return ret;
+			}
 		}
 		break;
 	default:
@@ -1351,6 +1422,11 @@ static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
 	smu->gfx_actual_hard_min_freq = 0;
 	smu->gfx_actual_soft_max_freq = 0;
 
+	smu->cpu_default_hard_min_freq = 1400;
+	smu->cpu_default_soft_max_freq = 3500;
+	smu->cpu_actual_hard_min_freq = 0;
+	smu->cpu_actual_soft_max_freq = 0;
+
 	return 0;
 }
 
-- 
2.25.1

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RE: [PATCH 7/7] drm/amd/pm: implement processor fine grain feature for vangogh

[Quan, Evan]

[AMD Official Use Only - Internal Distribution Only]

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Huang Rui
Sent: Friday, January 8, 2021 4:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Hou, Xiaomeng (Matthew) <Xiaomeng.Hou@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>
Subject: [PATCH 7/7] drm/amd/pm: implement processor fine grain feature for vangogh

This patch is to implement the processor fine grain feature for vangogh.
It's similar with gfx clock, the only difference is below:

echo "p core_id level value" > pp_od_clk_voltage

1. "p" - set the cclk (processor) frequency
2. "core_id" - 0/1/2/3, represents which cpu core you want to select
2. "level" - 0 or 1, "0" represents the min value,  "1" represents the
   max value
3. "value" - the target value of cclk frequency, it should be limited in
   the safe range

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 .../gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
 drivers/gpu/drm/amd/pm/amdgpu_pm.c            |  3 +
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h       |  6 ++
 drivers/gpu/drm/amd/pm/inc/smu_types.h        |  1 +
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 78 ++++++++++++++++++-
 5 files changed, 88 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 57b24c4c205b..a41875ac5dfb 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -156,6 +156,7 @@ enum {
 enum PP_OD_DPM_TABLE_COMMAND {
 PP_OD_EDIT_SCLK_VDDC_TABLE,
 PP_OD_EDIT_MCLK_VDDC_TABLE,
+PP_OD_EDIT_CCLK_VDDC_TABLE,
 PP_OD_EDIT_VDDC_CURVE,
 PP_OD_RESTORE_DEFAULT_TABLE,
 PP_OD_COMMIT_DPM_TABLE,
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index a5be03aa384b..298784f73705 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -800,6 +800,8 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,

 if (*buf == 's')
 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
+if (*buf == 'p')
[Quan, Evan] better to use "else if" here.
+type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 else if (*buf == 'm')
 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 else if(*buf == 'r')
@@ -916,6 +918,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDGFX_OFFSET, buf+size);
 size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
+size += smu_print_clk_levels(&adev->smu, SMU_OD_CCLK, buf+size);
 } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 97d788451624..5f781a27cfb7 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -465,6 +465,12 @@ struct smu_context
 uint32_t gfx_default_soft_max_freq;
 uint32_t gfx_actual_hard_min_freq;
 uint32_t gfx_actual_soft_max_freq;
+
+uint32_t cpu_default_hard_min_freq;
+uint32_t cpu_default_soft_max_freq;
+uint32_t cpu_actual_hard_min_freq;
+uint32_t cpu_actual_soft_max_freq;
+uint32_t cpu_core_id_select;
 };

 struct i2c_adapter;
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index 8e428c728e0e..b76270e8767c 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -237,6 +237,7 @@ enum smu_clk_type {
 SMU_SCLK,
 SMU_MCLK,
 SMU_PCIE,
+SMU_OD_CCLK,
 SMU_OD_SCLK,
 SMU_OD_MCLK,
 SMU_OD_VDDC_CURVE,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 63be82386964..4d02177cf9b0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -449,6 +449,15 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
 }
 break;
+case SMU_OD_CCLK:
+if (smu->od_enabled) {
+size = sprintf(buf, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
+size += sprintf(buf + size, "0: %10uMhz\n",
+(smu->cpu_actual_hard_min_freq > 0) ? smu->cpu_actual_hard_min_freq : smu->cpu_default_hard_min_freq);
+size += sprintf(buf + size, "1: %10uMhz\n",
+(smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
+}
+break;
 case SMU_OD_RANGE:
[Quan, Evan] The allowed frequency range for cclk should prompt user here in SMU_OD_RANGE.
 if (smu->od_enabled) {
 size = sprintf(buf, "%s:\n", "OD_RANGE");
@@ -1245,7 +1254,7 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
 }

 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
-long input[], uint32_t size)
+long input[], uint32_t size)
 {
 int ret = 0;

@@ -1255,6 +1264,34 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
 }

 switch (type) {
+case PP_OD_EDIT_CCLK_VDDC_TABLE:
+if (size != 3) {
+dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
+return -EINVAL;
+}
+if (input[0] >= boot_cpu_data.x86_max_cores) {
+dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
+boot_cpu_data.x86_max_cores);
+}
+smu->cpu_core_id_select = input[0];
+if (input[1] == 0) {
+if (input[2] < smu->cpu_default_hard_min_freq) {
+dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
+input[2], smu->cpu_default_hard_min_freq);
+return -EINVAL;
+}
+smu->cpu_actual_hard_min_freq = input[2];
+} else if (input[1] == 1) {
+if (input[2] > smu->cpu_default_soft_max_freq) {
+dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
+input[2], smu->cpu_default_soft_max_freq);
+return -EINVAL;
+}
+smu->cpu_actual_soft_max_freq = input[2];
+} else {
+return -EINVAL;
+}
+break;
 case PP_OD_EDIT_SCLK_VDDC_TABLE:
 if (size != 2) {
 dev_err(smu->adev->dev, "Input parameter number not correct\n");
@@ -1286,6 +1323,8 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
 } else {
 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+smu->cpu_actual_hard_min_freq = smu->cpu_default_hard_min_freq;
+smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;

 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
 smu->gfx_actual_hard_min_freq, NULL);
@@ -1300,6 +1339,20 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
 dev_err(smu->adev->dev, "Restore the default soft max sclk failed!");
 return ret;
 }
+
+ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
+      smu->cpu_actual_hard_min_freq, NULL);
[Quan, Evan] better to name it as "soft_min_freq" instead of "hard_min_freq".
+if (ret) {
+dev_err(smu->adev->dev, "Set hard min cclk failed!");
+return ret;
+}
+
+ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
+      smu->cpu_actual_soft_max_freq, NULL);
+if (ret) {
+dev_err(smu->adev->dev, "Set soft max cclk failed!");
+return ret;
+}
 }
 break;
 case PP_OD_COMMIT_DPM_TABLE:
@@ -1326,6 +1379,24 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
 dev_err(smu->adev->dev, "Set soft max sclk failed!");
 return ret;
 }
+
+ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
+      ((smu->cpu_core_id_select << 20)
+       | smu->cpu_actual_hard_min_freq),
+      NULL);
+if (ret) {
+dev_err(smu->adev->dev, "Set hard min cclk failed!");
+return ret;
+}
+
+ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
+      ((smu->cpu_core_id_select << 20)
+       | smu->cpu_actual_soft_max_freq),
+      NULL);
+if (ret) {
+dev_err(smu->adev->dev, "Set soft max cclk failed!");
+return ret;
+}
 }
 break;
 default:
@@ -1351,6 +1422,11 @@ static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
 smu->gfx_actual_hard_min_freq = 0;
 smu->gfx_actual_soft_max_freq = 0;

+smu->cpu_default_hard_min_freq = 1400;
+smu->cpu_default_soft_max_freq = 3500;
+smu->cpu_actual_hard_min_freq = 0;
+smu->cpu_actual_soft_max_freq = 0;
+
 return 0;
 }

--
2.25.1

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RE: [PATCH 2/7] drm/amd/pm: enhance the real response for smu message

[Quan, Evan]

[AMD Official Use Only - Internal Distribution Only]

Better to make this modification in smu_cmn_wait_for_response.

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Huang Rui
Sent: Friday, January 8, 2021 4:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Hou, Xiaomeng (Matthew) <Xiaomeng.Hou@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>
Subject: [PATCH 2/7] drm/amd/pm: enhance the real response for smu message

The user prefers to know the real response value from C2PMSG 90 register which is written by firmware not -EIO.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index f8260769061c..42b125701436 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -111,6 +111,7 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,  {
 struct amdgpu_device *adev = smu->adev;
 int ret = 0, index = 0;
+int response;

 if (smu->adev->in_pci_err_recovery)
 return 0;
@@ -137,8 +138,9 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,

 ret = smu_cmn_wait_for_response(smu);
 if (ret) {
+response = RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90);
 dev_err(adev->dev, "failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
-       smu_get_message_name(smu, msg), index, param, ret);
+       smu_get_message_name(smu, msg), index, param, response);
 goto out;
 }

--
2.25.1

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RE: [PATCH 6/7] drm/amd/pm: implement the processor clocks which read by metric

[Quan, Evan]

[AMD Official Use Only - Internal Distribution Only]

Patch1, 3-6 are reviewed-by: Evan Quan <evan.quan@amd.com>

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Huang Rui
Sent: Friday, January 8, 2021 4:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Hou, Xiaomeng (Matthew) <Xiaomeng.Hou@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>
Subject: [PATCH 6/7] drm/amd/pm: implement the processor clocks which read by metric

The core processor clocks will be stored in smu metric table, then we
add this runtime information into amdgpu_pm_info interface.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 .../gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
 drivers/gpu/drm/amd/pm/amdgpu_pm.c            | 25 +++++++++++++++++++
 drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h       |  2 ++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c     | 14 +++++++++++
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 11 ++++++++
 5 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 270f8db5115a..57b24c4c205b 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -103,6 +103,7 @@ enum pp_clock_type {

 enum amd_pp_sensors {
 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
+AMDGPU_PP_SENSOR_CPU_CLK,
 AMDGPU_PP_SENSOR_VDDNB,
 AMDGPU_PP_SENSOR_VDDGFX,
 AMDGPU_PP_SENSOR_UVD_VCLK,
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 97c669dd4cac..a5be03aa384b 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -36,6 +36,7 @@
 #include <linux/hwmon-sysfs.h>
 #include <linux/nospec.h>
 #include <linux/pm_runtime.h>
+#include <asm/processor.h>
 #include "hwmgr.h"

 static const struct cg_flag_name clocks[] = {
@@ -3621,6 +3622,27 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
  */
 #if defined(CONFIG_DEBUG_FS)

+static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
+   struct amdgpu_device *adev) {
+uint16_t *p_val;
+uint32_t size;
+int i;
+
+if (is_support_cclk_dpm(adev)) {
+p_val = kcalloc(boot_cpu_data.x86_max_cores, sizeof(uint16_t),
+GFP_KERNEL);
+
+if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
+    (void *)p_val, &size)) {
+for (i = 0; i < boot_cpu_data.x86_max_cores; i++)
+seq_printf(m, "\t%u MHz (CPU%d)\n",
+   *(p_val + i), i);
+}
+
+kfree(p_val);
+}
+}
+
 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
 {
 uint32_t value;
@@ -3631,6 +3653,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
 /* GPU Clocks */
 size = sizeof(value);
 seq_printf(m, "GFX Clocks and Power:\n");
+
+amdgpu_debugfs_prints_cpu_info(m, adev);
+
 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index a9622b5e9c7b..97d788451624 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1122,6 +1122,7 @@ typedef enum {
 METRICS_CURR_DCLK1,
 METRICS_CURR_FCLK,
 METRICS_CURR_DCEFCLK,
+METRICS_AVERAGE_CPUCLK,
 METRICS_AVERAGE_GFXCLK,
 METRICS_AVERAGE_SOCCLK,
 METRICS_AVERAGE_FCLK,
@@ -1250,6 +1251,7 @@ extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;

 bool is_support_sw_smu(struct amdgpu_device *adev);
+bool is_support_cclk_dpm(struct amdgpu_device *adev);
 int smu_reset(struct smu_context *smu);
 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index d80f7f8efdcd..22868ad87628 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -288,6 +288,20 @@ bool is_support_sw_smu(struct amdgpu_device *adev)
 return false;
 }

+bool is_support_cclk_dpm(struct amdgpu_device *adev)
+{
+struct smu_context *smu = &adev->smu;
+
+if (!is_support_sw_smu(adev))
+return false;
+
+if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
+return false;
+
+return true;
+}
+
+
 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 {
 struct smu_table_context *smu_table = &smu->smu_table;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 233c6e4ddd01..63be82386964 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -34,6 +34,7 @@
 #include "soc15_common.h"
 #include "asic_reg/gc/gc_10_3_0_offset.h"
 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
+#include <asm/processor.h>

 /*
  * DO NOT use these for err/warn/info/debug messages.
@@ -285,6 +286,10 @@ static int vangogh_get_smu_metrics_data(struct smu_context *smu,
 case METRICS_VOLTAGE_VDDSOC:
 *value = metrics->Voltage[1];
 break;
+case METRICS_AVERAGE_CPUCLK:
+memcpy(value, &metrics->CoreFrequency[0],
+       boot_cpu_data.x86_max_cores * sizeof(uint16_t));
+break;
 default:
 *value = UINT_MAX;
 break;
@@ -1113,6 +1118,12 @@ static int vangogh_read_sensor(struct smu_context *smu,
    (uint32_t *)data);
 *size = 4;
 break;
+case AMDGPU_PP_SENSOR_CPU_CLK:
+ret = vangogh_get_smu_metrics_data(smu,
+   METRICS_AVERAGE_CPUCLK,
+   (uint32_t *)data);
+*size = boot_cpu_data.x86_max_cores * sizeof(uint16_t);
+break;
 default:
 ret = -EOPNOTSUPP;
 break;
--
2.25.1

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Re: [PATCH 7/7] drm/amd/pm: implement processor fine grain feature for vangogh

[Huang Rui]

On Fri, Jan 08, 2021 at 06:01:08PM +0800, Quan, Evan wrote:
> [AMD Official Use Only - Internal Distribution Only]
> 
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Huang Rui
> Sent: Friday, January 8, 2021 4:55 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Hou, Xiaomeng (Matthew) <Xiaomeng.Hou@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>
> Subject: [PATCH 7/7] drm/amd/pm: implement processor fine grain feature for vangogh
> 
> This patch is to implement the processor fine grain feature for vangogh.
> It's similar with gfx clock, the only difference is below:
> 
> echo "p core_id level value" > pp_od_clk_voltage
> 
> 1. "p" - set the cclk (processor) frequency
> 2. "core_id" - 0/1/2/3, represents which cpu core you want to select
> 2. "level" - 0 or 1, "0" represents the min value,  "1" represents the
>    max value
> 3. "value" - the target value of cclk frequency, it should be limited in
>    the safe range
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  .../gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
>  drivers/gpu/drm/amd/pm/amdgpu_pm.c            |  3 +
>  drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h       |  6 ++
>  drivers/gpu/drm/amd/pm/inc/smu_types.h        |  1 +
>  .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 78 ++++++++++++++++++-
>  5 files changed, 88 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 57b24c4c205b..a41875ac5dfb 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -156,6 +156,7 @@ enum {
>  enum PP_OD_DPM_TABLE_COMMAND {
>  PP_OD_EDIT_SCLK_VDDC_TABLE,
>  PP_OD_EDIT_MCLK_VDDC_TABLE,
> +PP_OD_EDIT_CCLK_VDDC_TABLE,
>  PP_OD_EDIT_VDDC_CURVE,
>  PP_OD_RESTORE_DEFAULT_TABLE,
>  PP_OD_COMMIT_DPM_TABLE,
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index a5be03aa384b..298784f73705 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -800,6 +800,8 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
> 
>  if (*buf == 's')
>  type = PP_OD_EDIT_SCLK_VDDC_TABLE;
> +if (*buf == 'p')
> [Quan, Evan] better to use "else if" here.

Fine.

> +type = PP_OD_EDIT_CCLK_VDDC_TABLE;
>  else if (*buf == 'm')
>  type = PP_OD_EDIT_MCLK_VDDC_TABLE;
>  else if(*buf == 'r')
> @@ -916,6 +918,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
>  size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
>  size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDGFX_OFFSET, buf+size);
>  size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
> +size += smu_print_clk_levels(&adev->smu, SMU_OD_CCLK, buf+size);
>  } else if (adev->powerplay.pp_funcs->print_clock_levels) {
>  size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
>  size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index 97d788451624..5f781a27cfb7 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -465,6 +465,12 @@ struct smu_context
>  uint32_t gfx_default_soft_max_freq;
>  uint32_t gfx_actual_hard_min_freq;
>  uint32_t gfx_actual_soft_max_freq;
> +
> +uint32_t cpu_default_hard_min_freq;
> +uint32_t cpu_default_soft_max_freq;
> +uint32_t cpu_actual_hard_min_freq;
> +uint32_t cpu_actual_soft_max_freq;
> +uint32_t cpu_core_id_select;
>  };
> 
>  struct i2c_adapter;
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
> index 8e428c728e0e..b76270e8767c 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
> @@ -237,6 +237,7 @@ enum smu_clk_type {
>  SMU_SCLK,
>  SMU_MCLK,
>  SMU_PCIE,
> +SMU_OD_CCLK,
>  SMU_OD_SCLK,
>  SMU_OD_MCLK,
>  SMU_OD_VDDC_CURVE,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 63be82386964..4d02177cf9b0 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -449,6 +449,15 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
>  (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
>  }
>  break;
> +case SMU_OD_CCLK:
> +if (smu->od_enabled) {
> +size = sprintf(buf, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
> +size += sprintf(buf + size, "0: %10uMhz\n",
> +(smu->cpu_actual_hard_min_freq > 0) ? smu->cpu_actual_hard_min_freq : smu->cpu_default_hard_min_freq);
> +size += sprintf(buf + size, "1: %10uMhz\n",
> +(smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
> +}
> +break;
>  case SMU_OD_RANGE:
> [Quan, Evan] The allowed frequency range for cclk should prompt user here in SMU_OD_RANGE.

Fine.

>  if (smu->od_enabled) {
>  size = sprintf(buf, "%s:\n", "OD_RANGE");
> @@ -1245,7 +1254,7 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
>  }
> 
>  static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
> -long input[], uint32_t size)
> +long input[], uint32_t size)
>  {
>  int ret = 0;
> 
> @@ -1255,6 +1264,34 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
>  }
> 
>  switch (type) {
> +case PP_OD_EDIT_CCLK_VDDC_TABLE:
> +if (size != 3) {
> +dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
> +return -EINVAL;
> +}
> +if (input[0] >= boot_cpu_data.x86_max_cores) {
> +dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
> +boot_cpu_data.x86_max_cores);
> +}
> +smu->cpu_core_id_select = input[0];
> +if (input[1] == 0) {
> +if (input[2] < smu->cpu_default_hard_min_freq) {
> +dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
> +input[2], smu->cpu_default_hard_min_freq);
> +return -EINVAL;
> +}
> +smu->cpu_actual_hard_min_freq = input[2];
> +} else if (input[1] == 1) {
> +if (input[2] > smu->cpu_default_soft_max_freq) {
> +dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
> +input[2], smu->cpu_default_soft_max_freq);
> +return -EINVAL;
> +}
> +smu->cpu_actual_soft_max_freq = input[2];
> +} else {
> +return -EINVAL;
> +}
> +break;
>  case PP_OD_EDIT_SCLK_VDDC_TABLE:
>  if (size != 2) {
>  dev_err(smu->adev->dev, "Input parameter number not correct\n");
> @@ -1286,6 +1323,8 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
>  } else {
>  smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
>  smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +smu->cpu_actual_hard_min_freq = smu->cpu_default_hard_min_freq;
> +smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> 
>  ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
>  smu->gfx_actual_hard_min_freq, NULL);
> @@ -1300,6 +1339,20 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
>  dev_err(smu->adev->dev, "Restore the default soft max sclk failed!");
>  return ret;
>  }
> +
> +ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
> +      smu->cpu_actual_hard_min_freq, NULL);
> [Quan, Evan] better to name it as "soft_min_freq" instead of "hard_min_freq".

Fine.

Thanks for your comments.

Ray

> +if (ret) {
> +dev_err(smu->adev->dev, "Set hard min cclk failed!");
> +return ret;
> +}
> +
> +ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
> +      smu->cpu_actual_soft_max_freq, NULL);
> +if (ret) {
> +dev_err(smu->adev->dev, "Set soft max cclk failed!");
> +return ret;
> +}
>  }
>  break;
>  case PP_OD_COMMIT_DPM_TABLE:
> @@ -1326,6 +1379,24 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
>  dev_err(smu->adev->dev, "Set soft max sclk failed!");
>  return ret;
>  }
> +
> +ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
> +      ((smu->cpu_core_id_select << 20)
> +       | smu->cpu_actual_hard_min_freq),
> +      NULL);
> +if (ret) {
> +dev_err(smu->adev->dev, "Set hard min cclk failed!");
> +return ret;
> +}
> +
> +ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
> +      ((smu->cpu_core_id_select << 20)
> +       | smu->cpu_actual_soft_max_freq),
> +      NULL);
> +if (ret) {
> +dev_err(smu->adev->dev, "Set soft max cclk failed!");
> +return ret;
> +}
>  }
>  break;
>  default:
> @@ -1351,6 +1422,11 @@ static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
>  smu->gfx_actual_hard_min_freq = 0;
>  smu->gfx_actual_soft_max_freq = 0;
> 
> +smu->cpu_default_hard_min_freq = 1400;
> +smu->cpu_default_soft_max_freq = 3500;
> +smu->cpu_actual_hard_min_freq = 0;
> +smu->cpu_actual_soft_max_freq = 0;
> +
>  return 0;
>  }
> 
> --
> 2.25.1
> 
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Re: [PATCH 7/7] drm/amd/pm: implement processor fine grain feature for vangogh

[Huang Rui]

On Fri, Jan 08, 2021 at 06:01:08PM +0800, Quan, Evan wrote:
> [AMD Official Use Only - Internal Distribution Only]
> 
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Huang Rui
> Sent: Friday, January 8, 2021 4:55 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Hou, Xiaomeng (Matthew) <Xiaomeng.Hou@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>
> Subject: [PATCH 7/7] drm/amd/pm: implement processor fine grain feature for vangogh
> 
> This patch is to implement the processor fine grain feature for vangogh.
> It's similar with gfx clock, the only difference is below:
> 
> echo "p core_id level value" > pp_od_clk_voltage
> 
> 1. "p" - set the cclk (processor) frequency
> 2. "core_id" - 0/1/2/3, represents which cpu core you want to select
> 2. "level" - 0 or 1, "0" represents the min value,  "1" represents the
>    max value
> 3. "value" - the target value of cclk frequency, it should be limited in
>    the safe range
> 
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
>  .../gpu/drm/amd/include/kgd_pp_interface.h    |  1 +
>  drivers/gpu/drm/amd/pm/amdgpu_pm.c            |  3 +
>  drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h       |  6 ++
>  drivers/gpu/drm/amd/pm/inc/smu_types.h        |  1 +
>  .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 78 ++++++++++++++++++-
>  5 files changed, 88 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 57b24c4c205b..a41875ac5dfb 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -156,6 +156,7 @@ enum {
>  enum PP_OD_DPM_TABLE_COMMAND {
>  PP_OD_EDIT_SCLK_VDDC_TABLE,
>  PP_OD_EDIT_MCLK_VDDC_TABLE,
> +PP_OD_EDIT_CCLK_VDDC_TABLE,
>  PP_OD_EDIT_VDDC_CURVE,
>  PP_OD_RESTORE_DEFAULT_TABLE,
>  PP_OD_COMMIT_DPM_TABLE,
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index a5be03aa384b..298784f73705 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -800,6 +800,8 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
> 
>  if (*buf == 's')
>  type = PP_OD_EDIT_SCLK_VDDC_TABLE;
> +if (*buf == 'p')
> [Quan, Evan] better to use "else if" here.
> +type = PP_OD_EDIT_CCLK_VDDC_TABLE;
>  else if (*buf == 'm')
>  type = PP_OD_EDIT_MCLK_VDDC_TABLE;
>  else if(*buf == 'r')
> @@ -916,6 +918,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
>  size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
>  size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDGFX_OFFSET, buf+size);
>  size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
> +size += smu_print_clk_levels(&adev->smu, SMU_OD_CCLK, buf+size);
>  } else if (adev->powerplay.pp_funcs->print_clock_levels) {
>  size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
>  size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index 97d788451624..5f781a27cfb7 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -465,6 +465,12 @@ struct smu_context
>  uint32_t gfx_default_soft_max_freq;
>  uint32_t gfx_actual_hard_min_freq;
>  uint32_t gfx_actual_soft_max_freq;
> +
> +uint32_t cpu_default_hard_min_freq;
> +uint32_t cpu_default_soft_max_freq;
> +uint32_t cpu_actual_hard_min_freq;
> +uint32_t cpu_actual_soft_max_freq;
> +uint32_t cpu_core_id_select;
>  };
> 
>  struct i2c_adapter;
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
> index 8e428c728e0e..b76270e8767c 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
> @@ -237,6 +237,7 @@ enum smu_clk_type {
>  SMU_SCLK,
>  SMU_MCLK,
>  SMU_PCIE,
> +SMU_OD_CCLK,
>  SMU_OD_SCLK,
>  SMU_OD_MCLK,
>  SMU_OD_VDDC_CURVE,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 63be82386964..4d02177cf9b0 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -449,6 +449,15 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
>  (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
>  }
>  break;
> +case SMU_OD_CCLK:
> +if (smu->od_enabled) {
> +size = sprintf(buf, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
> +size += sprintf(buf + size, "0: %10uMhz\n",
> +(smu->cpu_actual_hard_min_freq > 0) ? smu->cpu_actual_hard_min_freq : smu->cpu_default_hard_min_freq);
> +size += sprintf(buf + size, "1: %10uMhz\n",
> +(smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
> +}
> +break;
>  case SMU_OD_RANGE:
> [Quan, Evan] The allowed frequency range for cclk should prompt user here in SMU_OD_RANGE.

I think about it again, we should not combine the fine grain and OD feature
together on the prints. APU doesn't support OD, it will make user confused.

Alternative, we can combine the fine grain prints both cpu and gfx together
here instead.

Thanks,
Ray

>  if (smu->od_enabled) {
>  size = sprintf(buf, "%s:\n", "OD_RANGE");
> @@ -1245,7 +1254,7 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
>  }
> 
>  static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
> -long input[], uint32_t size)
> +long input[], uint32_t size)
>  {
>  int ret = 0;
> 
> @@ -1255,6 +1264,34 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
>  }
> 
>  switch (type) {
> +case PP_OD_EDIT_CCLK_VDDC_TABLE:
> +if (size != 3) {
> +dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
> +return -EINVAL;
> +}
> +if (input[0] >= boot_cpu_data.x86_max_cores) {
> +dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
> +boot_cpu_data.x86_max_cores);
> +}
> +smu->cpu_core_id_select = input[0];
> +if (input[1] == 0) {
> +if (input[2] < smu->cpu_default_hard_min_freq) {
> +dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
> +input[2], smu->cpu_default_hard_min_freq);
> +return -EINVAL;
> +}
> +smu->cpu_actual_hard_min_freq = input[2];
> +} else if (input[1] == 1) {
> +if (input[2] > smu->cpu_default_soft_max_freq) {
> +dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
> +input[2], smu->cpu_default_soft_max_freq);
> +return -EINVAL;
> +}
> +smu->cpu_actual_soft_max_freq = input[2];
> +} else {
> +return -EINVAL;
> +}
> +break;
>  case PP_OD_EDIT_SCLK_VDDC_TABLE:
>  if (size != 2) {
>  dev_err(smu->adev->dev, "Input parameter number not correct\n");
> @@ -1286,6 +1323,8 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
>  } else {
>  smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
>  smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
> +smu->cpu_actual_hard_min_freq = smu->cpu_default_hard_min_freq;
> +smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
> 
>  ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
>  smu->gfx_actual_hard_min_freq, NULL);
> @@ -1300,6 +1339,20 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
>  dev_err(smu->adev->dev, "Restore the default soft max sclk failed!");
>  return ret;
>  }
> +
> +ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
> +      smu->cpu_actual_hard_min_freq, NULL);
> [Quan, Evan] better to name it as "soft_min_freq" instead of "hard_min_freq".
> +if (ret) {
> +dev_err(smu->adev->dev, "Set hard min cclk failed!");
> +return ret;
> +}
> +
> +ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
> +      smu->cpu_actual_soft_max_freq, NULL);
> +if (ret) {
> +dev_err(smu->adev->dev, "Set soft max cclk failed!");
> +return ret;
> +}
>  }
>  break;
>  case PP_OD_COMMIT_DPM_TABLE:
> @@ -1326,6 +1379,24 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
>  dev_err(smu->adev->dev, "Set soft max sclk failed!");
>  return ret;
>  }
> +
> +ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
> +      ((smu->cpu_core_id_select << 20)
> +       | smu->cpu_actual_hard_min_freq),
> +      NULL);
> +if (ret) {
> +dev_err(smu->adev->dev, "Set hard min cclk failed!");
> +return ret;
> +}
> +
> +ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
> +      ((smu->cpu_core_id_select << 20)
> +       | smu->cpu_actual_soft_max_freq),
> +      NULL);
> +if (ret) {
> +dev_err(smu->adev->dev, "Set soft max cclk failed!");
> +return ret;
> +}
>  }
>  break;
>  default:
> @@ -1351,6 +1422,11 @@ static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
>  smu->gfx_actual_hard_min_freq = 0;
>  smu->gfx_actual_soft_max_freq = 0;
> 
> +smu->cpu_default_hard_min_freq = 1400;
> +smu->cpu_default_soft_max_freq = 3500;
> +smu->cpu_actual_hard_min_freq = 0;
> +smu->cpu_actual_soft_max_freq = 0;
> +
>  return 0;
>  }
> 
> --
> 2.25.1
> 
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