* [PATCH v5 0/8] acpi: Some fixes for pxb support for ARM virt machine
@ 2021-01-14 10:06 Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 1/8] acpi: Allow DSDT acpi table changes Jiahui Cen
` (7 more replies)
0 siblings, 8 replies; 9+ messages in thread
From: Jiahui Cen @ 2021-01-14 10:06 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, Jiahui Cen, Eduardo Habkost, Michael S. Tsirkin,
Ard Biesheuvel, Richard Henderson, Paolo Bonzini, Igor Mammedov,
Laszlo Ersek, wu.wubin
This patch series adds some fixes for ARM virt machine pxb support.
1. Pass addr offset for IO, MMIO and bus number when builing crs, because
the addr_trans is needed to describe an addr resource. [1]
2. Inform guest os not to ignore the resource map generated by firmware as
the x86 default way. [2]
3. Enable pxb for ARM virt machine by default.
4. Update expected DSDT files with the above changes and enable the pxb
unit-test.
v4->v5:
* Modify commit logs of patch [2/8] and [8/8] which confuse git-am.
v3->v4:
* Separate the patch of ordering root buses for further discussion. [3]
v2->v3:
* Reorder the root bridges.
* Exclude resources of extra root bridges from main root bridge's _CRS.
v1->v2:
* Update expected DSDT files.
* Quote PCI Firmware spec as comments.
[1]: https://lore.kernel.org/qemu-devel/20201217132747.4744-1-cenjiahui@huawei.com/
[2]: https://lore.kernel.org/qemu-devel/20201217132926.4812-1-cenjiahui@huawei.com/
[3]: https://lore.kernel.org/qemu-devel/dca69f55-dfd1-3f97-dc3f-13eeedec5027@huawei.com/
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
Jiahui Cen (8):
acpi: Allow DSDT acpi table changes
acpi: Fix unmatched expected DSDT.pxb file
acpi: Add addr offset in build_crs
acpi/gpex: Inform os to keep firmware resource map
acpi/gpex: Exclude pxb's resources from PCI0
Kconfig: Compile PXB for ARM_VIRT
acpi: Enable pxb unit-test for ARM virt machine
acpi: Update _DSM method in expected files
hw/acpi/aml-build.c | 18 ++--
hw/i386/acpi-build.c | 3 +-
hw/pci-bridge/Kconfig | 2 +-
hw/pci-host/gpex-acpi.c | 87 ++++++++++++++------
include/hw/acpi/aml-build.h | 4 +-
tests/data/acpi/microvm/DSDT.pcie | Bin 3023 -> 3031 bytes
tests/data/acpi/virt/DSDT | Bin 5196 -> 5204 bytes
tests/data/acpi/virt/DSDT.memhp | Bin 6557 -> 6565 bytes
tests/data/acpi/virt/DSDT.numamem | Bin 5196 -> 5204 bytes
tests/data/acpi/virt/DSDT.pxb | Bin 7802 -> 7689 bytes
tests/qtest/bios-tables-test.c | 4 -
11 files changed, 79 insertions(+), 39 deletions(-)
--
2.29.2
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 1/8] acpi: Allow DSDT acpi table changes
2021-01-14 10:06 [PATCH v5 0/8] acpi: Some fixes for pxb support for ARM virt machine Jiahui Cen
@ 2021-01-14 10:06 ` Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 2/8] acpi: Fix unmatched expected DSDT.pxb file Jiahui Cen
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Jiahui Cen @ 2021-01-14 10:06 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, Jiahui Cen, Eduardo Habkost, Michael S. Tsirkin,
Ard Biesheuvel, Richard Henderson, Paolo Bonzini, Igor Mammedov,
Laszlo Ersek, wu.wubin
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..42418e58e7 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,6 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/microvm/DSDT.pcie",
+"tests/data/acpi/virt/DSDT",
+"tests/data/acpi/virt/DSDT.memhp",
+"tests/data/acpi/virt/DSDT.numamem",
+"tests/data/acpi/virt/DSDT.pxb",
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 2/8] acpi: Fix unmatched expected DSDT.pxb file
2021-01-14 10:06 [PATCH v5 0/8] acpi: Some fixes for pxb support for ARM virt machine Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 1/8] acpi: Allow DSDT acpi table changes Jiahui Cen
@ 2021-01-14 10:06 ` Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 3/8] acpi: Add addr offset in build_crs Jiahui Cen
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Jiahui Cen @ 2021-01-14 10:06 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, Jiahui Cen, Eduardo Habkost, Michael S. Tsirkin,
Ard Biesheuvel, Richard Henderson, Paolo Bonzini, Igor Mammedov,
Laszlo Ersek, wu.wubin
Commit fe1127da11 ("unit-test: Add the binary file and clear diff.h") does
not use the up-to-date expected file for pxb for ARM virt.
Fix the expected DSDT.pxb file.
Full diff of changed file disassembly:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/virt/DSDT.pxb, Thu Jan 14 09:33:09 2021
+ * Disassembly of tests/data/acpi/virt/DSDT.pxb, Thu Jan 14 13:34:47 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00001E7A (7802)
+ * Length 0x00001DF9 (7673)
* Revision 0x02
- * Checksum 0x57
+ * Checksum 0x42
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -45,32 +45,6 @@
})
}
- Device (FLS0)
- {
- Name (_HID, "LNRO0015") // _HID: Hardware ID
- Name (_UID, Zero) // _UID: Unique ID
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- Memory32Fixed (ReadWrite,
- 0x00000000, // Address Base
- 0x04000000, // Address Length
- )
- })
- }
-
- Device (FLS1)
- {
- Name (_HID, "LNRO0015") // _HID: Hardware ID
- Name (_UID, One) // _UID: Unique ID
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- Memory32Fixed (ReadWrite,
- 0x04000000, // Address Base
- 0x04000000, // Address Length
- )
- })
- }
-
Device (FWCF)
{
Name (_HID, "QEMU0002") // _HID: Hardware ID
@@ -665,9 +639,6 @@
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
- Name (_ADR, Zero) // _ADR: Address
- Name (_CCA, One) // _CCA: Cache Coherency Attribute
- Name (_SEG, Zero) // _SEG: PCI Segment
Name (_BBN, 0x80) // _BBN: BIOS Bus Number
Name (_UID, 0x80) // _UID: Unique ID
Name (_STR, Unicode ("pxb Device")) // _STR: Description String
@@ -1857,7 +1828,7 @@
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
- Name (_UID, "PCI0") // _UID: Unique ID
+ Name (_UID, Zero) // _UID: Unique ID
Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
@@ -2983,41 +2954,37 @@
Return (0x0000004010000000)
}
- Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
- Return (ResourceTemplate ()
- {
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, // Granularity
- 0x0000, // Range Minimum
- 0x007F, // Range Maximum
- 0x0000, // Translation Offset
- 0x0080, // Length
- ,, )
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
- 0x00000000, // Granularity
- 0x10000000, // Range Minimum
- 0x3EFEFFFF, // Range Maximum
- 0x00000000, // Translation Offset
- 0x2EFF0000, // Length
- ,, , AddressRangeMemory, TypeStatic)
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x00000000, // Granularity
- 0x00000000, // Range Minimum
- 0x0000FFFF, // Range Maximum
- 0x3EFF0000, // Translation Offset
- 0x00010000, // Length
- ,, , TypeStatic, DenseTranslation)
- QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
- 0x0000000000000000, // Granularity
- 0x0000008000000000, // Range Minimum
- 0x000000FFFFFFFFFF, // Range Maximum
- 0x0000000000000000, // Translation Offset
- 0x0000008000000000, // Length
- ,, , AddressRangeMemory, TypeStatic)
- })
- }
-
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x007F, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0080, // Length
+ ,, )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x10000000, // Range Minimum
+ 0x3EFEFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x2EFF0000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ 0x3EFF0000, // Translation Offset
+ 0x00010000, // Length
+ ,, , TypeStatic, DenseTranslation)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000008000000000, // Range Minimum
+ 0x000000FFFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000008000000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
Fixes: fe1127da11 ("unit-test: Add the binary file and clear diff.h")
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
tests/data/acpi/virt/DSDT.pxb | Bin 7802 -> 7673 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/tests/data/acpi/virt/DSDT.pxb b/tests/data/acpi/virt/DSDT.pxb
index d5f0533a02d62bc2ae2db9b9de9484e5c06652fe..76f5f1c2fd487644c6b4f827a70ad770edb9fdc9 100644
GIT binary patch
delta 70
zcmV-M0J;DAJo!5cL{mgm`5gcN0z#1r8v=ygktblW?YIa6OPZ6X2_m!G35f{>PNz^q
cNt3DxACrg^53`&Ttq27OUqez;vr-%=0*oRUFaQ7m
delta 217
zcmexq{mX{SCD<jTN{)enDSRTAG*j!-iRuaUhHgH=1|0Doo-VvTenI{Q28N~#9Py!^
zE<n;bC|FRCi?5B7fsp|MSSlH!n?PC&v1wsM*TMqS1=eEW7Vhi@(GuwD8){%+U<5Qj
zIK*+|g83XwzOyGgaw_pVx&(nNb#?@r6YT1~If1i>lgWL><aa`bth@ovo(7xch1YU$
Qia3I;VOX;HqO=AR0CN5_Pyhe`
--
2.29.2
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 3/8] acpi: Add addr offset in build_crs
2021-01-14 10:06 [PATCH v5 0/8] acpi: Some fixes for pxb support for ARM virt machine Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 1/8] acpi: Allow DSDT acpi table changes Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 2/8] acpi: Fix unmatched expected DSDT.pxb file Jiahui Cen
@ 2021-01-14 10:06 ` Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 4/8] acpi/gpex: Inform os to keep firmware resource map Jiahui Cen
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Jiahui Cen @ 2021-01-14 10:06 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, Jiahui Cen, Eduardo Habkost, Michael S. Tsirkin,
Ard Biesheuvel, Richard Henderson, Paolo Bonzini, Igor Mammedov,
Laszlo Ersek, wu.wubin
AML needs Address Translation offset to describe how a bridge translates
addresses accross the bridge when using an address descriptor, and
especially on ARM, the translation offset of pio resource is usually
non zero.
Therefore, it's necessary to pass offset for pio, mmio32, mmio64 and bus
number into build_crs.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
hw/acpi/aml-build.c | 18 ++++++++++--------
hw/i386/acpi-build.c | 3 ++-
hw/pci-host/gpex-acpi.c | 3 ++-
include/hw/acpi/aml-build.h | 4 +++-
4 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index f976aa667b..7b6ebb0cc8 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -2076,7 +2076,9 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL, NULL);
}
-Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
+Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset,
+ uint32_t mmio32_offset, uint64_t mmio64_offset,
+ uint16_t bus_nr_offset)
{
Aml *crs = aml_resource_template();
CrsRangeSet temp_range_set;
@@ -2189,10 +2191,10 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
for (i = 0; i < temp_range_set.io_ranges->len; i++) {
entry = g_ptr_array_index(temp_range_set.io_ranges, i);
aml_append(crs,
- aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
- AML_POS_DECODE, AML_ENTIRE_RANGE,
- 0, entry->base, entry->limit, 0,
- entry->limit - entry->base + 1));
+ aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_POS_DECODE, AML_ENTIRE_RANGE,
+ 0, entry->base, entry->limit, io_offset,
+ entry->limit - entry->base + 1));
crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
}
@@ -2205,7 +2207,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
AML_MAX_FIXED, AML_NON_CACHEABLE,
AML_READ_WRITE,
- 0, entry->base, entry->limit, 0,
+ 0, entry->base, entry->limit, mmio32_offset,
entry->limit - entry->base + 1));
crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
}
@@ -2217,7 +2219,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
AML_MAX_FIXED, AML_NON_CACHEABLE,
AML_READ_WRITE,
- 0, entry->base, entry->limit, 0,
+ 0, entry->base, entry->limit, mmio64_offset,
entry->limit - entry->base + 1));
crs_range_insert(range_set->mem_64bit_ranges,
entry->base, entry->limit);
@@ -2230,7 +2232,7 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
0,
pci_bus_num(host->bus),
max_bus,
- 0,
+ bus_nr_offset,
max_bus - pci_bus_num(host->bus) + 1));
return crs;
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index f18b71dea9..f56d699c7f 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1360,7 +1360,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
}
aml_append(dev, build_prt(false));
- crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
+ crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
+ 0, 0, 0, 0);
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(scope, dev);
aml_append(dsdt, scope);
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 7f20ee1c98..11b3db8f71 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -168,7 +168,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
* 1. The resources the pci-brige/pcie-root-port need.
* 2. The resources the devices behind pxb need.
*/
- crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
+ crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
+ cfg->pio.base, 0, 0, 0);
aml_append(dev, aml_name_decl("_CRS", crs));
acpi_dsdt_add_pci_osc(dev);
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index e727bea1bc..54a5aec4d7 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -452,7 +452,9 @@ void crs_replace_with_free_ranges(GPtrArray *ranges,
void crs_range_set_init(CrsRangeSet *range_set);
void crs_range_set_free(CrsRangeSet *range_set);
-Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set);
+Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset,
+ uint32_t mmio32_offset, uint64_t mmio64_offset,
+ uint16_t bus_nr_offset);
void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
uint64_t len, int node, MemoryAffinityFlags flags);
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 4/8] acpi/gpex: Inform os to keep firmware resource map
2021-01-14 10:06 [PATCH v5 0/8] acpi: Some fixes for pxb support for ARM virt machine Jiahui Cen
` (2 preceding siblings ...)
2021-01-14 10:06 ` [PATCH v5 3/8] acpi: Add addr offset in build_crs Jiahui Cen
@ 2021-01-14 10:06 ` Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 5/8] acpi/gpex: Exclude pxb's resources from PCI0 Jiahui Cen
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Jiahui Cen @ 2021-01-14 10:06 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, Jiahui Cen, Eduardo Habkost, Michael S. Tsirkin,
Ard Biesheuvel, Richard Henderson, Paolo Bonzini, Igor Mammedov,
Laszlo Ersek, wu.wubin
There may be some differences in pci resource assignment between guest os
and firmware.
Eg. A Bridge with Bus [d2]
-+-[0000:d2]---01.0-[d3]----01.0
where [d2:01.00] is a pcie-pci-bridge with BAR0 (mem, 64-bit, non-pref) [size=256]
[d3:01.00] is a PCI Device with BAR0 (mem, 64-bit, pref) [size=128K]
BAR4 (mem, 64-bit, pref) [size=64M]
In EDK2, the Resource Map would be:
PciBus: Resource Map for Bridge [D2|01|00]
Type = PMem64; Base = 0x8004000000; Length = 0x4100000; Alignment = 0x3FFFFFF
Base = 0x8004000000; Length = 0x4000000; Alignment = 0x3FFFFFF; Owner = PCI [D3|01|00:20]
Base = 0x8008000000; Length = 0x20000; Alignment = 0x1FFFF; Owner = PCI [D3|01|00:10]
Type = Mem64; Base = 0x8008100000; Length = 0x100; Alignment = 0xFFF
It would use 0x4100000 to calculate the root bus's PMem64 resource window.
While in Linux, kernel will use 0x1FFFFFF as the alignment to calculate
the PMem64 size, which would be 0x6000000. So kernel would try to
allocate 0x6000000 from the PMem64 resource window, but since the window
size is 0x4100000 as assigned by EDK2, the allocation would fail.
The diffences could result in resource assignment failure.
Using _DSM #5 method to inform guest os not to ignore the PCI configuration
that firmware has done at boot time could handle the differences.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
hw/pci-host/gpex-acpi.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index 11b3db8f71..cb13e75d2f 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -112,10 +112,26 @@ static void acpi_dsdt_add_pci_osc(Aml *dev)
UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
ifctx = aml_if(aml_equal(aml_arg(0), UUID));
ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
- uint8_t byte_list[1] = {1};
- buf = aml_buffer(1, byte_list);
+ uint8_t byte_list[] = {
+ 0x1 << 0 /* support for functions other than function 0 */ |
+ 0x1 << 5 /* support for function 5 */
+ };
+ buf = aml_buffer(ARRAY_SIZE(byte_list), byte_list);
aml_append(ifctx1, aml_return(buf));
aml_append(ifctx, ifctx1);
+
+ /*
+ * PCI Firmware Specification 3.1
+ * 4.6.5. _DSM for Ignoring PCI Boot Configurations
+ */
+ /* Arg2: Function Index: 5 */
+ ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(5)));
+ /*
+ * 0 - The operating system must not ignore the PCI configuration that
+ * firmware has done at boot time.
+ */
+ aml_append(ifctx1, aml_return(aml_int(0)));
+ aml_append(ifctx, ifctx1);
aml_append(method, ifctx);
byte_list[0] = 0;
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 5/8] acpi/gpex: Exclude pxb's resources from PCI0
2021-01-14 10:06 [PATCH v5 0/8] acpi: Some fixes for pxb support for ARM virt machine Jiahui Cen
` (3 preceding siblings ...)
2021-01-14 10:06 ` [PATCH v5 4/8] acpi/gpex: Inform os to keep firmware resource map Jiahui Cen
@ 2021-01-14 10:06 ` Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 6/8] Kconfig: Compile PXB for ARM_VIRT Jiahui Cen
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Jiahui Cen @ 2021-01-14 10:06 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, Jiahui Cen, Eduardo Habkost, Michael S. Tsirkin,
Ard Biesheuvel, Richard Henderson, Paolo Bonzini, Igor Mammedov,
Laszlo Ersek, wu.wubin
Exclude the resources of extra root bridges from PCI0's _CRS. Otherwise,
the resource windows would overlap in guest, and the IO resource window
would fail to be registered.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
hw/pci-host/gpex-acpi.c | 64 +++++++++++++-------
1 file changed, 43 insertions(+), 21 deletions(-)
diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
index cb13e75d2f..446912d771 100644
--- a/hw/pci-host/gpex-acpi.c
+++ b/hw/pci-host/gpex-acpi.c
@@ -146,6 +146,8 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
Aml *method, *crs, *dev, *rbuf;
PCIBus *bus = cfg->bus;
CrsRangeSet crs_range_set;
+ CrsRangeEntry *entry;
+ int i;
/* start to construct the tables for pxb */
crs_range_set_init(&crs_range_set);
@@ -193,7 +195,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(scope, dev);
}
}
- crs_range_set_free(&crs_range_set);
/* tables for the main */
dev = aml_device("%s", "PCI0");
@@ -211,36 +212,55 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(method, aml_return(aml_int(cfg->ecam.base)));
aml_append(dev, method);
+ /*
+ * At this point crs_range_set has all the ranges used by pci
+ * busses *other* than PCI0. These ranges will be excluded from
+ * the PCI0._CRS.
+ */
rbuf = aml_resource_template();
aml_append(rbuf,
aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
nr_pcie_buses));
if (cfg->mmio32.size) {
- aml_append(rbuf,
- aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
- cfg->mmio32.base,
- cfg->mmio32.base + cfg->mmio32.size - 1,
- 0x0000,
- cfg->mmio32.size));
+ crs_replace_with_free_ranges(crs_range_set.mem_ranges,
+ cfg->mmio32.base,
+ cfg->mmio32.base + cfg->mmio32.size - 1);
+ for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
+ entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
+ aml_append(rbuf,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
+ entry->base, entry->limit,
+ 0x0000, entry->limit - entry->base + 1));
+ }
}
if (cfg->pio.size) {
- aml_append(rbuf,
- aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- AML_ENTIRE_RANGE, 0x0000, 0x0000,
- cfg->pio.size - 1,
- cfg->pio.base,
- cfg->pio.size));
+ crs_replace_with_free_ranges(crs_range_set.io_ranges,
+ 0x0000,
+ cfg->pio.size - 1);
+ for (i = 0; i < crs_range_set.io_ranges->len; i++) {
+ entry = g_ptr_array_index(crs_range_set.io_ranges, i);
+ aml_append(rbuf,
+ aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
+ AML_ENTIRE_RANGE, 0x0000, entry->base,
+ entry->limit, cfg->pio.base,
+ entry->limit - entry->base + 1));
+ }
}
if (cfg->mmio64.size) {
- aml_append(rbuf,
- aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
- AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
- cfg->mmio64.base,
- cfg->mmio64.base + cfg->mmio64.size - 1,
- 0x0000,
- cfg->mmio64.size));
+ crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
+ cfg->mmio64.base,
+ cfg->mmio64.base + cfg->mmio64.size - 1);
+ for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
+ entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
+ aml_append(rbuf,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
+ entry->base,
+ entry->limit, 0x0000,
+ entry->limit - entry->base + 1));
+ }
}
aml_append(dev, aml_name_decl("_CRS", rbuf));
@@ -259,4 +279,6 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
aml_append(dev_res0, aml_name_decl("_CRS", crs));
aml_append(dev, dev_res0);
aml_append(scope, dev);
+
+ crs_range_set_free(&crs_range_set);
}
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 6/8] Kconfig: Compile PXB for ARM_VIRT
2021-01-14 10:06 [PATCH v5 0/8] acpi: Some fixes for pxb support for ARM virt machine Jiahui Cen
` (4 preceding siblings ...)
2021-01-14 10:06 ` [PATCH v5 5/8] acpi/gpex: Exclude pxb's resources from PCI0 Jiahui Cen
@ 2021-01-14 10:06 ` Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 7/8] acpi: Enable pxb unit-test for ARM virt machine Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 8/8] acpi: Update _DSM method in expected files Jiahui Cen
7 siblings, 0 replies; 9+ messages in thread
From: Jiahui Cen @ 2021-01-14 10:06 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, Jiahui Cen, Eduardo Habkost, Michael S. Tsirkin,
Ard Biesheuvel, Richard Henderson, Paolo Bonzini, Igor Mammedov,
Laszlo Ersek, wu.wubin
PXB is now supported on ARM, so let's compile for arm_virt machine.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
hw/pci-bridge/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-bridge/Kconfig b/hw/pci-bridge/Kconfig
index a51ec716f5..f8df4315ba 100644
--- a/hw/pci-bridge/Kconfig
+++ b/hw/pci-bridge/Kconfig
@@ -5,7 +5,7 @@ config PCIE_PORT
config PXB
bool
- default y if Q35
+ default y if Q35 || ARM_VIRT
config XIO3130
bool
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 7/8] acpi: Enable pxb unit-test for ARM virt machine
2021-01-14 10:06 [PATCH v5 0/8] acpi: Some fixes for pxb support for ARM virt machine Jiahui Cen
` (5 preceding siblings ...)
2021-01-14 10:06 ` [PATCH v5 6/8] Kconfig: Compile PXB for ARM_VIRT Jiahui Cen
@ 2021-01-14 10:06 ` Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 8/8] acpi: Update _DSM method in expected files Jiahui Cen
7 siblings, 0 replies; 9+ messages in thread
From: Jiahui Cen @ 2021-01-14 10:06 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, Jiahui Cen, Eduardo Habkost, Michael S. Tsirkin,
Ard Biesheuvel, Richard Henderson, Paolo Bonzini, Igor Mammedov,
Laszlo Ersek, wu.wubin
No matter whether the pxb is enabled or not, the CONFIG_PXB macro in test
would keep undefined. And since pxb is now enabled for ARM Virt machine
by default, let's enable pxb unit-test by removing the CONFIG_PXB.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
tests/qtest/bios-tables-test.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 4e026f90d0..669202fc95 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1196,7 +1196,6 @@ static void test_acpi_virt_tcg_numamem(void)
}
-#ifdef CONFIG_PXB
static void test_acpi_virt_tcg_pxb(void)
{
test_data data = {
@@ -1228,7 +1227,6 @@ static void test_acpi_virt_tcg_pxb(void)
free_test_data(&data);
}
-#endif
static void test_acpi_tcg_acpi_hmat(const char *machine)
{
@@ -1342,9 +1340,7 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem);
qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
-#ifdef CONFIG_PXB
qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
-#endif
}
ret = g_test_run();
boot_sector_cleanup(disk);
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 8/8] acpi: Update _DSM method in expected files
2021-01-14 10:06 [PATCH v5 0/8] acpi: Some fixes for pxb support for ARM virt machine Jiahui Cen
` (6 preceding siblings ...)
2021-01-14 10:06 ` [PATCH v5 7/8] acpi: Enable pxb unit-test for ARM virt machine Jiahui Cen
@ 2021-01-14 10:06 ` Jiahui Cen
7 siblings, 0 replies; 9+ messages in thread
From: Jiahui Cen @ 2021-01-14 10:06 UTC (permalink / raw)
To: qemu-devel
Cc: xieyingtai, Jiahui Cen, Eduardo Habkost, Michael S. Tsirkin,
Ard Biesheuvel, Richard Henderson, Paolo Bonzini, Igor Mammedov,
Laszlo Ersek, wu.wubin
A new _DSM #5 method is added.
Update expected DSDT files accordingly, and re-enable their testing.
Full diff of changed files disassembly:
tests/data/acpi/microvm/DSDT.pcie.dsl:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/microvm/DSDT.pcie, Thu Jan 14 13:39:35 2021
+ * Disassembly of tests/data/acpi/microvm/DSDT.pcie, Thu Jan 14 13:51:13 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00000BCF (3023)
+ * Length 0x00000BD7 (3031)
* Revision 0x02
- * Checksum 0x29
+ * Checksum 0x99
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -1302,9 +1302,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
tests/data/acpi/virt/DSDT.dsl:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/virt/DSDT, Thu Jan 14 13:39:35 2021
+ * Disassembly of tests/data/acpi/virt/DSDT, Thu Jan 14 13:51:13 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x0000144C (5196)
+ * Length 0x00001454 (5204)
* Revision 0x02
- * Checksum 0xF0
+ * Checksum 0x60
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -1838,9 +1838,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
tests/data/acpi/virt/DSDT.memhp.dsl:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/virt/DSDT.memhp, Thu Jan 14 13:39:35 2021
+ * Disassembly of tests/data/acpi/virt/DSDT.memhp, Thu Jan 14 13:51:13 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x0000199D (6557)
+ * Length 0x000019A5 (6565)
* Revision 0x02
- * Checksum 0x11
+ * Checksum 0x90
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -1840,9 +1840,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
tests/data/acpi/virt/DSDT.numamem.dsl:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/virt/DSDT.numamem, Thu Jan 14 13:39:35 2021
+ * Disassembly of tests/data/acpi/virt/DSDT.numamem, Thu Jan 14 13:51:13 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x0000144C (5196)
+ * Length 0x00001454 (5204)
* Revision 0x02
- * Checksum 0xF0
+ * Checksum 0x60
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -1838,9 +1838,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
tests/data/acpi/virt/DSDT.pxb.dsl:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/virt/DSDT.pxb, Thu Jan 14 13:39:35 2021
+ * Disassembly of tests/data/acpi/virt/DSDT.pxb, Thu Jan 14 13:51:13 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00001DF9 (7673)
+ * Length 0x00001E09 (7689)
* Revision 0x02
- * Checksum 0x42
+ * Checksum 0x30
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x00000001 (1)
@@ -1810,9 +1810,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
@@ -3025,9 +3030,14 @@
{
Return (Buffer (One)
{
- 0x01 // .
+ 0x21 // !
})
}
+
+ If ((Arg2 == 0x05))
+ {
+ Return (Zero)
+ }
}
Return (Buffer (One)
Acked-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
---
tests/data/acpi/microvm/DSDT.pcie | Bin 3023 -> 3031 bytes
tests/data/acpi/virt/DSDT | Bin 5196 -> 5204 bytes
tests/data/acpi/virt/DSDT.memhp | Bin 6557 -> 6565 bytes
tests/data/acpi/virt/DSDT.numamem | Bin 5196 -> 5204 bytes
tests/data/acpi/virt/DSDT.pxb | Bin 7673 -> 7689 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 5 -----
6 files changed, 5 deletions(-)
diff --git a/tests/data/acpi/microvm/DSDT.pcie b/tests/data/acpi/microvm/DSDT.pcie
index 4b765541e372f4ba4e25529c14acf696516c8f61..e590b98f9960025f75dd0544492d3088781406dc 100644
GIT binary patch
delta 59
zcmV-B0L1^#7uOdGL{mgm*9!mu0-2Et8v;SPu_reH0Z6l70pke>HD5$iO$4ARlS&I8
R2_c{dlWGbDqyUp@3uOk*5ZC|!
delta 51
zcmcaEeqNl*CD<k8JU0UaljcM&X(rE|8`aGj867sqGd||z(2aKq_GMY1IN6I^o{@2K
H5qBy8b(js<
diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT
index bc519abff9cadc1552e4e586b0a3f5f0db498f4a..ea8a0869af1637ab75fe335e100256a2acf85e16 100644
GIT binary patch
delta 58
zcmX@3aYcj6CD<h-M1+BXDPba)G-LlpHAzk;w-t*WIk`AY<6VM%Sr%wc_7s-qR9wJ5
OIg5*R3B%+};l}{T<qzlp
delta 50
zcmcbjaYlp7CD<jzM}&ca>BB@WX~y=AYLc8xe#;j-a&mF##=8XjvMf-X>?thI$T+!B
G_%Q%yeGTXU
diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp
index 54728e2b4b8b959f3f829386f6a388ef2600e747..897648637cc6c8af47c67a9a349477c0240f833b 100644
GIT binary patch
delta 60
zcmV-C0K@;CGo>>ML{mgmr5OMK0+5jk8v=lsu_qV_0!FB#K?w>7HD5$iO$4ARlSvaF
S2_c{dlWGbDqyV#N6Ep_<;t(eQ
delta 52
zcmZ2#JlB}ZCD<iot|S8kli)-yX{L_p8`UK^nf#V7cI4#Z(2aKq_GMY1IN4KJo{@2L
Ip|A-X0Bmp#CjbBd
diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSDT.numamem
index bc519abff9cadc1552e4e586b0a3f5f0db498f4a..ea8a0869af1637ab75fe335e100256a2acf85e16 100644
GIT binary patch
delta 58
zcmX@3aYcj6CD<h-M1+BXDPba)G-LlpHAzk;w-t*WIk`AY<6VM%Sr%wc_7s-qR9wJ5
OIg5*R3B%+};l}{T<qzlp
delta 50
zcmcbjaYlp7CD<jzM}&ca>BB@WX~y=AYLc8xe#;j-a&mF##=8XjvMf-X>?thI$T+!B
G_%Q%yeGTXU
diff --git a/tests/data/acpi/virt/DSDT.pxb b/tests/data/acpi/virt/DSDT.pxb
index 76f5f1c2fd487644c6b4f827a70ad770edb9fdc9..ce3b67dff277e23f43925b1adcbb55c9d0b4eee3 100644
GIT binary patch
delta 95
zcmexq-D$(+66_MfDaXLTWH6CShVkA;bqP);=h>SbIcqpMOygaGeOVT0PW~n%FQmAD
ieR38T>k@_~g3OEz(M@hE7QYkXLQ%sBS2I~m_AvnX%^QRO
delta 79
zcmeCQ`DxAN66_N4Q<i~&$!Q{&4CCF6>Jpqx-m^A4a@KHi=*GJQ`?4%hocvElo{Mpb
ZATuLFbd%rm#ovUuP~;dHC#%Um1^}tB7n}e9
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index 42418e58e7..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,6 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/microvm/DSDT.pcie",
-"tests/data/acpi/virt/DSDT",
-"tests/data/acpi/virt/DSDT.memhp",
-"tests/data/acpi/virt/DSDT.numamem",
-"tests/data/acpi/virt/DSDT.pxb",
--
2.29.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-01-14 10:14 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-14 10:06 [PATCH v5 0/8] acpi: Some fixes for pxb support for ARM virt machine Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 1/8] acpi: Allow DSDT acpi table changes Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 2/8] acpi: Fix unmatched expected DSDT.pxb file Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 3/8] acpi: Add addr offset in build_crs Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 4/8] acpi/gpex: Inform os to keep firmware resource map Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 5/8] acpi/gpex: Exclude pxb's resources from PCI0 Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 6/8] Kconfig: Compile PXB for ARM_VIRT Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 7/8] acpi: Enable pxb unit-test for ARM virt machine Jiahui Cen
2021-01-14 10:06 ` [PATCH v5 8/8] acpi: Update _DSM method in expected files Jiahui Cen
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