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[83.57.169.13]) by smtp.gmail.com with ESMTPSA id p8sm11339706wru.50.2021.01.14.08.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 08:20:39 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Subject: [PULL v2 32/69] target/mips: Declare generic FPU / Coprocessor functions in translate.h Date: Thu, 14 Jan 2021 17:20:03 +0100 Message-Id: <20210114162016.2901557-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210114162016.2901557-1-f4bug@amsat.org> References: <20210114162016.2901557-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Richard Henderson , qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Some FPU / Coprocessor translation functions / registers can be used by ISA / ASE / extensions out of the big translate.c file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20201214183739.500368-15-f4bug@amsat.org> --- target/mips/translate.h | 12 ++++++++++++ target/mips/translate.c | 24 ++++++++++++------------ 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index 98cadffe4e5..a3f4a56750d 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -61,16 +61,28 @@ void check_insn(DisasContext *ctx, uint64_t flags); #ifdef TARGET_MIPS64 void check_mips_64(DisasContext *ctx); #endif +void check_cp0_enabled(DisasContext *ctx); +void check_cp1_enabled(DisasContext *ctx); +void check_cp1_64bitmode(DisasContext *ctx); +void check_cp1_registers(DisasContext *ctx, int regs); +void check_cop1x(DisasContext *ctx); void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset); void gen_move_low32(TCGv ret, TCGv_i64 arg); void gen_move_high32(TCGv ret, TCGv_i64 arg); void gen_load_gpr(TCGv t, int reg); void gen_store_gpr(TCGv t, int reg); +void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg); +void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); +void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg); +void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); +int get_fp_bit(int cc); void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1); extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv_i32 fpu_fcr0, fpu_fcr31; +extern TCGv_i64 fpu_f64[32]; extern TCGv bcond; #define LOG_DISAS(...) \ diff --git a/target/mips/translate.c b/target/mips/translate.c index d7767215050..9b822344a2e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2492,8 +2492,8 @@ static TCGv cpu_dspctrl, btarget; TCGv bcond; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; -static TCGv_i32 fpu_fcr0, fpu_fcr31; -static TCGv_i64 fpu_f64[32]; +TCGv_i32 fpu_fcr0, fpu_fcr31; +TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; #if defined(TARGET_MIPS64) @@ -2768,7 +2768,7 @@ void gen_reserved_instruction(DisasContext *ctx) } /* Floating point register moves. */ -static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) +void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) { if (ctx->hflags & MIPS_HFLAG_FRE) { generate_exception(ctx, EXCP_RI); @@ -2776,7 +2776,7 @@ static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) tcg_gen_extrl_i64_i32(t, fpu_f64[reg]); } -static void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) +void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) { TCGv_i64 t64; if (ctx->hflags & MIPS_HFLAG_FRE) { @@ -2809,7 +2809,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) } } -static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { tcg_gen_mov_i64(t, fpu_f64[reg]); @@ -2818,7 +2818,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) } } -static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { tcg_gen_mov_i64(fpu_f64[reg], t); @@ -2832,7 +2832,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) } } -static inline int get_fp_bit(int cc) +int get_fp_bit(int cc) { if (cc) { return 24 + cc; @@ -2899,14 +2899,14 @@ void gen_move_high32(TCGv ret, TCGv_i64 arg) #endif } -static inline void check_cp0_enabled(DisasContext *ctx) +void check_cp0_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { generate_exception_end(ctx, EXCP_CpU); } } -static inline void check_cp1_enabled(DisasContext *ctx) +void check_cp1_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { generate_exception_err(ctx, EXCP_CpU, 1); @@ -2918,7 +2918,7 @@ static inline void check_cp1_enabled(DisasContext *ctx) * This is associated with the nabla symbol in the MIPS32 and MIPS64 * opcode tables. */ -static inline void check_cop1x(DisasContext *ctx) +void check_cop1x(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { gen_reserved_instruction(ctx); @@ -2929,7 +2929,7 @@ static inline void check_cop1x(DisasContext *ctx) * Verify that the processor is running with 64-bit floating-point * operations enabled. */ -static inline void check_cp1_64bitmode(DisasContext *ctx) +void check_cp1_64bitmode(DisasContext *ctx) { if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) { gen_reserved_instruction(ctx); @@ -2947,7 +2947,7 @@ static inline void check_cp1_64bitmode(DisasContext *ctx) * Multiple 64 bit wide registers can be checked by calling * gen_op_cp1_registers(freg1 | freg2 | ... | fregN); */ -static inline void check_cp1_registers(DisasContext *ctx, int regs) +void check_cp1_registers(DisasContext *ctx, int regs) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { gen_reserved_instruction(ctx); -- 2.26.2