From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: [intel-linux-intel-lts:5.4/yocto 1/13] drivers/mtd/spi-nor/core.c:3383:34: sparse: sparse: cast to restricted __le32
Date: Thu, 14 Jan 2021 20:14:47 +0800 [thread overview]
Message-ID: <202101142036.Xqja9Yjp-lkp@intel.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 23983 bytes --]
Hi Boris,
First bad commit (maybe != root cause):
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto
head: 756623e2f190038a96e780f5f07990a065ebf2b9
commit: 4541b62447f9a65c9192597304d5f6cd11664386 [1/13] mtd: spi-nor: Prepare core / manufacturer code split
config: i386-randconfig-s001-20210114 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce:
# apt-get install sparse
# sparse version: v0.6.3-208-g46a52ca4-dirty
# https://github.com/intel/linux-intel-lts/commit/4541b62447f9a65c9192597304d5f6cd11664386
git remote add intel-linux-intel-lts https://github.com/intel/linux-intel-lts.git
git fetch --no-tags intel-linux-intel-lts 5.4/yocto
git checkout 4541b62447f9a65c9192597304d5f6cd11664386
# save the attached .config to linux build tree
make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
"sparse warnings: (new ones prefixed by >>)"
>> drivers/mtd/spi-nor/core.c:3383:34: sparse: sparse: cast to restricted __le32
>> drivers/mtd/spi-nor/core.c:3651:38: sparse: sparse: dubious: x | !y
drivers/mtd/spi-nor/core.c:3837:27: sparse: sparse: cast to restricted __le32
drivers/mtd/spi-nor/core.c:3931:29: sparse: sparse: cast to restricted __le32
drivers/mtd/spi-nor/core.c:4071:13: sparse: sparse: cast to restricted __le32
vim +3383 drivers/mtd/spi-nor/core.c
2aaa5f7e0c07a0f1 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2018-12-06 3324
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3325 /**
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3326 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table.
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3327 * @nor: pointer to a 'struct spi_nor'
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3328 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3329 * the Basic Flash Parameter Table length and version
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3330 * @params: pointer to the 'struct spi_nor_flash_parameter' to be
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3331 * filled
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3332 *
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3333 * The Basic Flash Parameter Table is the main and only mandatory table as
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3334 * defined by the SFDP (JESD216) specification.
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3335 * It provides us with the total size (memory density) of the data array and
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3336 * the number of address bytes for Fast Read, Page Program and Sector Erase
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3337 * commands.
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3338 * For Fast READ commands, it also gives the number of mode clock cycles and
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3339 * wait states (regrouped in the number of dummy clock cycles) for each
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3340 * supported instruction op code.
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3341 * For Page Program, the page size is now available since JESD216 rev A, however
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3342 * the supported instruction op codes are still not provided.
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3343 * For Sector Erase commands, this table stores the supported instruction op
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3344 * codes and the associated sector sizes.
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3345 * Finally, the Quad Enable Requirements (QER) are also available since JESD216
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3346 * rev A. The QER bits encode the manufacturer dependent procedure to be
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3347 * executed to set the Quad Enable (QE) bit in some internal register of the
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3348 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3349 * sending any Quad SPI command to the memory. Actually, setting the QE bit
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3350 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3351 * and IO3 hence enabling 4 (Quad) I/O lines.
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3352 *
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3353 * Return: 0 on success, -errno otherwise.
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3354 */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3355 static int spi_nor_parse_bfpt(struct spi_nor *nor,
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3356 const struct sfdp_parameter_header *bfpt_header,
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3357 struct spi_nor_flash_parameter *params)
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3358 {
c46872170a54c902 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2019-08-23 3359 struct spi_nor_erase_map *map = ¶ms->erase_map;
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3360 struct spi_nor_erase_type *erase_type = map->erase_type;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3361 struct sfdp_bfpt bfpt;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3362 size_t len;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3363 int i, cmd, err;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3364 u32 addr;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3365 u16 half;
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3366 u8 erase_mask;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3367
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3368 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3369 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3370 return -EINVAL;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3371
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3372 /* Read the Basic Flash Parameter Table. */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3373 len = min_t(size_t, sizeof(bfpt),
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3374 bfpt_header->length * sizeof(u32));
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3375 addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3376 memset(&bfpt, 0, sizeof(bfpt));
bfa4133795e5a0ba drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-09-06 3377 err = spi_nor_read_sfdp_dma_unsafe(nor, addr, len, &bfpt);
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3378 if (err < 0)
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3379 return err;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3380
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3381 /* Fix endianness of the BFPT DWORDs. */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3382 for (i = 0; i < BFPT_DWORD_MAX; i++)
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 @3383 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3384
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3385 /* Number of address bytes. */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3386 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3387 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3388 nor->addr_width = 3;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3389 break;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3390
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3391 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3392 nor->addr_width = 4;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3393 break;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3394
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3395 default:
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3396 break;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3397 }
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3398
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3399 /* Flash Memory Density (in bits). */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3400 params->size = bfpt.dwords[BFPT_DWORD(2)];
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3401 if (params->size & BIT(31)) {
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3402 params->size &= ~BIT(31);
b8f3911610529ba5 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 3403
b8f3911610529ba5 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 3404 /*
b8f3911610529ba5 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 3405 * Prevent overflows on params->size. Anyway, a NOR of 2^64
b8f3911610529ba5 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 3406 * bits is unlikely to exist so this error probably means
b8f3911610529ba5 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 3407 * the BFPT we are reading is corrupted/wrong.
b8f3911610529ba5 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 3408 */
b8f3911610529ba5 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 3409 if (params->size > 63)
b8f3911610529ba5 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 3410 return -EINVAL;
b8f3911610529ba5 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2017-09-12 3411
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3412 params->size = 1ULL << params->size;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3413 } else {
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3414 params->size++;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3415 }
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3416 params->size >>= 3; /* Convert to bytes. */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3417
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3418 /* Fast Read settings. */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3419 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) {
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3420 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i];
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3421 struct spi_nor_read_command *read;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3422
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3423 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) {
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3424 params->hwcaps.mask &= ~rd->hwcaps;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3425 continue;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3426 }
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3427
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3428 params->hwcaps.mask |= rd->hwcaps;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3429 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps);
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3430 read = ¶ms->reads[cmd];
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3431 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3432 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto);
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3433 }
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3434
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3435 /*
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3436 * Sector Erase settings. Reinitialize the uniform erase map using the
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3437 * Erase Types defined in the bfpt table.
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3438 */
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3439 erase_mask = 0;
c46872170a54c902 drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2019-08-23 3440 memset(¶ms->erase_map, 0, sizeof(params->erase_map));
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3441 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) {
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3442 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i];
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3443 u32 erasesize;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3444 u8 opcode;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3445
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3446 half = bfpt.dwords[er->dword] >> er->shift;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3447 erasesize = half & 0xff;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3448
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3449 /* erasesize == 0 means this Erase Type is not supported. */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3450 if (!erasesize)
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3451 continue;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3452
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3453 erasesize = 1U << erasesize;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3454 opcode = (half >> 8) & 0xff;
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3455 erase_mask |= BIT(i);
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3456 spi_nor_set_erase_settings_from_bfpt(&erase_type[i], erasesize,
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3457 opcode, i);
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3458 }
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3459 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3460 /*
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3461 * Sort all the map's Erase Types in ascending order with the smallest
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3462 * erase size being the first member in the erase_type array.
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3463 */
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3464 sort(erase_type, SNOR_ERASE_TYPE_MAX, sizeof(erase_type[0]),
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3465 spi_nor_map_cmp_erase_type, NULL);
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3466 /*
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3467 * Sort the erase types in the uniform region in order to update the
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3468 * uniform_erase_type bitmask. The bitmask will be used later on when
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3469 * selecting the uniform erase.
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3470 */
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3471 spi_nor_regions_sort_erase_types(map);
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3472 map->uniform_erase_type = map->uniform_region.offset &
5390a8df769ec9ba drivers/mtd/spi-nor/spi-nor.c Tudor Ambarus 2018-09-11 3473 SNOR_ERASE_TYPE_MASK;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3474
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3475 /* Stop here if not JESD216 rev A or later. */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3476 if (bfpt_header->length < BFPT_DWORD_MAX)
2aaa5f7e0c07a0f1 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2018-12-06 3477 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
2aaa5f7e0c07a0f1 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2018-12-06 3478 params);
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3479
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3480 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3481 params->page_size = bfpt.dwords[BFPT_DWORD(11)];
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3482 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3483 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3484 params->page_size = 1U << params->page_size;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3485
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3486 /* Quad Enable Requirements. */
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3487 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3488 case BFPT_DWORD15_QER_NONE:
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3489 params->quad_enable = NULL;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3490 break;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3491
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3492 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3493 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3494 params->quad_enable = spansion_no_read_cr_quad_enable;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3495 break;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3496
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3497 case BFPT_DWORD15_QER_SR1_BIT6:
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3498 params->quad_enable = macronix_quad_enable;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3499 break;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3500
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3501 case BFPT_DWORD15_QER_SR2_BIT7:
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3502 params->quad_enable = sr2_bit7_quad_enable;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3503 break;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3504
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3505 case BFPT_DWORD15_QER_SR2_BIT1:
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3506 params->quad_enable = spansion_read_cr_quad_enable;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3507 break;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3508
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3509 default:
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3510 return -EINVAL;
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3511 }
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3512
2aaa5f7e0c07a0f1 drivers/mtd/spi-nor/spi-nor.c Boris Brezillon 2018-12-06 3513 return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3514 }
f384b352cbf0310f drivers/mtd/spi-nor/spi-nor.c Cyrille Pitchen 2017-06-26 3515
:::::: The code at line 3383 was first introduced by commit
:::::: f384b352cbf0310fd20c379c4710408c70e769b6 mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables
:::::: TO: Cyrille Pitchen <cyrille.pitchen@microchip.com>
:::::: CC: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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next reply other threads:[~2021-01-14 12:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-14 12:14 kernel test robot [this message]
2021-04-12 14:17 [intel-linux-intel-lts:5.4/yocto 1/13] drivers/mtd/spi-nor/core.c:3383:34: sparse: sparse: cast to restricted __le32 kernel test robot
2021-06-10 14:38 kernel test robot
2021-08-20 12:42 kernel test robot
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