From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57F66C43381 for ; Mon, 18 Jan 2021 15:57:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1BFA822472 for ; Mon, 18 Jan 2021 15:57:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406101AbhARP5Q (ORCPT ); Mon, 18 Jan 2021 10:57:16 -0500 Received: from foss.arm.com ([217.140.110.172]:38426 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2405992AbhARPyO (ORCPT ); Mon, 18 Jan 2021 10:54:14 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EC96E31B; Mon, 18 Jan 2021 07:53:28 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 061FA3F68F; Mon, 18 Jan 2021 07:53:26 -0800 (PST) Date: Mon, 18 Jan 2021 15:52:28 +0000 From: Andre Przywara To: Maxime Ripard Cc: Chen-Yu Tsai , Jernej Skrabec , Icenowy Zheng , Linus Walleij , Rob Herring , =?UTF-8?B?Q2zDqW1lbnQgUMOpcm9u?= , Samuel Holland , Shuosheng Huang , Yangtao Li , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Ulf Hansson Subject: Re: [PATCH v3 02/21] mmc: sunxi: add support for A100 mmc controller Message-ID: <20210118155228.3bd0e909@slackpad.fritz.box> In-Reply-To: <20210118132854.yiwn7rnvcyexgqim@gilmour> References: <20210118020848.11721-1-andre.przywara@arm.com> <20210118020848.11721-3-andre.przywara@arm.com> <20210118132854.yiwn7rnvcyexgqim@gilmour> Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 18 Jan 2021 14:28:54 +0100 Maxime Ripard wrote: Hi Maxime, > On Mon, Jan 18, 2021 at 02:08:29AM +0000, Andre Przywara wrote: > > From: Yangtao Li > > > > This patch adds support for A100 MMC controller, which use word > > address for internal dma. > > > > Signed-off-by: Yangtao Li > > Signed-off-by: Andre Przywara > > We should also disable the timings setup in probe to derive them from > the DT. This is causing issues on some SoCs already, so it would be > best to not make the situation worse But only for those new SoCs, where we have the speed modes in the DT in every case (so only new ones)? And this disabling would be SoC/compatible string dependent? Happy to send a patch later if that is what you were thinking about. Also I was wondering about the voltage dependent speed modes: At the moment the driver declares both MMC_CAP_1_8V_DDR and MMC_CAP_3_3V_DDR, so I mimic this in the .dtsi. However in the eventual DTB this looks somewhat dodgy, since most boards only support one of those voltages. Do we ignore this, and rely on the vqmmc-supply to limit this choice? Cheers, Andre Btw: This patch is already in Ulf's -next tree, I just included it here for the sake of completeness. Is that a problem? I don't think it affects the build, so we don't care too much? From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF419C433DB for ; Mon, 18 Jan 2021 15:55:01 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3F9B22472 for ; Mon, 18 Jan 2021 15:55:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A3F9B22472 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=eHDdiP8AvY4VEUdH3+KnJYvI3cravqAfHKYZEDrQGfc=; b=NjAV9yeQdgd90ILNWFfyzAuvO 1QaRG0NQFmVFZ4+8sQHAA1TQWmy4kol8snnU9MsIOQG92TwPzk3HO9O1EbxMl2s/lPXBszDHlpgXe cN4iywrqCOD/hHXpGLNaSnpQRQwX+U0Gk0b6MciYlP+oM8cY+CJ9sCs6sb2+w78MQCwoD8juTVdk3 fx5/0UgycnaVXOZqkr/gGhM3vWwLe1obqBLonvAE/YwY4EeUpE1D6qMG1dquHyGJrSInEGKiXk7Xt 5zZ11FgLjKyiHwI7xDGc+AeHjhY7dVw13gTcrv9gv1Lg1tRM7kl8osuqLplhCR98DEBavij1gdWu9 RqXMGDo1w==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l1Wqh-00008i-4t; Mon, 18 Jan 2021 15:53:47 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l1WqP-0008Sq-QQ for linux-arm-kernel@lists.infradead.org; Mon, 18 Jan 2021 15:53:30 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EC96E31B; Mon, 18 Jan 2021 07:53:28 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 061FA3F68F; Mon, 18 Jan 2021 07:53:26 -0800 (PST) Date: Mon, 18 Jan 2021 15:52:28 +0000 From: Andre Przywara To: Maxime Ripard Subject: Re: [PATCH v3 02/21] mmc: sunxi: add support for A100 mmc controller Message-ID: <20210118155228.3bd0e909@slackpad.fritz.box> In-Reply-To: <20210118132854.yiwn7rnvcyexgqim@gilmour> References: <20210118020848.11721-1-andre.przywara@arm.com> <20210118020848.11721-3-andre.przywara@arm.com> <20210118132854.yiwn7rnvcyexgqim@gilmour> Organization: Arm Ltd. X-Mailer: Claws Mail 3.17.1 (GTK+ 2.24.31; x86_64-slackware-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210118_105329_938040_57DB6503 X-CRM114-Status: GOOD ( 19.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jernej Skrabec , Samuel Holland , Yangtao Li , Linus Walleij , linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, Chen-Yu Tsai , =?UTF-8?B?Q2zDqW1lbnQgUMOpcm9u?= , Shuosheng Huang , Ulf Hansson , linux-arm-kernel@lists.infradead.org, Icenowy Zheng Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, 18 Jan 2021 14:28:54 +0100 Maxime Ripard wrote: Hi Maxime, > On Mon, Jan 18, 2021 at 02:08:29AM +0000, Andre Przywara wrote: > > From: Yangtao Li > > > > This patch adds support for A100 MMC controller, which use word > > address for internal dma. > > > > Signed-off-by: Yangtao Li > > Signed-off-by: Andre Przywara > > We should also disable the timings setup in probe to derive them from > the DT. This is causing issues on some SoCs already, so it would be > best to not make the situation worse But only for those new SoCs, where we have the speed modes in the DT in every case (so only new ones)? And this disabling would be SoC/compatible string dependent? Happy to send a patch later if that is what you were thinking about. Also I was wondering about the voltage dependent speed modes: At the moment the driver declares both MMC_CAP_1_8V_DDR and MMC_CAP_3_3V_DDR, so I mimic this in the .dtsi. However in the eventual DTB this looks somewhat dodgy, since most boards only support one of those voltages. Do we ignore this, and rely on the vqmmc-supply to limit this choice? Cheers, Andre Btw: This patch is already in Ulf's -next tree, I just included it here for the sake of completeness. Is that a problem? I don't think it affects the build, so we don't care too much? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel