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Tue, 19 Jan 2021 05:15:06 -0500 (EST) From: Klaus Jensen To: qemu-devel@nongnu.org Subject: [PATCH v3 00/12] hw/block/nvme: misc cmb/pmr patches and bump to v1.4 Date: Tue, 19 Jan 2021 11:14:52 +0100 Message-Id: <20210119101504.231259-1-its@irrelevant.dk> X-Mailer: git-send-email 2.30.0 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=64.147.123.25; envelope-from=its@irrelevant.dk; helo=wout2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen =0D This is a resend of "hw/block/nvme: allow cmb and pmr to coexist" with=0D some more PMR work added (PMR RDS/WDS support).=0D =0D This includes a resurrection of Andrzej's series[1] from back July.=0D =0D Andrzej's main patch basically moved the CMB from BAR 2 into an offset=0D in BAR 4 (located after the MSI-X table and PBA). Having an offset on=0D the CMB causes a bunch of calculations related to address mapping to=0D change.=0D =0D So, since I couldn't get the patch to apply cleanly I took a stab at=0D implementing the suggestion I originally came up with: simply move the=0D MSI-X table and PBA from BAR 4 into BAR 0 (up-aligned to a 4 KiB=0D boundary after the main NVMe controller registers). This way we can keep=0D the CMB at offset zero in its own BAR and free up BAR 4 for use by PMR.=0D This makes the patch simpler and does not impact any of the existing=0D address mapping code.=0D =0D [1]: https://lore.kernel.org/qemu-devel/20200729220107.37758-1-andrzej.ja= kowski@linux.intel.com/=0D =0D Changes for v3=0D ~~~~~~~~~~~~~~=0D =0D - Fix a masking bug in "hw/block/nvme: fix 64 bit register hi/lo split=0D writes" (Minwoo)=0D - Restore a deleted comment in "hw/block/nvme: remove redundant=0D zeroing of PMR registers" (Minwoo)=0D - Restore the 'legacy-cmb' parameter from v1 to allow the device to=0D exhibit the v1.3 CMB behavior.=0D =0D Changes for v2=0D ~~~~~~~~~~~~~~=0D =0D - Rebased on nvme-next=0D - Added a fix for 64 bit register hi/lo split writes=0D - Added the patches from "hw/block/nvme: cmb enhancements and bump to=0D v1.4" to the back of this.=0D - As suggested by Keith, I removed "legacy CMB" support - the patch=0D now exclusively bumps the support to the "v1.4 variant", so the=0D linux kernel nvme gang have to get their game on ;)=0D =0D Andrzej Jakowski (1):=0D hw/block/nvme: indicate CMB support through controller capabilities=0D register=0D =0D Klaus Jensen (9):=0D hw/block/nvme: add size to mmio read/write trace events=0D hw/block/nvme: fix 64 bit register hi/lo split writes=0D hw/block/nvme: move msix table and pba to BAR 0=0D hw/block/nvme: allow cmb and pmr to coexist=0D hw/block/nvme: rename PMR/CMB shift/mask fields=0D hw/block/nvme: remove redundant zeroing of PMR registers=0D hw/block/nvme: disable PMR at boot up=0D hw/block/nvme: bump to v1.4=0D hw/block/nvme: lift cmb restrictions=0D =0D Naveen Nagar (1):=0D hw/block/nvme: add PMR RDS/WDS support=0D =0D Padmakar Kalghatgi (1):=0D hw/block/nvme: move cmb logic to v1.4=0D =0D hw/block/nvme.h | 17 +-=0D include/block/nvme.h | 125 +++++++++++++--=0D hw/block/nvme.c | 350 +++++++++++++++++++++++++++---------------=0D hw/block/trace-events | 6 +-=0D 4 files changed, 351 insertions(+), 147 deletions(-)=0D =0D -- =0D 2.30.0=0D =0D