From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79B73C282D1 for ; Tue, 19 Jan 2021 18:28:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A94922DFB for ; Tue, 19 Jan 2021 18:28:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387730AbhASRZI (ORCPT ); Tue, 19 Jan 2021 12:25:08 -0500 Received: from foss.arm.com ([217.140.110.172]:41494 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730082AbhASRZE (ORCPT ); Tue, 19 Jan 2021 12:25:04 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 978B011FB; Tue, 19 Jan 2021 09:24:17 -0800 (PST) Received: from bogus (unknown [10.57.35.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EE9B63F66E; Tue, 19 Jan 2021 09:24:14 -0800 (PST) Date: Tue, 19 Jan 2021 17:24:12 +0000 From: Sudeep Holla To: Dave Gerlach Cc: Nishanth Menon , devicetree@vger.kernel.org, Vignesh Raghavendra , Tony Lindgren , Sekhar Nori , Kishon Vijay Abraham , Lokesh Vutla , Rob Herring , Aswath Govindraju , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 3/5] arm64: dts: ti: Add support for AM642 SoC Message-ID: <20210119172412.smsjdo2sjzqi5vcn@bogus> References: <20210119163927.774-1-d-gerlach@ti.com> <20210119163927.774-4-d-gerlach@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210119163927.774-4-d-gerlach@ti.com> User-Agent: NeoMutt/20171215 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Jan 19, 2021 at 10:39:25AM -0600, Dave Gerlach wrote: > The AM642 SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration to enable applications such as > Motor Drives, PLC, Remote IO and IoT Gateways. > > Some highlights of this SoC are: > * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F > MCUs, and a single Cortex-M4F. > * Two Gigabit Industrial Communication Subsystems (ICSSG). > * Integrated Ethernet switch supporting up to a total of two external > ports. > * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory > controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other > peripherals. > * Centralized System Controller for Security, Power, and Resource > Management (DMSC). > > See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) > for further details: https://www.ti.com/lit/pdf/spruim2 > > Introduce basic support for the AM642 SoC to enable ramdisk or MMC > boot. Introduce the sdhci, i2c, spi, and uart MAIN domain periperhals > under cbass_main and the i2c, spi, and uart MCU domain periperhals > under cbass_mcu. > > Signed-off-by: Faiz Abbas > Signed-off-by: Aswath Govindraju > Signed-off-by: Dave Gerlach > --- > v1 -> v2: > * Add i2c. sdhci. and spi nodes to cbass_main > * Add cbass_mcu with uart, i2c, and spi nodes > * Add oc_sram node > * Add additional ranges for main_cbass to cover all use cases. > > arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 332 +++++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 76 ++++++ > arch/arm64/boot/dts/ti/k3-am64.dtsi | 103 +++++++ > arch/arm64/boot/dts/ti/k3-am642.dtsi | 65 +++++ > 4 files changed, 576 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-am64-main.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am64.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-am642.dtsi > > diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi > new file mode 100644 > index 000000000000..a35a0aff50f8 > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi > @@ -0,0 +1,103 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Device Tree Source for AM642 SoC Family > + * > + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +/ { > + model = "Texas Instruments K3 AM642 SoC"; > + compatible = "ti,am642"; > + interrupt-parent = <&gic500>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &mcu_uart0; > + serial1 = &mcu_uart1; > + serial2 = &main_uart0; > + serial3 = &main_uart1; > + serial4 = &main_uart2; > + serial5 = &main_uart3; > + serial6 = &main_uart4; > + serial7 = &main_uart5; > + serial8 = &main_uart6; > + }; > + > + chosen { }; > + > + firmware { > + optee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + }; > + > + psci: psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + }; > + > + a53_timer0: timer-cl0-cpu0 { > + compatible = "arm,armv8-timer"; > + interrupts = , /* cntpsirq */ > + , /* cntpnsirq */ > + , /* cntvirq */ > + ; /* cnthpirq */ > + }; > + > + pmu: pmu { > + compatible = "arm,armv8-pmuv3"; Is this just copy paste from some DTS or do we really don't know which CPU this platform has 😄 ? Reading further down, I thought it was Cortex A53, no ? -- Regards, Sudeep From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37672C433DB for ; Tue, 19 Jan 2021 20:16:19 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C44BE23107 for ; Tue, 19 Jan 2021 20:16:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter 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arm64: dts: ti: Add support for AM642 SoC Message-ID: <20210119172412.smsjdo2sjzqi5vcn@bogus> References: <20210119163927.774-1-d-gerlach@ti.com> <20210119163927.774-4-d-gerlach@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210119163927.774-4-d-gerlach@ti.com> User-Agent: NeoMutt/20171215 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210119_122421_207154_BE6C9009 X-CRM114-Status: GOOD ( 22.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , devicetree@vger.kernel.org, Vignesh Raghavendra , Tony Lindgren , Sekhar Nori , Kishon Vijay Abraham , Lokesh Vutla , Rob Herring , Aswath Govindraju , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: 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